| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Intel Atom platform clocks for BayTrail and CherryTrail SoC. |
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| 4 | * |
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| 5 | * Copyright (C) 2016, Intel Corporation |
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| 6 | * Author: Irina Tirdea <irina.tirdea@intel.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H |
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| 10 | #define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H |
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| 11 | |
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| 12 | /** |
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| 13 | * struct pmc_clk - PMC platform clock configuration |
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| 14 | * |
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| 15 | * @name: identified, typically pmc_plt_clk_<x>, x=[0..5] |
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| 16 | * @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported |
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| 17 | * @parent_name: one of 'xtal' or 'osc' |
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| 18 | */ |
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| 19 | struct pmc_clk { |
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| 20 | const char *name; |
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| 21 | unsigned long freq; |
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| 22 | const char *parent_name; |
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| 23 | }; |
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| 24 | |
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| 25 | /** |
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| 26 | * struct pmc_clk_data - common PMC clock configuration |
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| 27 | * |
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| 28 | * @base: PMC clock register base offset |
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| 29 | * @clks: pointer to set of registered clocks, typically 0..5 |
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| 30 | * @critical: flag to indicate if firmware enabled pmc_plt_clks |
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| 31 | * should be marked as critial or not |
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| 32 | */ |
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| 33 | struct pmc_clk_data { |
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| 34 | void __iomem *base; |
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| 35 | const struct pmc_clk *clks; |
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| 36 | bool critical; |
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| 37 | }; |
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| 38 | |
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| 39 | #endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */ |
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| 40 | |
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