| 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
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| 2 | /* |
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| 3 | * MTK SDG1 ECC controller |
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| 4 | * |
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| 5 | * Copyright (c) 2016 Mediatek |
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| 6 | * Authors: Xiaolei Li <xiaolei.li@mediatek.com> |
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| 7 | * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ |
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| 11 | #define __DRIVERS_MTD_NAND_MTK_ECC_H__ |
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| 12 | |
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| 13 | #include <linux/types.h> |
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| 14 | |
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| 15 | enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; |
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| 16 | enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; |
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| 17 | |
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| 18 | struct device_node; |
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| 19 | struct mtk_ecc; |
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| 20 | |
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| 21 | struct mtk_ecc_stats { |
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| 22 | u32 corrected; |
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| 23 | u32 bitflips; |
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| 24 | u32 failed; |
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| 25 | }; |
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| 26 | |
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| 27 | struct mtk_ecc_config { |
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| 28 | enum mtk_ecc_operation op; |
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| 29 | enum mtk_ecc_mode mode; |
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| 30 | dma_addr_t addr; |
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| 31 | u32 strength; |
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| 32 | u32 sectors; |
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| 33 | u32 len; |
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| 34 | }; |
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| 35 | |
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| 36 | int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); |
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| 37 | void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); |
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| 38 | int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); |
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| 39 | int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); |
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| 40 | void mtk_ecc_disable(struct mtk_ecc *); |
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| 41 | void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); |
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| 42 | unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); |
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| 43 | |
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| 44 | struct mtk_ecc *of_mtk_ecc_get(struct device_node *); |
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| 45 | void mtk_ecc_release(struct mtk_ecc *); |
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| 46 | |
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| 47 | #endif |
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| 48 | |
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