1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Functions to access TPS65215/TPS65219 Power Management Integrated Chips
4 *
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9#ifndef MFD_TPS65219_H
10#define MFD_TPS65219_H
11
12#include <linux/bitops.h>
13#include <linux/regmap.h>
14#include <linux/regulator/driver.h>
15
16/* Chip id list*/
17enum pmic_id {
18 TPS65214,
19 TPS65215,
20 TPS65219,
21};
22
23/* I2C ID for TPS65219 part */
24#define TPS65219_I2C_ID 0x24
25
26/* All register addresses */
27#define TPS65219_REG_TI_DEV_ID 0x00
28#define TPS65219_REG_NVM_ID 0x01
29#define TPS65219_REG_ENABLE_CTRL 0x02
30#define TPS65219_REG_BUCKS_CONFIG 0x03
31#define TPS65214_REG_LOCK 0x03
32#define TPS65219_REG_LDO4_VOUT 0x04
33#define TPS65214_REG_LDO1_VOUT_STBY 0x04
34#define TPS65219_REG_LDO3_VOUT 0x05
35#define TPS65215_REG_LDO2_VOUT 0x05
36#define TPS65214_REG_LDO1_VOUT 0x05
37#define TPS65219_REG_LDO2_VOUT 0x06
38#define TPS65214_REG_LDO2_VOUT 0x06
39#define TPS65219_REG_LDO1_VOUT 0x07
40#define TPS65214_REG_LDO2_VOUT_STBY 0x07
41#define TPS65219_REG_BUCK3_VOUT 0x8
42#define TPS65219_REG_BUCK2_VOUT 0x9
43#define TPS65219_REG_BUCK1_VOUT 0xA
44#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
45#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
46#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC
47#define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC
48#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
49#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
50#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
51#define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10
52#define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11
53#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12
54#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13
55#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14
56#define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14
57#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15
58#define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15
59#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16
60#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17
61/* _SLOT_DURATION_3 doesn't apply to TPS65215*/
62#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18
63#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19
64#define TPS65214_REG_BUCK3_VOUT_STBY 0x19
65#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A
66#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B
67#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C
68#define TPS65214_REG_BUCK2_VOUT_STBY 0x1C
69#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D
70#define TPS65214_REG_BUCK1_VOUT_STBY 0x1D
71#define TPS65219_REG_GENERAL_CONFIG 0x1E
72#define TPS65219_REG_MFP_1_CONFIG 0x1F
73#define TPS65219_REG_MFP_2_CONFIG 0x20
74#define TPS65219_REG_STBY_1_CONFIG 0x21
75#define TPS65219_REG_STBY_2_CONFIG 0x22
76#define TPS65219_REG_OC_DEGL_CONFIG 0x23
77/* 'sub irq' MASK registers */
78#define TPS65219_REG_INT_MASK_UV 0x24
79#define TPS65219_REG_MASK_CONFIG 0x25
80
81#define TPS65219_REG_I2C_ADDRESS_REG 0x26
82#define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27
83#define TPS65219_REG_MANUFACTURING_VER 0x28
84#define TPS65219_REG_MFP_CTRL 0x29
85#define TPS65219_REG_DISCHARGE_CONFIG 0x2A
86/* main irq registers */
87#define TPS65219_REG_INT_SOURCE 0x2B
88
89/* TPS65219 'sub irq' registers */
90#define TPS65219_REG_INT_LDO_3_4 0x2C
91#define TPS65219_REG_INT_LDO_1_2 0x2D
92
93/* TPS65215 specific 'sub irq' registers */
94#define TPS65215_REG_INT_LDO_2 0x2C
95#define TPS65215_REG_INT_LDO_1 0x2D
96
97/* TPS65214 specific 'sub irq' register */
98#define TPS65214_REG_INT_LDO_1_2 0x2D
99
100/* Common TPS65215 & TPS65219 'sub irq' registers */
101#define TPS65219_REG_INT_BUCK_3 0x2E
102#define TPS65219_REG_INT_BUCK_1_2 0x2F
103#define TPS65219_REG_INT_SYSTEM 0x30
104#define TPS65219_REG_INT_RV 0x31
105#define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32
106#define TPS65219_REG_INT_PB 0x33
107
108#define TPS65219_REG_INT_LDO_3_4_POS 0
109#define TPS65219_REG_INT_LDO_1_2_POS 1
110#define TPS65219_REG_INT_BUCK_3_POS 2
111#define TPS65219_REG_INT_BUCK_1_2_POS 3
112#define TPS65219_REG_INT_SYS_POS 4
113#define TPS65219_REG_INT_RV_POS 5
114#define TPS65219_REG_INT_TO_RV_POS 6
115#define TPS65219_REG_INT_PB_POS 7
116
117#define TPS65215_REG_INT_LDO_2_POS 0
118#define TPS65215_REG_INT_LDO_1_POS 1
119
120#define TPS65214_REG_INT_LDO_1_2_POS 0
121#define TPS65214_REG_INT_BUCK_3_POS 1
122#define TPS65214_REG_INT_BUCK_1_2_POS 2
123#define TPS65214_REG_INT_SYS_POS 3
124#define TPS65214_REG_INT_RV_POS 4
125#define TPS65214_REG_INT_TO_RV_POS 5
126#define TPS65214_REG_INT_PB_POS 6
127
128#define TPS65219_REG_USER_NVM_CMD 0x34
129#define TPS65219_REG_POWER_UP_STATUS 0x35
130#define TPS65219_REG_SPARE_2 0x36
131#define TPS65219_REG_SPARE_3 0x37
132#define TPS65219_REG_FACTORY_CONFIG_2 0x41
133
134/* Register field definitions */
135#define TPS65219_DEVID_REV_MASK GENMASK(7, 0)
136#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)
137#define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
138#define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
139#define LDO_BYP_SHIFT 6
140#define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
141#define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
142/* Regulators enable control */
143#define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
144#define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
145#define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
146#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3)
147#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
148#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
149#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5)
150#define TPS65214_ENABLE_LDO1_EN_MASK BIT(5)
151#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
152/* power ON-OFF sequence slot */
153#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
154#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4)
155/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */
156#define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0)
157#define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1)
158#define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2)
159#define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3)
160#define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4)
161#define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5)
162#define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6)
163/* STBY_2 config */
164#define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0)
165#define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1)
166#define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2)
167/* MFP Control */
168#define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0)
169#define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1)
170#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2)
171#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3)
172#define TPS65219_MFP_GPIO_STATUS_MASK BIT(4)
173/* MFP_1 Config */
174#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0)
175#define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1)
176#define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2)
177/* MFP_2 Config */
178#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0)
179#define TPS65219_MFP_2_MODE_RESET_MASK BIT(2)
180#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3)
181#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4)
182#define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6)
183#define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7)
184#define TPS65219_MFP_2_EN 0
185#define TPS65219_MFP_2_PB BIT(4)
186#define TPS65219_MFP_2_VSENSE BIT(5)
187/* MASK_UV Config */
188#define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0)
189#define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1)
190#define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2)
191#define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3)
192#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4)
193#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5)
194#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6)
195#define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7)
196/* MASK Config */
197// SENSOR_N_WARM_MASK already defined in Thermal
198#define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4)
199#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
200#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
201/* UnderVoltage - Short to GND - OverCurrent*/
202/* LDO3-4: only for TPS65219*/
203#define TPS65219_INT_LDO3_SCG_MASK BIT(0)
204#define TPS65219_INT_LDO3_OC_MASK BIT(1)
205#define TPS65219_INT_LDO3_UV_MASK BIT(2)
206#define TPS65219_INT_LDO4_SCG_MASK BIT(3)
207#define TPS65219_INT_LDO4_OC_MASK BIT(4)
208#define TPS65219_INT_LDO4_UV_MASK BIT(5)
209/* LDO1-2: TPS65214 & TPS65219 */
210#define TPS65219_INT_LDO1_SCG_MASK BIT(0)
211#define TPS65219_INT_LDO1_OC_MASK BIT(1)
212#define TPS65219_INT_LDO1_UV_MASK BIT(2)
213#define TPS65219_INT_LDO2_SCG_MASK BIT(3)
214#define TPS65219_INT_LDO2_OC_MASK BIT(4)
215#define TPS65219_INT_LDO2_UV_MASK BIT(5)
216/* TPS65215 LDO1-2*/
217#define TPS65215_INT_LDO1_SCG_MASK BIT(0)
218#define TPS65215_INT_LDO1_OC_MASK BIT(1)
219#define TPS65215_INT_LDO1_UV_MASK BIT(2)
220#define TPS65215_INT_LDO2_SCG_MASK BIT(0)
221#define TPS65215_INT_LDO2_OC_MASK BIT(1)
222#define TPS65215_INT_LDO2_UV_MASK BIT(2)
223/* BUCK3 */
224#define TPS65219_INT_BUCK3_SCG_MASK BIT(0)
225#define TPS65219_INT_BUCK3_OC_MASK BIT(1)
226#define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2)
227#define TPS65219_INT_BUCK3_UV_MASK BIT(3)
228/* BUCK1-2 */
229#define TPS65219_INT_BUCK1_SCG_MASK BIT(0)
230#define TPS65219_INT_BUCK1_OC_MASK BIT(1)
231#define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2)
232#define TPS65219_INT_BUCK1_UV_MASK BIT(3)
233#define TPS65219_INT_BUCK2_SCG_MASK BIT(4)
234#define TPS65219_INT_BUCK2_OC_MASK BIT(5)
235#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
236#define TPS65219_INT_BUCK2_UV_MASK BIT(7)
237/* Thermal Sensor: TPS65219/TPS65215 */
238#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
239#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
240/* Thermal Sensor: TPS65219/TPS65215/TPS65214 */
241#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
242#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
243#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
244#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
245#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
246#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
247/* Residual Voltage */
248#define TPS65219_INT_BUCK1_RV_MASK BIT(0)
249#define TPS65219_INT_BUCK2_RV_MASK BIT(1)
250#define TPS65219_INT_BUCK3_RV_MASK BIT(2)
251#define TPS65219_INT_LDO1_RV_MASK BIT(3)
252#define TPS65219_INT_LDO2_RV_MASK BIT(4)
253#define TPS65219_INT_LDO3_RV_MASK BIT(5)
254#define TPS65215_INT_LDO2_RV_MASK BIT(5)
255#define TPS65214_INT_LDO2_RV_MASK BIT(5)
256#define TPS65219_INT_LDO4_RV_MASK BIT(6)
257/* Residual Voltage ShutDown */
258#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
259#define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1)
260#define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2)
261#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3)
262#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
263#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
264#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5)
265#define TPS65214_INT_LDO1_RV_SD_MASK BIT(5)
266#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
267#define TPS65219_INT_TIMEOUT_MASK BIT(7)
268/* Power Button */
269#define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0)
270#define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1)
271#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2)
272
273#define TPS65219_PB_POS 7
274#define TPS65219_TO_RV_POS 6
275#define TPS65219_RV_POS 5
276#define TPS65219_SYS_POS 4
277#define TPS65219_BUCK_1_2_POS 3
278#define TPS65219_BUCK_3_POS 2
279#define TPS65219_LDO_1_2_POS 1
280#define TPS65219_LDO_3_4_POS 0
281
282/* IRQs */
283enum {
284 /* LDO3-4 register IRQs */
285 TPS65219_INT_LDO3_SCG,
286 TPS65219_INT_LDO3_OC,
287 TPS65219_INT_LDO3_UV,
288 TPS65219_INT_LDO4_SCG,
289 TPS65219_INT_LDO4_OC,
290 TPS65219_INT_LDO4_UV,
291 /* TPS65215 LDO1*/
292 TPS65215_INT_LDO1_SCG,
293 TPS65215_INT_LDO1_OC,
294 TPS65215_INT_LDO1_UV,
295 /* TPS65215 LDO2*/
296 TPS65215_INT_LDO2_SCG,
297 TPS65215_INT_LDO2_OC,
298 TPS65215_INT_LDO2_UV,
299 /* LDO1-2: TPS65219/TPS65214 */
300 TPS65219_INT_LDO1_SCG,
301 TPS65219_INT_LDO1_OC,
302 TPS65219_INT_LDO1_UV,
303 TPS65219_INT_LDO2_SCG,
304 TPS65219_INT_LDO2_OC,
305 TPS65219_INT_LDO2_UV,
306 /* BUCK3 */
307 TPS65219_INT_BUCK3_SCG,
308 TPS65219_INT_BUCK3_OC,
309 TPS65219_INT_BUCK3_NEG_OC,
310 TPS65219_INT_BUCK3_UV,
311 /* BUCK1-2 */
312 TPS65219_INT_BUCK1_SCG,
313 TPS65219_INT_BUCK1_OC,
314 TPS65219_INT_BUCK1_NEG_OC,
315 TPS65219_INT_BUCK1_UV,
316 TPS65219_INT_BUCK2_SCG,
317 TPS65219_INT_BUCK2_OC,
318 TPS65219_INT_BUCK2_NEG_OC,
319 TPS65219_INT_BUCK2_UV,
320 /* Thermal Sensor */
321 TPS65219_INT_SENSOR_3_WARM,
322 TPS65219_INT_SENSOR_2_WARM,
323 TPS65219_INT_SENSOR_1_WARM,
324 TPS65219_INT_SENSOR_0_WARM,
325 TPS65219_INT_SENSOR_3_HOT,
326 TPS65219_INT_SENSOR_2_HOT,
327 TPS65219_INT_SENSOR_1_HOT,
328 TPS65219_INT_SENSOR_0_HOT,
329 /* Residual Voltage */
330 TPS65219_INT_BUCK1_RV,
331 TPS65219_INT_BUCK2_RV,
332 TPS65219_INT_BUCK3_RV,
333 TPS65219_INT_LDO1_RV,
334 TPS65219_INT_LDO2_RV,
335 TPS65215_INT_LDO2_RV,
336 TPS65214_INT_LDO2_RV,
337 TPS65219_INT_LDO3_RV,
338 TPS65219_INT_LDO4_RV,
339 /* Residual Voltage ShutDown */
340 TPS65219_INT_BUCK1_RV_SD,
341 TPS65219_INT_BUCK2_RV_SD,
342 TPS65219_INT_BUCK3_RV_SD,
343 TPS65219_INT_LDO1_RV_SD,
344 TPS65214_INT_LDO1_RV_SD,
345 TPS65215_INT_LDO2_RV_SD,
346 TPS65219_INT_LDO2_RV_SD,
347 TPS65219_INT_LDO3_RV_SD,
348 TPS65219_INT_LDO4_RV_SD,
349 TPS65219_INT_TIMEOUT,
350 /* Power Button */
351 TPS65219_INT_PB_FALLING_EDGE_DETECT,
352 TPS65219_INT_PB_RISING_EDGE_DETECT,
353};
354
355enum tps65214_regulator_id {
356 /*
357 * DCDC's same as TPS65219
358 * LDO1 maps to TPS65219's LDO3
359 * LDO2 is the same as TPS65219
360 *
361 */
362 TPS65214_LDO_1 = 3,
363 TPS65214_LDO_2 = 4,
364};
365
366enum tps65215_regulator_id {
367 /* DCDC's same as TPS65219 */
368 /* LDO1 is the same as TPS65219 */
369 TPS65215_LDO_2 = 4,
370};
371
372enum tps65219_regulator_id {
373 /* DCDC's */
374 TPS65219_BUCK_1,
375 TPS65219_BUCK_2,
376 TPS65219_BUCK_3,
377 /* LDOs */
378 TPS65219_LDO_1,
379 TPS65219_LDO_2,
380 TPS65219_LDO_3,
381 TPS65219_LDO_4,
382};
383
384/* Number of step-down converters available */
385#define TPS6521X_NUM_BUCKS 3
386/* Number of LDO voltage regulators available */
387#define TPS65219_NUM_LDO 4
388#define TPS65215_NUM_LDO 2
389#define TPS65214_NUM_LDO 2
390/* Number of total regulators available */
391#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO)
392#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO)
393#define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO)
394
395/* Define the TPS65214 IRQ numbers */
396enum tps65214_irqs {
397 /* INT source registers */
398 TPS65214_TO_RV_SD_SET_IRQ,
399 TPS65214_RV_SET_IRQ,
400 TPS65214_SYS_SET_IRQ,
401 TPS65214_BUCK_1_2_SET_IRQ,
402 TPS65214_BUCK_3_SET_IRQ,
403 TPS65214_LDO_1_2_SET_IRQ,
404 TPS65214_PB_SET_IRQ = 7,
405};
406
407/* Define the TPS65215 IRQ numbers */
408enum tps65215_irqs {
409 /* INT source registers */
410 TPS65215_TO_RV_SD_SET_IRQ,
411 TPS65215_RV_SET_IRQ,
412 TPS65215_SYS_SET_IRQ,
413 TPS65215_BUCK_1_2_SET_IRQ,
414 TPS65215_BUCK_3_SET_IRQ,
415 TPS65215_LDO_1_SET_IRQ,
416 TPS65215_LDO_2_SET_IRQ,
417 TPS65215_PB_SET_IRQ,
418};
419
420/* Define the TPS65219 IRQ numbers */
421enum tps65219_irqs {
422 /* INT source registers */
423 TPS65219_TO_RV_SD_SET_IRQ,
424 TPS65219_RV_SET_IRQ,
425 TPS65219_SYS_SET_IRQ,
426 TPS65219_BUCK_1_2_SET_IRQ,
427 TPS65219_BUCK_3_SET_IRQ,
428 TPS65219_LDO_1_2_SET_IRQ,
429 TPS65219_LDO_3_4_SET_IRQ,
430 TPS65219_PB_SET_IRQ,
431};
432
433/**
434 * struct tps65219 - tps65219 sub-driver chip access routines
435 *
436 * Device data may be used to access the TPS65219 chip
437 *
438 * @dev: MFD device
439 * @regmap: Regmap for accessing the device registers
440 * @irq_data: Regmap irq data used for the irq chip
441 */
442struct tps65219 {
443 struct device *dev;
444 struct regmap *regmap;
445
446 struct regmap_irq_chip_data *irq_data;
447};
448
449#endif /* MFD_TPS65219_H */
450

source code of linux/include/linux/mfd/tps65219.h