| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * MFD core driver for Richtek RT5033 |
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| 4 | * |
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| 5 | * Copyright (C) 2014 Samsung Electronics, Co., Ltd. |
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| 6 | * Author: Beomho Seo <beomho.seo@samsung.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __RT5033_PRIVATE_H__ |
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| 10 | #define __RT5033_PRIVATE_H__ |
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| 11 | |
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| 12 | enum rt5033_reg { |
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| 13 | RT5033_REG_CHG_STAT = 0x00, |
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| 14 | RT5033_REG_CHG_CTRL1 = 0x01, |
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| 15 | RT5033_REG_CHG_CTRL2 = 0x02, |
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| 16 | RT5033_REG_DEVICE_ID = 0x03, |
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| 17 | RT5033_REG_CHG_CTRL3 = 0x04, |
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| 18 | RT5033_REG_CHG_CTRL4 = 0x05, |
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| 19 | RT5033_REG_CHG_CTRL5 = 0x06, |
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| 20 | RT5033_REG_RT_CTRL0 = 0x07, |
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| 21 | RT5033_REG_CHG_RESET = 0x08, |
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| 22 | /* Reserved 0x09~0x18 */ |
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| 23 | RT5033_REG_RT_CTRL1 = 0x19, |
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| 24 | /* Reserved 0x1A~0x20 */ |
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| 25 | RT5033_REG_FLED_FUNCTION1 = 0x21, |
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| 26 | RT5033_REG_FLED_FUNCTION2 = 0x22, |
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| 27 | RT5033_REG_FLED_STROBE_CTRL1 = 0x23, |
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| 28 | RT5033_REG_FLED_STROBE_CTRL2 = 0x24, |
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| 29 | RT5033_REG_FLED_CTRL1 = 0x25, |
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| 30 | RT5033_REG_FLED_CTRL2 = 0x26, |
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| 31 | RT5033_REG_FLED_CTRL3 = 0x27, |
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| 32 | RT5033_REG_FLED_CTRL4 = 0x28, |
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| 33 | RT5033_REG_FLED_CTRL5 = 0x29, |
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| 34 | /* Reserved 0x2A~0x40 */ |
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| 35 | RT5033_REG_CTRL = 0x41, |
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| 36 | RT5033_REG_BUCK_CTRL = 0x42, |
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| 37 | RT5033_REG_LDO_CTRL = 0x43, |
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| 38 | /* Reserved 0x44~0x46 */ |
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| 39 | RT5033_REG_MANUAL_RESET_CTRL = 0x47, |
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| 40 | /* Reserved 0x48~0x5F */ |
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| 41 | RT5033_REG_CHG_IRQ1 = 0x60, |
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| 42 | RT5033_REG_CHG_IRQ2 = 0x61, |
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| 43 | RT5033_REG_CHG_IRQ3 = 0x62, |
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| 44 | RT5033_REG_CHG_IRQ1_CTRL = 0x63, |
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| 45 | RT5033_REG_CHG_IRQ2_CTRL = 0x64, |
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| 46 | RT5033_REG_CHG_IRQ3_CTRL = 0x65, |
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| 47 | RT5033_REG_LED_IRQ_STAT = 0x66, |
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| 48 | RT5033_REG_LED_IRQ_CTRL = 0x67, |
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| 49 | RT5033_REG_PMIC_IRQ_STAT = 0x68, |
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| 50 | RT5033_REG_PMIC_IRQ_CTRL = 0x69, |
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| 51 | RT5033_REG_SHDN_CTRL = 0x6A, |
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| 52 | RT5033_REG_OFF_EVENT = 0x6B, |
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| 53 | |
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| 54 | RT5033_REG_END, |
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| 55 | }; |
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| 56 | |
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| 57 | /* RT5033 Charger state register */ |
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| 58 | #define RT5033_CHG_STAT_TYPE_MASK 0x60 |
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| 59 | #define RT5033_CHG_STAT_TYPE_PRE 0x20 |
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| 60 | #define RT5033_CHG_STAT_TYPE_FAST 0x60 |
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| 61 | #define RT5033_CHG_STAT_MASK 0x30 |
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| 62 | #define RT5033_CHG_STAT_DISCHARGING 0x00 |
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| 63 | #define RT5033_CHG_STAT_FULL 0x10 |
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| 64 | #define RT5033_CHG_STAT_CHARGING 0x20 |
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| 65 | #define RT5033_CHG_STAT_NOT_CHARGING 0x30 |
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| 66 | |
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| 67 | /* RT5033 CHGCTRL1 register */ |
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| 68 | #define RT5033_CHGCTRL1_IAICR_MASK 0xe0 |
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| 69 | #define RT5033_CHGCTRL1_TE_EN_MASK 0x08 |
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| 70 | #define RT5033_CHGCTRL1_HZ_MASK 0x02 |
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| 71 | #define RT5033_CHGCTRL1_MODE_MASK 0x01 |
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| 72 | |
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| 73 | /* RT5033 CHGCTRL2 register */ |
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| 74 | #define RT5033_CHGCTRL2_CV_MASK 0xfc |
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| 75 | #define RT5033_CHGCTRL2_CV_SHIFT 0x02 |
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| 76 | |
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| 77 | /* RT5033 DEVICE_ID register */ |
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| 78 | #define RT5033_VENDOR_ID_MASK 0xf0 |
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| 79 | #define RT5033_CHIP_REV_MASK 0x0f |
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| 80 | |
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| 81 | /* RT5033 CHGCTRL3 register */ |
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| 82 | #define RT5033_CHGCTRL3_CFO_EN_MASK 0x40 |
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| 83 | #define RT5033_CHGCTRL3_TIMER_MASK 0x38 |
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| 84 | #define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01 |
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| 85 | |
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| 86 | /* RT5033 CHGCTRL4 register */ |
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| 87 | #define RT5033_CHGCTRL4_MIVR_MASK 0xe0 |
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| 88 | #define RT5033_CHGCTRL4_IPREC_MASK 0x18 |
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| 89 | #define RT5033_CHGCTRL4_IPREC_SHIFT 0x03 |
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| 90 | #define RT5033_CHGCTRL4_EOC_MASK 0x07 |
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| 91 | |
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| 92 | /* RT5033 CHGCTRL5 register */ |
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| 93 | #define RT5033_CHGCTRL5_ICHG_MASK 0xf0 |
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| 94 | #define RT5033_CHGCTRL5_ICHG_SHIFT 0x04 |
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| 95 | #define RT5033_CHGCTRL5_VPREC_MASK 0x0f |
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| 96 | |
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| 97 | /* RT5033 RT CTRL1 register */ |
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| 98 | #define RT5033_RT_CTRL1_UUG_MASK 0x02 |
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| 99 | |
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| 100 | /* RT5033 control register */ |
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| 101 | #define RT5033_CTRL_FCCM_BUCK_MASK BIT(0) |
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| 102 | #define RT5033_CTRL_BUCKOMS_MASK BIT(1) |
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| 103 | #define RT5033_CTRL_LDOOMS_MASK BIT(2) |
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| 104 | #define RT5033_CTRL_SLDOOMS_MASK BIT(3) |
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| 105 | #define RT5033_CTRL_EN_BUCK_MASK BIT(4) |
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| 106 | #define RT5033_CTRL_EN_LDO_MASK BIT(5) |
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| 107 | #define RT5033_CTRL_EN_SAFE_LDO_MASK BIT(6) |
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| 108 | #define RT5033_CTRL_LDO_SLEEP_MASK BIT(7) |
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| 109 | |
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| 110 | /* RT5033 BUCK control register */ |
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| 111 | #define RT5033_BUCK_CTRL_MASK 0x1f |
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| 112 | |
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| 113 | /* RT5033 LDO control register */ |
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| 114 | #define RT5033_LDO_CTRL_MASK 0x1f |
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| 115 | |
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| 116 | /* RT5033 charger property - model, manufacturer */ |
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| 117 | #define RT5033_CHARGER_MODEL "RT5033WSC Charger" |
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| 118 | #define RT5033_MANUFACTURER "Richtek Technology Corporation" |
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| 119 | |
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| 120 | /* |
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| 121 | * While RT5033 charger can limit the fast-charge current (as in CHGCTRL1 |
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| 122 | * register), AICR mode limits the input current. For example, the AIRC 100 |
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| 123 | * mode limits the input current to 100 mA. |
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| 124 | */ |
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| 125 | #define RT5033_AICR_DISABLE 0x00 |
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| 126 | #define RT5033_AICR_100_MODE 0x20 |
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| 127 | #define RT5033_AICR_500_MODE 0x40 |
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| 128 | #define RT5033_AICR_700_MODE 0x60 |
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| 129 | #define RT5033_AICR_900_MODE 0x80 |
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| 130 | #define RT5033_AICR_1000_MODE 0xa0 |
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| 131 | #define RT5033_AICR_1500_MODE 0xc0 |
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| 132 | #define RT5033_AICR_2000_MODE 0xe0 |
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| 133 | |
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| 134 | /* RT5033 charger minimum input voltage regulation */ |
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| 135 | #define RT5033_CHARGER_MIVR_DISABLE 0x00 |
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| 136 | #define RT5033_CHARGER_MIVR_4200MV 0x20 |
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| 137 | #define RT5033_CHARGER_MIVR_4300MV 0x40 |
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| 138 | #define RT5033_CHARGER_MIVR_4400MV 0x60 |
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| 139 | #define RT5033_CHARGER_MIVR_4500MV 0x80 |
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| 140 | #define RT5033_CHARGER_MIVR_4600MV 0xa0 |
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| 141 | #define RT5033_CHARGER_MIVR_4700MV 0xc0 |
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| 142 | #define RT5033_CHARGER_MIVR_4800MV 0xe0 |
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| 143 | |
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| 144 | /* RT5033 use internal timer need to set time */ |
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| 145 | #define RT5033_FAST_CHARGE_TIMER4 0x00 /* 4 hrs */ |
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| 146 | #define RT5033_FAST_CHARGE_TIMER6 0x08 /* 6 hrs */ |
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| 147 | #define RT5033_FAST_CHARGE_TIMER8 0x10 /* 8 hrs */ |
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| 148 | #define RT5033_FAST_CHARGE_TIMER10 0x18 /* 10 hrs */ |
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| 149 | #define RT5033_FAST_CHARGE_TIMER12 0x20 /* 12 hrs */ |
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| 150 | #define RT5033_FAST_CHARGE_TIMER14 0x28 /* 14 hrs */ |
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| 151 | #define RT5033_FAST_CHARGE_TIMER16 0x30 /* 16 hrs */ |
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| 152 | |
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| 153 | #define RT5033_INT_TIMER_DISABLE 0x00 |
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| 154 | #define RT5033_INT_TIMER_ENABLE 0x01 |
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| 155 | |
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| 156 | /* |
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| 157 | * RT5033 charger opa mode. RT5033 has two opa modes for OTG: charger mode |
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| 158 | * and boost mode. |
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| 159 | */ |
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| 160 | #define RT5033_CHARGER_MODE 0x00 |
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| 161 | #define RT5033_BOOST_MODE 0x01 |
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| 162 | |
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| 163 | /* RT5033 charger termination enable */ |
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| 164 | #define RT5033_TE_DISABLE 0x00 |
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| 165 | #define RT5033_TE_ENABLE 0x08 |
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| 166 | |
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| 167 | /* RT5033 charger CFO enable */ |
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| 168 | #define RT5033_CFO_DISABLE 0x00 |
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| 169 | #define RT5033_CFO_ENABLE 0x40 |
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| 170 | |
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| 171 | /* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */ |
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| 172 | #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U |
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| 173 | #define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U |
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| 174 | #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U |
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| 175 | #define RT5033_CV_MAX_VOLTAGE 0x1e |
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| 176 | |
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| 177 | /* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */ |
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| 178 | #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U |
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| 179 | #define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U |
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| 180 | #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U |
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| 181 | #define RT5033_CHG_MAX_PRE_CURRENT 0x03 |
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| 182 | |
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| 183 | /* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */ |
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| 184 | #define RT5033_CHARGER_FAST_CURRENT_MIN 700000U |
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| 185 | #define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U |
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| 186 | #define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U |
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| 187 | #define RT5033_CHG_MAX_CURRENT 0x0d |
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| 188 | |
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| 189 | /* |
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| 190 | * RT5033 charger const-charge end of charger current ( |
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| 191 | * as in CHGCTRL4 register), uA |
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| 192 | */ |
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| 193 | #define RT5033_CHARGER_EOC_MIN 150000U |
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| 194 | #define RT5033_CHARGER_EOC_REF 300000U |
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| 195 | #define RT5033_CHARGER_EOC_STEP_NUM1 50000U |
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| 196 | #define RT5033_CHARGER_EOC_STEP_NUM2 100000U |
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| 197 | #define RT5033_CHARGER_EOC_MAX 600000U |
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| 198 | |
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| 199 | /* |
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| 200 | * RT5033 charger pre-charge threshold volt limits |
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| 201 | * (as in CHGCTRL5 register), uV |
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| 202 | */ |
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| 203 | #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U |
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| 204 | #define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U |
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| 205 | #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U |
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| 206 | |
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| 207 | /* |
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| 208 | * RT5033 charger UUG. It enables MOS auto control by H/W charger |
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| 209 | * circuit. |
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| 210 | */ |
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| 211 | #define RT5033_CHARGER_UUG_DISABLE 0x00 |
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| 212 | #define RT5033_CHARGER_UUG_ENABLE 0x02 |
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| 213 | |
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| 214 | /* RT5033 charger high impedance mode */ |
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| 215 | #define RT5033_CHARGER_HZ_DISABLE 0x00 |
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| 216 | #define RT5033_CHARGER_HZ_ENABLE 0x02 |
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| 217 | |
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| 218 | /* RT5033 regulator BUCK output voltage uV */ |
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| 219 | #define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U |
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| 220 | #define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U |
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| 221 | #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U |
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| 222 | #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32 |
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| 223 | |
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| 224 | /* RT5033 regulator LDO output voltage uV */ |
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| 225 | #define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U |
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| 226 | #define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U |
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| 227 | #define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U |
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| 228 | #define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32 |
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| 229 | |
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| 230 | /* RT5033 regulator SAFE LDO output voltage uV */ |
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| 231 | #define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U |
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| 232 | |
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| 233 | enum rt5033_fuel_reg { |
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| 234 | RT5033_FUEL_REG_OCV_H = 0x00, |
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| 235 | RT5033_FUEL_REG_OCV_L = 0x01, |
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| 236 | RT5033_FUEL_REG_VBAT_H = 0x02, |
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| 237 | RT5033_FUEL_REG_VBAT_L = 0x03, |
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| 238 | RT5033_FUEL_REG_SOC_H = 0x04, |
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| 239 | RT5033_FUEL_REG_SOC_L = 0x05, |
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| 240 | RT5033_FUEL_REG_CTRL_H = 0x06, |
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| 241 | RT5033_FUEL_REG_CTRL_L = 0x07, |
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| 242 | RT5033_FUEL_REG_CRATE = 0x08, |
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| 243 | RT5033_FUEL_REG_DEVICE_ID = 0x09, |
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| 244 | RT5033_FUEL_REG_AVG_VOLT_H = 0x0A, |
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| 245 | RT5033_FUEL_REG_AVG_VOLT_L = 0x0B, |
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| 246 | RT5033_FUEL_REG_CONFIG_H = 0x0C, |
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| 247 | RT5033_FUEL_REG_CONFIG_L = 0x0D, |
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| 248 | /* Reserved 0x0E~0x0F */ |
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| 249 | RT5033_FUEL_REG_IRQ_CTRL = 0x10, |
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| 250 | RT5033_FUEL_REG_IRQ_FLAG = 0x11, |
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| 251 | RT5033_FUEL_VMIN = 0x12, |
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| 252 | RT5033_FUEL_SMIN = 0x13, |
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| 253 | /* Reserved 0x14~0x1F */ |
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| 254 | RT5033_FUEL_VGCOMP1 = 0x20, |
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| 255 | RT5033_FUEL_VGCOMP2 = 0x21, |
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| 256 | RT5033_FUEL_VGCOMP3 = 0x22, |
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| 257 | RT5033_FUEL_VGCOMP4 = 0x23, |
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| 258 | /* Reserved 0x24~0xFD */ |
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| 259 | RT5033_FUEL_MFA_H = 0xFE, |
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| 260 | RT5033_FUEL_MFA_L = 0xFF, |
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| 261 | |
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| 262 | RT5033_FUEL_REG_END, |
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| 263 | }; |
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| 264 | |
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| 265 | /* RT5033 fuel gauge battery present property */ |
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| 266 | #define RT5033_FUEL_BAT_PRESENT 0x02 |
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| 267 | |
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| 268 | /* RT5033 PMIC interrupts */ |
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| 269 | #define RT5033_PMIC_IRQ_BUCKOCP BIT(2) |
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| 270 | #define RT5033_PMIC_IRQ_BUCKLV BIT(3) |
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| 271 | #define RT5033_PMIC_IRQ_SAFELDOLV BIT(4) |
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| 272 | #define RT5033_PMIC_IRQ_LDOLV BIT(5) |
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| 273 | #define RT5033_PMIC_IRQ_OT BIT(6) |
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| 274 | #define RT5033_PMIC_IRQ_VDDA_UV BIT(7) |
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| 275 | |
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| 276 | #endif /* __RT5033_PRIVATE_H__ */ |
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| 277 | |
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