| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Copyright (C) 2025 ROHM Semiconductors |
| 4 | * |
| 5 | * The digital interface of trhe BD96802 PMIC is a reduced version of the |
| 6 | * BD96801. Hence the BD96801 definitions are used for registers and masks |
| 7 | * while this header only holds the IRQ definitions - mainly to avoid gaps in |
| 8 | * IRQ numbers caused by the lack of some BUCKs / LDOs and their respective |
| 9 | * IRQs. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __LINUX_MFD_BD96802_H__ |
| 13 | #define __LINUX_MFD_BD96802_H__ |
| 14 | |
| 15 | /* ERRB IRQs */ |
| 16 | enum { |
| 17 | /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */ |
| 18 | BD96802_OTP_ERR_STAT, |
| 19 | BD96802_DBIST_ERR_STAT, |
| 20 | BD96802_EEP_ERR_STAT, |
| 21 | BD96802_ABIST_ERR_STAT, |
| 22 | BD96802_PRSTB_ERR_STAT, |
| 23 | BD96802_DRMOS1_ERR_STAT, |
| 24 | BD96802_DRMOS2_ERR_STAT, |
| 25 | BD96802_SLAVE_ERR_STAT, |
| 26 | BD96802_VREF_ERR_STAT, |
| 27 | BD96802_TSD_ERR_STAT, |
| 28 | BD96802_UVLO_ERR_STAT, |
| 29 | BD96802_OVLO_ERR_STAT, |
| 30 | BD96802_OSC_ERR_STAT, |
| 31 | BD96802_PON_ERR_STAT, |
| 32 | BD96802_POFF_ERR_STAT, |
| 33 | BD96802_CMD_SHDN_ERR_STAT, |
| 34 | BD96802_INT_SHDN_ERR_STAT, |
| 35 | |
| 36 | /* Reg 0x55 BUCK1 ERR IRQs */ |
| 37 | BD96802_BUCK1_PVIN_ERR_STAT, |
| 38 | BD96802_BUCK1_OVP_ERR_STAT, |
| 39 | BD96802_BUCK1_UVP_ERR_STAT, |
| 40 | BD96802_BUCK1_SHDN_ERR_STAT, |
| 41 | |
| 42 | /* Reg 0x56 BUCK2 ERR IRQs */ |
| 43 | BD96802_BUCK2_PVIN_ERR_STAT, |
| 44 | BD96802_BUCK2_OVP_ERR_STAT, |
| 45 | BD96802_BUCK2_UVP_ERR_STAT, |
| 46 | BD96802_BUCK2_SHDN_ERR_STAT, |
| 47 | }; |
| 48 | |
| 49 | /* INTB IRQs */ |
| 50 | enum { |
| 51 | /* Reg 0x5c (System INTB) */ |
| 52 | BD96802_TW_STAT, |
| 53 | BD96802_WDT_ERR_STAT, |
| 54 | BD96802_I2C_ERR_STAT, |
| 55 | BD96802_CHIP_IF_ERR_STAT, |
| 56 | |
| 57 | /* Reg 0x5d (BUCK1 INTB) */ |
| 58 | BD96802_BUCK1_OCPH_STAT, |
| 59 | BD96802_BUCK1_OCPL_STAT, |
| 60 | BD96802_BUCK1_OCPN_STAT, |
| 61 | BD96802_BUCK1_OVD_STAT, |
| 62 | BD96802_BUCK1_UVD_STAT, |
| 63 | BD96802_BUCK1_TW_CH_STAT, |
| 64 | |
| 65 | /* Reg 0x5e (BUCK2 INTB) */ |
| 66 | BD96802_BUCK2_OCPH_STAT, |
| 67 | BD96802_BUCK2_OCPL_STAT, |
| 68 | BD96802_BUCK2_OCPN_STAT, |
| 69 | BD96802_BUCK2_OVD_STAT, |
| 70 | BD96802_BUCK2_UVD_STAT, |
| 71 | BD96802_BUCK2_TW_CH_STAT, |
| 72 | }; |
| 73 | |
| 74 | #endif |
| 75 | |