| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Lochnagar2 register definitions |
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| 4 | * |
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| 5 | * Copyright (c) 2017-2018 Cirrus Logic, Inc. and |
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| 6 | * Cirrus Logic International Semiconductor Ltd. |
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| 7 | * |
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| 8 | * Author: Charles Keepax <ckeepax@opensource.cirrus.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef LOCHNAGAR2_REGISTERS_H |
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| 12 | #define LOCHNAGAR2_REGISTERS_H |
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| 13 | |
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| 14 | /* Register Addresses */ |
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| 15 | #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D |
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| 16 | #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E |
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| 17 | #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F |
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| 18 | #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010 |
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| 19 | #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011 |
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| 20 | #define LOCHNAGAR2_PSIA1_CTRL 0x0012 |
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| 21 | #define LOCHNAGAR2_PSIA2_CTRL 0x0013 |
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| 22 | #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014 |
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| 23 | #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015 |
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| 24 | #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016 |
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| 25 | #define LOCHNAGAR2_GF_AIF2_CTRL 0x0017 |
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| 26 | #define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018 |
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| 27 | #define LOCHNAGAR2_USB_AIF1_CTRL 0x0019 |
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| 28 | #define LOCHNAGAR2_USB_AIF2_CTRL 0x001A |
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| 29 | #define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B |
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| 30 | #define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E |
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| 31 | #define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F |
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| 32 | #define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020 |
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| 33 | #define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021 |
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| 34 | #define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022 |
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| 35 | #define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023 |
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| 36 | #define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024 |
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| 37 | #define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025 |
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| 38 | #define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026 |
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| 39 | #define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027 |
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| 40 | #define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031 |
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| 41 | #define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032 |
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| 42 | #define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033 |
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| 43 | #define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034 |
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| 44 | #define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035 |
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| 45 | #define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036 |
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| 46 | #define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037 |
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| 47 | #define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038 |
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| 48 | #define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039 |
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| 49 | #define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A |
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| 50 | #define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B |
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| 51 | #define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C |
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| 52 | #define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D |
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| 53 | #define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E |
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| 54 | #define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F |
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| 55 | #define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040 |
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| 56 | #define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041 |
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| 57 | #define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042 |
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| 58 | #define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043 |
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| 59 | #define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044 |
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| 60 | #define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045 |
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| 61 | #define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046 |
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| 62 | #define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047 |
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| 63 | #define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048 |
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| 64 | #define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049 |
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| 65 | #define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A |
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| 66 | #define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B |
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| 67 | #define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C |
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| 68 | #define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D |
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| 69 | #define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E |
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| 70 | #define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F |
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| 71 | #define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050 |
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| 72 | #define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051 |
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| 73 | #define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052 |
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| 74 | #define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053 |
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| 75 | #define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054 |
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| 76 | #define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055 |
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| 77 | #define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056 |
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| 78 | #define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057 |
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| 79 | #define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058 |
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| 80 | #define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059 |
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| 81 | #define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A |
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| 82 | #define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B |
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| 83 | #define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C |
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| 84 | #define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D |
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| 85 | #define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E |
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| 86 | #define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F |
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| 87 | #define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060 |
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| 88 | #define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061 |
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| 89 | #define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062 |
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| 90 | #define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063 |
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| 91 | #define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064 |
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| 92 | #define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065 |
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| 93 | #define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066 |
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| 94 | #define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067 |
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| 95 | #define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068 |
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| 96 | #define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069 |
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| 97 | #define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A |
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| 98 | #define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B |
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| 99 | #define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C |
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| 100 | #define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D |
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| 101 | #define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E |
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| 102 | #define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F |
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| 103 | #define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070 |
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| 104 | #define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071 |
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| 105 | #define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072 |
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| 106 | #define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073 |
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| 107 | #define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074 |
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| 108 | #define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075 |
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| 109 | #define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076 |
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| 110 | #define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077 |
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| 111 | #define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078 |
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| 112 | #define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079 |
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| 113 | #define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A |
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| 114 | #define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C |
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| 115 | #define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D |
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| 116 | #define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E |
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| 117 | #define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F |
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| 118 | #define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080 |
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| 119 | #define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081 |
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| 120 | #define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082 |
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| 121 | #define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083 |
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| 122 | #define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084 |
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| 123 | #define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085 |
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| 124 | #define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086 |
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| 125 | #define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087 |
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| 126 | #define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088 |
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| 127 | #define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089 |
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| 128 | #define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A |
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| 129 | #define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B |
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| 130 | #define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C |
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| 131 | #define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D |
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| 132 | #define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E |
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| 133 | #define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F |
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| 134 | #define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090 |
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| 135 | #define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091 |
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| 136 | #define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092 |
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| 137 | #define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093 |
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| 138 | #define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094 |
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| 139 | #define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095 |
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| 140 | #define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096 |
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| 141 | #define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097 |
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| 142 | #define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098 |
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| 143 | #define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099 |
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| 144 | #define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A |
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| 145 | #define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9 |
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| 146 | #define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA |
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| 147 | #define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB |
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| 148 | #define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC |
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| 149 | #define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD |
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| 150 | #define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE |
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| 151 | #define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF |
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| 152 | #define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0 |
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| 153 | #define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1 |
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| 154 | #define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2 |
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| 155 | #define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3 |
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| 156 | #define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4 |
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| 157 | #define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5 |
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| 158 | #define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6 |
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| 159 | #define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7 |
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| 160 | #define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8 |
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| 161 | #define LOCHNAGAR2_MINICARD_RESETS 0x00DF |
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| 162 | #define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3 |
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| 163 | #define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4 |
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| 164 | #define LOCHNAGAR2_COMMS_CTRL4 0x00F0 |
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| 165 | #define LOCHNAGAR2_SPDIF_CTRL 0x00FE |
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| 166 | #define LOCHNAGAR2_IMON_CTRL1 0x0108 |
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| 167 | #define LOCHNAGAR2_IMON_CTRL2 0x0109 |
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| 168 | #define LOCHNAGAR2_IMON_CTRL3 0x010A |
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| 169 | #define LOCHNAGAR2_IMON_CTRL4 0x010B |
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| 170 | #define LOCHNAGAR2_IMON_DATA1 0x010C |
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| 171 | #define LOCHNAGAR2_IMON_DATA2 0x010D |
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| 172 | #define LOCHNAGAR2_POWER_CTRL 0x0116 |
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| 173 | #define LOCHNAGAR2_MICVDD_CTRL1 0x0119 |
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| 174 | #define LOCHNAGAR2_MICVDD_CTRL2 0x011B |
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| 175 | #define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E |
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| 176 | #define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120 |
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| 177 | #define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180 |
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| 178 | |
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| 179 | /* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */ |
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| 180 | #define LOCHNAGAR2_AIF_ENA_MASK 0x8000 |
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| 181 | #define LOCHNAGAR2_AIF_ENA_SHIFT 15 |
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| 182 | #define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000 |
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| 183 | #define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14 |
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| 184 | #define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000 |
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| 185 | #define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13 |
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| 186 | #define LOCHNAGAR2_AIF_SRC_MASK 0x00FF |
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| 187 | #define LOCHNAGAR2_AIF_SRC_SHIFT 0 |
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| 188 | |
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| 189 | /* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */ |
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| 190 | #define LOCHNAGAR2_CLK_ENA_MASK 0x8000 |
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| 191 | #define LOCHNAGAR2_CLK_ENA_SHIFT 15 |
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| 192 | #define LOCHNAGAR2_CLK_SRC_MASK 0x00FF |
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| 193 | #define LOCHNAGAR2_CLK_SRC_SHIFT 0 |
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| 194 | |
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| 195 | /* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */ |
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| 196 | #define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF |
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| 197 | #define LOCHNAGAR2_GPIO_SRC_SHIFT 0 |
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| 198 | |
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| 199 | /* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */ |
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| 200 | #define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000 |
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| 201 | #define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15 |
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| 202 | #define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF |
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| 203 | #define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0 |
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| 204 | |
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| 205 | /* (0x00DF) MINICARD_RESETS */ |
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| 206 | #define LOCHNAGAR2_DSP_RESET_MASK 0x0002 |
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| 207 | #define LOCHNAGAR2_DSP_RESET_SHIFT 1 |
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| 208 | #define LOCHNAGAR2_CDC_RESET_MASK 0x0001 |
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| 209 | #define LOCHNAGAR2_CDC_RESET_SHIFT 0 |
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| 210 | |
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| 211 | /* (0x00E3) ANALOGUE_PATH_CTRL1 */ |
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| 212 | #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000 |
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| 213 | #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15 |
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| 214 | #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000 |
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| 215 | #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14 |
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| 216 | |
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| 217 | /* (0x00E4) ANALOGUE_PATH_CTRL2 */ |
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| 218 | #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080 |
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| 219 | #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7 |
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| 220 | #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040 |
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| 221 | #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6 |
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| 222 | #define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038 |
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| 223 | #define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3 |
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| 224 | #define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007 |
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| 225 | #define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0 |
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| 226 | |
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| 227 | /* (0x00F0) COMMS_CTRL4 */ |
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| 228 | #define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001 |
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| 229 | #define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0 |
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| 230 | |
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| 231 | /* (0x00FE) SPDIF_CTRL */ |
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| 232 | #define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008 |
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| 233 | #define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3 |
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| 234 | #define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001 |
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| 235 | #define LOCHNAGAR2_SPDIF_RESET_SHIFT 0 |
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| 236 | |
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| 237 | /* (0x0108) IMON_CTRL1 */ |
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| 238 | #define LOCHNAGAR2_IMON_ENA_MASK 0x8000 |
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| 239 | #define LOCHNAGAR2_IMON_ENA_SHIFT 15 |
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| 240 | #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC |
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| 241 | #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2 |
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| 242 | #define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003 |
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| 243 | #define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0 |
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| 244 | |
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| 245 | /* (0x0109) IMON_CTRL2 */ |
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| 246 | #define LOCHNAGAR2_IMON_FSR_MASK 0x03FF |
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| 247 | #define LOCHNAGAR2_IMON_FSR_SHIFT 0 |
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| 248 | |
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| 249 | /* (0x010A) IMON_CTRL3 */ |
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| 250 | #define LOCHNAGAR2_IMON_DONE_MASK 0x0004 |
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| 251 | #define LOCHNAGAR2_IMON_DONE_SHIFT 2 |
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| 252 | #define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002 |
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| 253 | #define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1 |
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| 254 | #define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001 |
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| 255 | #define LOCHNAGAR2_IMON_MEASURE_SHIFT 0 |
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| 256 | |
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| 257 | /* (0x010B) IMON_CTRL4 */ |
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| 258 | #define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080 |
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| 259 | #define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7 |
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| 260 | #define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070 |
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| 261 | #define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4 |
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| 262 | #define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008 |
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| 263 | #define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3 |
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| 264 | #define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007 |
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| 265 | #define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0 |
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| 266 | |
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| 267 | /* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */ |
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| 268 | #define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF |
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| 269 | #define LOCHNAGAR2_IMON_DATA_SHIFT 0 |
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| 270 | |
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| 271 | /* (0x0116) POWER_CTRL */ |
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| 272 | #define LOCHNAGAR2_PWR_ENA_MASK 0x0001 |
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| 273 | #define LOCHNAGAR2_PWR_ENA_SHIFT 0 |
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| 274 | |
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| 275 | /* (0x0119) MICVDD_CTRL1 */ |
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| 276 | #define LOCHNAGAR2_MICVDD_REG_ENA_MASK 0x8000 |
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| 277 | #define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT 15 |
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| 278 | |
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| 279 | /* (0x011B) MICVDD_CTRL2 */ |
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| 280 | #define LOCHNAGAR2_MICVDD_VSEL_MASK 0x001F |
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| 281 | #define LOCHNAGAR2_MICVDD_VSEL_SHIFT 0 |
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| 282 | |
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| 283 | /* (0x011E) VDDCORE_CDC_CTRL1 */ |
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| 284 | #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK 0x8000 |
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| 285 | #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT 15 |
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| 286 | |
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| 287 | /* (0x0120) VDDCORE_CDC_CTRL2 */ |
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| 288 | #define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK 0x007F |
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| 289 | #define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT 0 |
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| 290 | |
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| 291 | #endif |
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| 292 | |
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