| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Lochnagar1 register definitions |
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| 4 | * |
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| 5 | * Copyright (c) 2017-2018 Cirrus Logic, Inc. and |
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| 6 | * Cirrus Logic International Semiconductor Ltd. |
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| 7 | * |
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| 8 | * Author: Charles Keepax <ckeepax@opensource.cirrus.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef LOCHNAGAR1_REGISTERS_H |
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| 12 | #define LOCHNAGAR1_REGISTERS_H |
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| 13 | |
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| 14 | /* Register Addresses */ |
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| 15 | #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008 |
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| 16 | #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009 |
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| 17 | #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A |
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| 18 | #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B |
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| 19 | #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C |
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| 20 | #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D |
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| 21 | #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E |
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| 22 | #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F |
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| 23 | #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010 |
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| 24 | #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011 |
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| 25 | #define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012 |
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| 26 | #define LOCHNAGAR1_DSP_AIF 0x0013 |
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| 27 | #define LOCHNAGAR1_GF_AIF1 0x0014 |
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| 28 | #define LOCHNAGAR1_GF_AIF2 0x0015 |
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| 29 | #define LOCHNAGAR1_PSIA_AIF 0x0016 |
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| 30 | #define LOCHNAGAR1_PSIA1_SEL 0x0017 |
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| 31 | #define LOCHNAGAR1_PSIA2_SEL 0x0018 |
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| 32 | #define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019 |
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| 33 | #define LOCHNAGAR1_GF_AIF3_SEL 0x001C |
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| 34 | #define LOCHNAGAR1_GF_AIF4_SEL 0x001D |
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| 35 | #define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E |
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| 36 | #define LOCHNAGAR1_GF_AIF1_SEL 0x001F |
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| 37 | #define LOCHNAGAR1_GF_AIF2_SEL 0x0020 |
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| 38 | #define LOCHNAGAR1_GF_GPIO2 0x0026 |
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| 39 | #define LOCHNAGAR1_GF_GPIO3 0x0027 |
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| 40 | #define LOCHNAGAR1_GF_GPIO7 0x0028 |
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| 41 | #define LOCHNAGAR1_RST 0x0029 |
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| 42 | #define LOCHNAGAR1_LED1 0x002A |
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| 43 | #define LOCHNAGAR1_LED2 0x002B |
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| 44 | #define LOCHNAGAR1_I2C_CTRL 0x0046 |
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| 45 | |
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| 46 | /* |
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| 47 | * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020) |
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| 48 | * CDC_AIF1_SEL - GF_AIF2_SEL |
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| 49 | */ |
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| 50 | #define LOCHNAGAR1_SRC_MASK 0xFF |
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| 51 | #define LOCHNAGAR1_SRC_SHIFT 0 |
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| 52 | |
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| 53 | /* (0x000D) CDC_AIF_CTRL1 */ |
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| 54 | #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40 |
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| 55 | #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6 |
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| 56 | #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20 |
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| 57 | #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5 |
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| 58 | #define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10 |
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| 59 | #define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4 |
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| 60 | #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04 |
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| 61 | #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2 |
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| 62 | #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02 |
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| 63 | #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1 |
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| 64 | #define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01 |
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| 65 | #define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0 |
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| 66 | |
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| 67 | /* (0x000E) CDC_AIF_CTRL2 */ |
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| 68 | #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40 |
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| 69 | #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6 |
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| 70 | #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20 |
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| 71 | #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5 |
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| 72 | #define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10 |
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| 73 | #define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4 |
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| 74 | #define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02 |
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| 75 | #define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1 |
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| 76 | #define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01 |
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| 77 | #define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0 |
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| 78 | |
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| 79 | /* (0x000F) EXT_AIF_CTRL */ |
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| 80 | #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20 |
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| 81 | #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5 |
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| 82 | #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10 |
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| 83 | #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4 |
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| 84 | #define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08 |
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| 85 | #define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3 |
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| 86 | |
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| 87 | /* (0x0013) DSP_AIF */ |
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| 88 | #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40 |
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| 89 | #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6 |
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| 90 | #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20 |
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| 91 | #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5 |
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| 92 | #define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10 |
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| 93 | #define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4 |
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| 94 | #define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08 |
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| 95 | #define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3 |
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| 96 | #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04 |
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| 97 | #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2 |
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| 98 | #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02 |
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| 99 | #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1 |
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| 100 | #define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01 |
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| 101 | #define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0 |
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| 102 | |
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| 103 | /* (0x0014) GF_AIF1 */ |
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| 104 | #define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40 |
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| 105 | #define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6 |
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| 106 | #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20 |
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| 107 | #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5 |
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| 108 | #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10 |
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| 109 | #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4 |
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| 110 | #define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08 |
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| 111 | #define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3 |
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| 112 | #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04 |
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| 113 | #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2 |
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| 114 | #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02 |
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| 115 | #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1 |
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| 116 | #define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01 |
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| 117 | #define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0 |
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| 118 | |
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| 119 | /* (0x0015) GF_AIF2 */ |
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| 120 | #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20 |
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| 121 | #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5 |
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| 122 | #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10 |
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| 123 | #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4 |
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| 124 | #define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08 |
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| 125 | #define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3 |
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| 126 | #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04 |
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| 127 | #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2 |
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| 128 | #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02 |
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| 129 | #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1 |
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| 130 | #define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01 |
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| 131 | #define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0 |
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| 132 | |
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| 133 | /* (0x0016) PSIA_AIF */ |
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| 134 | #define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40 |
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| 135 | #define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6 |
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| 136 | #define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20 |
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| 137 | #define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5 |
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| 138 | #define LOCHNAGAR1_PSIA2_ENA_MASK 0x10 |
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| 139 | #define LOCHNAGAR1_PSIA2_ENA_SHIFT 4 |
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| 140 | #define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04 |
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| 141 | #define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2 |
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| 142 | #define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02 |
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| 143 | #define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1 |
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| 144 | #define LOCHNAGAR1_PSIA1_ENA_MASK 0x01 |
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| 145 | #define LOCHNAGAR1_PSIA1_ENA_SHIFT 0 |
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| 146 | |
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| 147 | /* (0x0029) RST */ |
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| 148 | #define LOCHNAGAR1_DSP_RESET_MASK 0x02 |
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| 149 | #define LOCHNAGAR1_DSP_RESET_SHIFT 1 |
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| 150 | #define LOCHNAGAR1_CDC_RESET_MASK 0x01 |
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| 151 | #define LOCHNAGAR1_CDC_RESET_SHIFT 0 |
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| 152 | |
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| 153 | /* (0x0046) I2C_CTRL */ |
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| 154 | #define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01 |
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| 155 | #define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0 |
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| 156 | |
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| 157 | #endif |
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| 158 | |
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