| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * ATC2609A PMIC register definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __LINUX_MFD_ATC260X_ATC2609A_H |
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| 9 | #define __LINUX_MFD_ATC260X_ATC2609A_H |
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| 10 | |
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| 11 | enum atc2609a_irq_def { |
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| 12 | ATC2609A_IRQ_AUDIO = 0, |
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| 13 | ATC2609A_IRQ_OV, |
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| 14 | ATC2609A_IRQ_OC, |
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| 15 | ATC2609A_IRQ_OT, |
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| 16 | ATC2609A_IRQ_UV, |
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| 17 | ATC2609A_IRQ_ALARM, |
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| 18 | ATC2609A_IRQ_ONOFF, |
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| 19 | ATC2609A_IRQ_WKUP, |
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| 20 | ATC2609A_IRQ_IR, |
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| 21 | ATC2609A_IRQ_REMCON, |
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| 22 | ATC2609A_IRQ_POWER_IN, |
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| 23 | }; |
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| 24 | |
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| 25 | /* PMU Registers */ |
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| 26 | #define ATC2609A_PMU_SYS_CTL0 0x00 |
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| 27 | #define ATC2609A_PMU_SYS_CTL1 0x01 |
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| 28 | #define ATC2609A_PMU_SYS_CTL2 0x02 |
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| 29 | #define ATC2609A_PMU_SYS_CTL3 0x03 |
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| 30 | #define ATC2609A_PMU_SYS_CTL4 0x04 |
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| 31 | #define ATC2609A_PMU_SYS_CTL5 0x05 |
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| 32 | #define ATC2609A_PMU_SYS_CTL6 0x06 |
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| 33 | #define ATC2609A_PMU_SYS_CTL7 0x07 |
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| 34 | #define ATC2609A_PMU_SYS_CTL8 0x08 |
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| 35 | #define ATC2609A_PMU_SYS_CTL9 0x09 |
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| 36 | #define ATC2609A_PMU_BAT_CTL0 0x0A |
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| 37 | #define ATC2609A_PMU_BAT_CTL1 0x0B |
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| 38 | #define ATC2609A_PMU_VBUS_CTL0 0x0C |
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| 39 | #define ATC2609A_PMU_VBUS_CTL1 0x0D |
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| 40 | #define ATC2609A_PMU_WALL_CTL0 0x0E |
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| 41 | #define ATC2609A_PMU_WALL_CTL1 0x0F |
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| 42 | #define ATC2609A_PMU_SYS_PENDING 0x10 |
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| 43 | #define ATC2609A_PMU_APDS_CTL0 0x11 |
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| 44 | #define ATC2609A_PMU_APDS_CTL1 0x12 |
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| 45 | #define ATC2609A_PMU_APDS_CTL2 0x13 |
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| 46 | #define ATC2609A_PMU_CHARGER_CTL 0x14 |
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| 47 | #define ATC2609A_PMU_BAKCHARGER_CTL 0x15 |
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| 48 | #define ATC2609A_PMU_SWCHG_CTL0 0x16 |
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| 49 | #define ATC2609A_PMU_SWCHG_CTL1 0x17 |
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| 50 | #define ATC2609A_PMU_SWCHG_CTL2 0x18 |
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| 51 | #define ATC2609A_PMU_SWCHG_CTL3 0x19 |
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| 52 | #define ATC2609A_PMU_SWCHG_CTL4 0x1A |
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| 53 | #define ATC2609A_PMU_DC_OSC 0x1B |
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| 54 | #define ATC2609A_PMU_DC0_CTL0 0x1C |
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| 55 | #define ATC2609A_PMU_DC0_CTL1 0x1D |
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| 56 | #define ATC2609A_PMU_DC0_CTL2 0x1E |
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| 57 | #define ATC2609A_PMU_DC0_CTL3 0x1F |
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| 58 | #define ATC2609A_PMU_DC0_CTL4 0x20 |
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| 59 | #define ATC2609A_PMU_DC0_CTL5 0x21 |
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| 60 | #define ATC2609A_PMU_DC0_CTL6 0x22 |
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| 61 | #define ATC2609A_PMU_DC1_CTL0 0x23 |
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| 62 | #define ATC2609A_PMU_DC1_CTL1 0x24 |
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| 63 | #define ATC2609A_PMU_DC1_CTL2 0x25 |
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| 64 | #define ATC2609A_PMU_DC1_CTL3 0x26 |
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| 65 | #define ATC2609A_PMU_DC1_CTL4 0x27 |
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| 66 | #define ATC2609A_PMU_DC1_CTL5 0x28 |
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| 67 | #define ATC2609A_PMU_DC1_CTL6 0x29 |
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| 68 | #define ATC2609A_PMU_DC2_CTL0 0x2A |
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| 69 | #define ATC2609A_PMU_DC2_CTL1 0x2B |
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| 70 | #define ATC2609A_PMU_DC2_CTL2 0x2C |
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| 71 | #define ATC2609A_PMU_DC2_CTL3 0x2D |
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| 72 | #define ATC2609A_PMU_DC2_CTL4 0x2E |
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| 73 | #define ATC2609A_PMU_DC2_CTL5 0x2F |
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| 74 | #define ATC2609A_PMU_DC2_CTL6 0x30 |
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| 75 | #define ATC2609A_PMU_DC3_CTL0 0x31 |
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| 76 | #define ATC2609A_PMU_DC3_CTL1 0x32 |
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| 77 | #define ATC2609A_PMU_DC3_CTL2 0x33 |
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| 78 | #define ATC2609A_PMU_DC3_CTL3 0x34 |
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| 79 | #define ATC2609A_PMU_DC3_CTL4 0x35 |
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| 80 | #define ATC2609A_PMU_DC3_CTL5 0x36 |
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| 81 | #define ATC2609A_PMU_DC3_CTL6 0x37 |
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| 82 | #define ATC2609A_PMU_DC_ZR 0x38 |
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| 83 | #define ATC2609A_PMU_LDO0_CTL0 0x39 |
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| 84 | #define ATC2609A_PMU_LDO0_CTL1 0x3A |
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| 85 | #define ATC2609A_PMU_LDO1_CTL0 0x3B |
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| 86 | #define ATC2609A_PMU_LDO1_CTL1 0x3C |
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| 87 | #define ATC2609A_PMU_LDO2_CTL0 0x3D |
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| 88 | #define ATC2609A_PMU_LDO2_CTL1 0x3E |
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| 89 | #define ATC2609A_PMU_LDO3_CTL0 0x3F |
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| 90 | #define ATC2609A_PMU_LDO3_CTL1 0x40 |
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| 91 | #define ATC2609A_PMU_LDO4_CTL0 0x41 |
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| 92 | #define ATC2609A_PMU_LDO4_CTL1 0x42 |
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| 93 | #define ATC2609A_PMU_LDO5_CTL0 0x43 |
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| 94 | #define ATC2609A_PMU_LDO5_CTL1 0x44 |
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| 95 | #define ATC2609A_PMU_LDO6_CTL0 0x45 |
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| 96 | #define ATC2609A_PMU_LDO6_CTL1 0x46 |
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| 97 | #define ATC2609A_PMU_LDO7_CTL0 0x47 |
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| 98 | #define ATC2609A_PMU_LDO7_CTL1 0x48 |
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| 99 | #define ATC2609A_PMU_LDO8_CTL0 0x49 |
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| 100 | #define ATC2609A_PMU_LDO8_CTL1 0x4A |
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| 101 | #define ATC2609A_PMU_LDO9_CTL 0x4B |
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| 102 | #define ATC2609A_PMU_OV_INT_EN 0x4C |
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| 103 | #define ATC2609A_PMU_OV_STATUS 0x4D |
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| 104 | #define ATC2609A_PMU_UV_INT_EN 0x4E |
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| 105 | #define ATC2609A_PMU_UV_STATUS 0x4F |
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| 106 | #define ATC2609A_PMU_OC_INT_EN 0x50 |
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| 107 | #define ATC2609A_PMU_OC_STATUS 0x51 |
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| 108 | #define ATC2609A_PMU_OT_CTL 0x52 |
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| 109 | #define ATC2609A_PMU_CM_CTL0 0x53 |
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| 110 | #define ATC2609A_PMU_FW_USE0 0x54 |
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| 111 | #define ATC2609A_PMU_FW_USE1 0x55 |
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| 112 | #define ATC2609A_PMU_ADC12B_I 0x56 |
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| 113 | #define ATC2609A_PMU_ADC12B_V 0x57 |
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| 114 | #define ATC2609A_PMU_ADC12B_DUMMY 0x58 |
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| 115 | #define ATC2609A_PMU_AUXADC_CTL0 0x59 |
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| 116 | #define ATC2609A_PMU_AUXADC_CTL1 0x5A |
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| 117 | #define ATC2609A_PMU_BATVADC 0x5B |
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| 118 | #define ATC2609A_PMU_BATIADC 0x5C |
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| 119 | #define ATC2609A_PMU_WALLVADC 0x5D |
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| 120 | #define ATC2609A_PMU_WALLIADC 0x5E |
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| 121 | #define ATC2609A_PMU_VBUSVADC 0x5F |
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| 122 | #define ATC2609A_PMU_VBUSIADC 0x60 |
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| 123 | #define ATC2609A_PMU_SYSPWRADC 0x61 |
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| 124 | #define ATC2609A_PMU_REMCONADC 0x62 |
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| 125 | #define ATC2609A_PMU_SVCCADC 0x63 |
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| 126 | #define ATC2609A_PMU_CHGIADC 0x64 |
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| 127 | #define ATC2609A_PMU_IREFADC 0x65 |
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| 128 | #define ATC2609A_PMU_BAKBATADC 0x66 |
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| 129 | #define ATC2609A_PMU_ICTEMPADC 0x67 |
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| 130 | #define ATC2609A_PMU_AUXADC0 0x68 |
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| 131 | #define ATC2609A_PMU_AUXADC1 0x69 |
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| 132 | #define ATC2609A_PMU_AUXADC2 0x6A |
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| 133 | #define ATC2609A_PMU_AUXADC3 0x6B |
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| 134 | #define ATC2609A_PMU_ICTEMPADC_ADJ 0x6C |
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| 135 | #define ATC2609A_PMU_BDG_CTL 0x6D |
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| 136 | #define ATC2609A_RTC_CTL 0x6E |
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| 137 | #define ATC2609A_RTC_MSALM 0x6F |
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| 138 | #define ATC2609A_RTC_HALM 0x70 |
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| 139 | #define ATC2609A_RTC_YMDALM 0x71 |
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| 140 | #define ATC2609A_RTC_MS 0x72 |
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| 141 | #define ATC2609A_RTC_H 0x73 |
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| 142 | #define ATC2609A_RTC_DC 0x74 |
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| 143 | #define ATC2609A_RTC_YMD 0x75 |
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| 144 | #define ATC2609A_EFUSE_DAT 0x76 |
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| 145 | #define ATC2609A_EFUSECRTL1 0x77 |
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| 146 | #define ATC2609A_EFUSECRTL2 0x78 |
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| 147 | #define ATC2609A_PMU_DC4_CTL0 0x79 |
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| 148 | #define ATC2609A_PMU_DC4_CTL1 0x7A |
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| 149 | #define ATC2609A_PMU_DC4_CTL2 0x7B |
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| 150 | #define ATC2609A_PMU_DC4_CTL3 0x7C |
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| 151 | #define ATC2609A_PMU_DC4_CTL4 0x7D |
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| 152 | #define ATC2609A_PMU_DC4_CTL5 0x7E |
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| 153 | #define ATC2609A_PMU_DC4_CTL6 0x7F |
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| 154 | #define ATC2609A_PMU_PWR_STATUS 0x80 |
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| 155 | #define ATC2609A_PMU_S2_PWR 0x81 |
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| 156 | #define ATC2609A_CLMT_CTL0 0x82 |
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| 157 | #define ATC2609A_CLMT_DATA0 0x83 |
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| 158 | #define ATC2609A_CLMT_DATA1 0x84 |
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| 159 | #define ATC2609A_CLMT_DATA2 0x85 |
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| 160 | #define ATC2609A_CLMT_DATA3 0x86 |
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| 161 | #define ATC2609A_CLMT_ADD0 0x87 |
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| 162 | #define ATC2609A_CLMT_ADD1 0x88 |
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| 163 | #define ATC2609A_CLMT_OCV_TABLE 0x89 |
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| 164 | #define ATC2609A_CLMT_R_TABLE 0x8A |
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| 165 | #define ATC2609A_PMU_PWRON_CTL0 0x8D |
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| 166 | #define ATC2609A_PMU_PWRON_CTL1 0x8E |
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| 167 | #define ATC2609A_PMU_PWRON_CTL2 0x8F |
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| 168 | #define ATC2609A_IRC_CTL 0x90 |
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| 169 | #define ATC2609A_IRC_STAT 0x91 |
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| 170 | #define ATC2609A_IRC_CC 0x92 |
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| 171 | #define ATC2609A_IRC_KDC 0x93 |
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| 172 | #define ATC2609A_IRC_WK 0x94 |
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| 173 | #define ATC2609A_IRC_RCC 0x95 |
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| 174 | |
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| 175 | /* AUDIO_OUT Registers */ |
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| 176 | #define ATC2609A_AUDIOINOUT_CTL 0xA0 |
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| 177 | #define ATC2609A_AUDIO_DEBUGOUTCTL 0xA1 |
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| 178 | #define ATC2609A_DAC_DIGITALCTL 0xA2 |
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| 179 | #define ATC2609A_DAC_VOLUMECTL0 0xA3 |
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| 180 | #define ATC2609A_DAC_ANALOG0 0xA4 |
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| 181 | #define ATC2609A_DAC_ANALOG1 0xA5 |
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| 182 | #define ATC2609A_DAC_ANALOG2 0xA6 |
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| 183 | #define ATC2609A_DAC_ANALOG3 0xA7 |
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| 184 | |
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| 185 | /* AUDIO_IN Registers */ |
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| 186 | #define ATC2609A_ADC_DIGITALCTL 0xA8 |
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| 187 | #define ATC2609A_ADC_HPFCTL 0xA9 |
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| 188 | #define ATC2609A_ADC_CTL 0xAA |
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| 189 | #define ATC2609A_AGC_CTL0 0xAB |
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| 190 | #define ATC2609A_AGC_CTL1 0xAC |
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| 191 | #define ATC2609A_AGC_CTL2 0xAD |
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| 192 | #define ATC2609A_ADC_ANALOG0 0xAE |
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| 193 | #define ATC2609A_ADC_ANALOG1 0xAF |
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| 194 | |
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| 195 | /* PCM_IF Registers */ |
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| 196 | #define ATC2609A_PCM0_CTL 0xB0 |
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| 197 | #define ATC2609A_PCM1_CTL 0xB1 |
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| 198 | #define ATC2609A_PCM2_CTL 0xB2 |
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| 199 | #define ATC2609A_PCMIF_CTL 0xB3 |
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| 200 | |
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| 201 | /* CMU_CONTROL Registers */ |
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| 202 | #define ATC2609A_CMU_DEVRST 0xC1 |
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| 203 | |
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| 204 | /* INTS Registers */ |
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| 205 | #define ATC2609A_INTS_PD 0xC8 |
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| 206 | #define ATC2609A_INTS_MSK 0xC9 |
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| 207 | |
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| 208 | /* MFP Registers */ |
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| 209 | #define ATC2609A_MFP_CTL 0xD0 |
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| 210 | #define ATC2609A_PAD_VSEL 0xD1 |
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| 211 | #define ATC2609A_GPIO_OUTEN 0xD2 |
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| 212 | #define ATC2609A_GPIO_INEN 0xD3 |
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| 213 | #define ATC2609A_GPIO_DAT 0xD4 |
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| 214 | #define ATC2609A_PAD_DRV 0xD5 |
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| 215 | #define ATC2609A_PAD_EN 0xD6 |
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| 216 | #define ATC2609A_DEBUG_SEL 0xD7 |
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| 217 | #define ATC2609A_DEBUG_IE 0xD8 |
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| 218 | #define ATC2609A_DEBUG_OE 0xD9 |
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| 219 | #define ATC2609A_CHIP_VER 0xDC |
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| 220 | |
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| 221 | /* PWSI Registers */ |
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| 222 | #define ATC2609A_PWSI_CTL 0xF0 |
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| 223 | #define ATC2609A_PWSI_STATUS 0xF1 |
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| 224 | |
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| 225 | /* TWSI Registers */ |
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| 226 | #define ATC2609A_SADDR 0xFF |
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| 227 | |
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| 228 | /* PMU_SYS_CTL0 Register Mask Bits */ |
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| 229 | #define ATC2609A_PMU_SYS_CTL0_IR_WK_EN BIT(5) |
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| 230 | #define ATC2609A_PMU_SYS_CTL0_RESET_WK_EN BIT(6) |
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| 231 | #define ATC2609A_PMU_SYS_CTL0_HDSW_WK_EN BIT(7) |
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| 232 | #define ATC2609A_PMU_SYS_CTL0_ALARM_WK_EN BIT(8) |
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| 233 | #define ATC2609A_PMU_SYS_CTL0_REM_CON_WK_EN BIT(9) |
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| 234 | #define ATC2609A_PMU_SYS_CTL0_RESTART_EN BIT(10) |
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| 235 | #define ATC2609A_PMU_SYS_CTL0_WKIRQ_WK_EN BIT(11) |
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| 236 | #define ATC2609A_PMU_SYS_CTL0_ONOFF_SHORT_WK_EN BIT(12) |
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| 237 | #define ATC2609A_PMU_SYS_CTL0_ONOFF_LONG_WK_EN BIT(13) |
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| 238 | #define ATC2609A_PMU_SYS_CTL0_WALL_WK_EN BIT(14) |
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| 239 | #define ATC2609A_PMU_SYS_CTL0_USB_WK_EN BIT(15) |
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| 240 | #define ATC2609A_PMU_SYS_CTL0_WK_ALL (GENMASK(15, 5) & (~BIT(10))) |
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| 241 | |
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| 242 | /* PMU_SYS_CTL1 Register Mask Bits */ |
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| 243 | #define ATC2609A_PMU_SYS_CTL1_EN_S1 BIT(0) |
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| 244 | #define ATC2609A_PMU_SYS_CTL1_LB_S4_EN BIT(2) |
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| 245 | #define ATC2609A_PMU_SYS_CTL1_LB_S4 GENMASK(4, 3) |
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| 246 | #define ATC2609A_PMU_SYS_CTL1_LB_S4_3_1V BIT(4) |
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| 247 | #define ATC2609A_PMU_SYS_CTL1_IR_WK_FLAG BIT(5) |
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| 248 | #define ATC2609A_PMU_SYS_CTL1_RESET_WK_FLAG BIT(6) |
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| 249 | #define ATC2609A_PMU_SYS_CTL1_HDSW_WK_FLAG BIT(7) |
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| 250 | #define ATC2609A_PMU_SYS_CTL1_ALARM_WK_FLAG BIT(8) |
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| 251 | #define ATC2609A_PMU_SYS_CTL1_REM_CON_WK_FLAG BIT(9) |
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| 252 | #define ATC2609A_PMU_SYS_CTL1_RESTART_WK_FLAG BIT(10) |
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| 253 | #define ATC2609A_PMU_SYS_CTL1_WKIRQ_WK_FLAG BIT(11) |
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| 254 | #define ATC2609A_PMU_SYS_CTL1_ONOFF_SHORT_WK_FLAG BIT(12) |
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| 255 | #define ATC2609A_PMU_SYS_CTL1_ONOFF_LONG_WK_FLAG BIT(13) |
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| 256 | #define ATC2609A_PMU_SYS_CTL1_WALL_WK_FLAG BIT(14) |
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| 257 | #define ATC2609A_PMU_SYS_CTL1_USB_WK_FLAG BIT(15) |
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| 258 | |
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| 259 | /* PMU_SYS_CTL2 Register Mask Bits */ |
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| 260 | #define ATC2609A_PMU_SYS_CTL2_PMU_A_EN BIT(0) |
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| 261 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_INT_EN BIT(1) |
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| 262 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_PD BIT(2) |
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| 263 | #define ATC2609A_PMU_SYS_CTL2_S2TIMER GENMASK(5, 3) |
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| 264 | #define ATC2609A_PMU_SYS_CTL2_S2_TIMER_EN BIT(6) |
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| 265 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_TIME_SEL GENMASK(8, 7) |
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| 266 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_RESET_EN BIT(9) |
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| 267 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS_TIME GENMASK(11, 10) |
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| 268 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_LSP_INT_EN BIT(12) |
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| 269 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_LONG_PRESS BIT(13) |
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| 270 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_SHORT_PRESS BIT(14) |
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| 271 | #define ATC2609A_PMU_SYS_CTL2_ONOFF_PRESS BIT(15) |
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| 272 | |
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| 273 | /* PMU_SYS_CTL3 Register Mask Bits */ |
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| 274 | #define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER GENMASK(8, 7) |
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| 275 | #define ATC2609A_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN BIT(9) |
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| 276 | #define ATC2609A_PMU_SYS_CTL3_S3_TIMER GENMASK(12, 10) |
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| 277 | #define ATC2609A_PMU_SYS_CTL3_S3_TIMER_EN BIT(13) |
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| 278 | #define ATC2609A_PMU_SYS_CTL3_EN_S3 BIT(14) |
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| 279 | #define ATC2609A_PMU_SYS_CTL3_EN_S2 BIT(15) |
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| 280 | |
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| 281 | /* PMU_SYS_CTL5 Register Mask Bits */ |
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| 282 | #define ATC2609A_PMU_SYS_CTL5_WALLWKDTEN BIT(7) |
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| 283 | #define ATC2609A_PMU_SYS_CTL5_VBUSWKDTEN BIT(8) |
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| 284 | #define ATC2609A_PMU_SYS_CTL5_REMCON_DECT_EN BIT(9) |
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| 285 | #define ATC2609A_PMU_SYS_CTL5_ONOFF_8S_SEL BIT(10) |
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| 286 | |
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| 287 | /* INTS_MSK Register Mask Bits */ |
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| 288 | #define ATC2609A_INTS_MSK_AUDIO BIT(0) |
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| 289 | #define ATC2609A_INTS_MSK_OV BIT(1) |
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| 290 | #define ATC2609A_INTS_MSK_OC BIT(2) |
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| 291 | #define ATC2609A_INTS_MSK_OT BIT(3) |
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| 292 | #define ATC2609A_INTS_MSK_UV BIT(4) |
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| 293 | #define ATC2609A_INTS_MSK_ALARM BIT(5) |
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| 294 | #define ATC2609A_INTS_MSK_ONOFF BIT(6) |
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| 295 | #define ATC2609A_INTS_MSK_WKUP BIT(7) |
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| 296 | #define ATC2609A_INTS_MSK_IR BIT(8) |
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| 297 | #define ATC2609A_INTS_MSK_REMCON BIT(9) |
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| 298 | #define ATC2609A_INTS_MSK_POWERIN BIT(10) |
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| 299 | |
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| 300 | /* CMU_DEVRST Register Mask Bits */ |
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| 301 | #define ATC2609A_CMU_DEVRST_AUDIO BIT(0) |
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| 302 | #define ATC2609A_CMU_DEVRST_MFP BIT(1) |
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| 303 | #define ATC2609A_CMU_DEVRST_INTS BIT(2) |
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| 304 | |
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| 305 | /* PAD_EN Register Mask Bits */ |
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| 306 | #define ATC2609A_PAD_EN_EXTIRQ BIT(0) |
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| 307 | |
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| 308 | #endif /* __LINUX_MFD_ATC260X_ATC2609A_H */ |
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| 309 | |
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