1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#ifndef _I40E_ADMINQ_CMD_H_
5#define _I40E_ADMINQ_CMD_H_
6
7#include <linux/net/intel/libie/adminq.h>
8
9#include <linux/bits.h>
10#include <linux/types.h>
11
12/* This header file defines the i40e Admin Queue commands and is shared between
13 * i40e Firmware and Software.
14 *
15 * This file needs to comply with the Linux Kernel coding style.
16 */
17
18#define I40E_FW_API_VERSION_MAJOR 0x0001
19#define I40E_FW_API_VERSION_MINOR_X722 0x000C
20#define I40E_FW_API_VERSION_MINOR_X710 0x000F
21
22#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
23 I40E_FW_API_VERSION_MINOR_X710 : \
24 I40E_FW_API_VERSION_MINOR_X722)
25
26/* API version 1.7 implements additional link and PHY-specific APIs */
27#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
28/* API version 1.9 for X722 implements additional link and PHY-specific APIs */
29#define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
30/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
31#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
32/* API version 1.10 for X722 devices adds ability to request FEC encoding */
33#define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
34
35/* Admin Queue command opcodes */
36enum i40e_admin_queue_opc {
37 /* aq commands */
38 i40e_aqc_opc_get_version = 0x0001,
39 i40e_aqc_opc_driver_version = 0x0002,
40 i40e_aqc_opc_queue_shutdown = 0x0003,
41 i40e_aqc_opc_set_pf_context = 0x0004,
42
43 /* resource ownership */
44 i40e_aqc_opc_request_resource = 0x0008,
45 i40e_aqc_opc_release_resource = 0x0009,
46
47 i40e_aqc_opc_list_func_capabilities = 0x000A,
48 i40e_aqc_opc_list_dev_capabilities = 0x000B,
49
50 /* Proxy commands */
51 i40e_aqc_opc_set_proxy_config = 0x0104,
52 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
53
54 /* LAA */
55 i40e_aqc_opc_mac_address_read = 0x0107,
56 i40e_aqc_opc_mac_address_write = 0x0108,
57
58 /* PXE */
59 i40e_aqc_opc_clear_pxe_mode = 0x0110,
60
61 /* WoL commands */
62 i40e_aqc_opc_set_wol_filter = 0x0120,
63 i40e_aqc_opc_get_wake_reason = 0x0121,
64
65 /* internal switch commands */
66 i40e_aqc_opc_get_switch_config = 0x0200,
67 i40e_aqc_opc_add_statistics = 0x0201,
68 i40e_aqc_opc_remove_statistics = 0x0202,
69 i40e_aqc_opc_set_port_parameters = 0x0203,
70 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
71 i40e_aqc_opc_set_switch_config = 0x0205,
72 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
73 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
74
75 i40e_aqc_opc_add_vsi = 0x0210,
76 i40e_aqc_opc_update_vsi_parameters = 0x0211,
77 i40e_aqc_opc_get_vsi_parameters = 0x0212,
78
79 i40e_aqc_opc_add_pv = 0x0220,
80 i40e_aqc_opc_update_pv_parameters = 0x0221,
81 i40e_aqc_opc_get_pv_parameters = 0x0222,
82
83 i40e_aqc_opc_add_veb = 0x0230,
84 i40e_aqc_opc_update_veb_parameters = 0x0231,
85 i40e_aqc_opc_get_veb_parameters = 0x0232,
86
87 i40e_aqc_opc_delete_element = 0x0243,
88
89 i40e_aqc_opc_add_macvlan = 0x0250,
90 i40e_aqc_opc_remove_macvlan = 0x0251,
91 i40e_aqc_opc_add_vlan = 0x0252,
92 i40e_aqc_opc_remove_vlan = 0x0253,
93 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
94 i40e_aqc_opc_add_tag = 0x0255,
95 i40e_aqc_opc_remove_tag = 0x0256,
96 i40e_aqc_opc_add_multicast_etag = 0x0257,
97 i40e_aqc_opc_remove_multicast_etag = 0x0258,
98 i40e_aqc_opc_update_tag = 0x0259,
99 i40e_aqc_opc_add_control_packet_filter = 0x025A,
100 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
101 i40e_aqc_opc_add_cloud_filters = 0x025C,
102 i40e_aqc_opc_remove_cloud_filters = 0x025D,
103 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
104
105 i40e_aqc_opc_add_mirror_rule = 0x0260,
106 i40e_aqc_opc_delete_mirror_rule = 0x0261,
107
108 /* Dynamic Device Personalization */
109 i40e_aqc_opc_write_personalization_profile = 0x0270,
110 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
111
112 /* DCB commands */
113 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
114 i40e_aqc_opc_dcb_updated = 0x0302,
115 i40e_aqc_opc_set_dcb_parameters = 0x0303,
116
117 /* TX scheduler */
118 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
119 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
120 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
121 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
122 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
123 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
124
125 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
126 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
127 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
128 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
129 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
130 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
131 i40e_aqc_opc_query_port_ets_config = 0x0419,
132 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
133 i40e_aqc_opc_suspend_port_tx = 0x041B,
134 i40e_aqc_opc_resume_port_tx = 0x041C,
135 i40e_aqc_opc_configure_partition_bw = 0x041D,
136 /* hmc */
137 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
138 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
139
140 /* phy commands*/
141 i40e_aqc_opc_get_phy_abilities = 0x0600,
142 i40e_aqc_opc_set_phy_config = 0x0601,
143 i40e_aqc_opc_set_mac_config = 0x0603,
144 i40e_aqc_opc_set_link_restart_an = 0x0605,
145 i40e_aqc_opc_get_link_status = 0x0607,
146 i40e_aqc_opc_set_phy_int_mask = 0x0613,
147 i40e_aqc_opc_get_local_advt_reg = 0x0614,
148 i40e_aqc_opc_set_local_advt_reg = 0x0615,
149 i40e_aqc_opc_get_partner_advt = 0x0616,
150 i40e_aqc_opc_set_lb_modes = 0x0618,
151 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
152 i40e_aqc_opc_set_phy_debug = 0x0622,
153 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
154 i40e_aqc_opc_run_phy_activity = 0x0626,
155 i40e_aqc_opc_set_phy_register = 0x0628,
156 i40e_aqc_opc_get_phy_register = 0x0629,
157
158 /* NVM commands */
159 i40e_aqc_opc_nvm_read = 0x0701,
160 i40e_aqc_opc_nvm_erase = 0x0702,
161 i40e_aqc_opc_nvm_update = 0x0703,
162 i40e_aqc_opc_nvm_config_read = 0x0704,
163 i40e_aqc_opc_nvm_config_write = 0x0705,
164 i40e_aqc_opc_oem_post_update = 0x0720,
165 i40e_aqc_opc_thermal_sensor = 0x0721,
166
167 /* virtualization commands */
168 i40e_aqc_opc_send_msg_to_pf = 0x0801,
169 i40e_aqc_opc_send_msg_to_vf = 0x0802,
170 i40e_aqc_opc_send_msg_to_peer = 0x0803,
171
172 /* alternate structure */
173 i40e_aqc_opc_alternate_write = 0x0900,
174 i40e_aqc_opc_alternate_write_indirect = 0x0901,
175 i40e_aqc_opc_alternate_read = 0x0902,
176 i40e_aqc_opc_alternate_read_indirect = 0x0903,
177 i40e_aqc_opc_alternate_write_done = 0x0904,
178 i40e_aqc_opc_alternate_set_mode = 0x0905,
179 i40e_aqc_opc_alternate_clear_port = 0x0906,
180
181 /* LLDP commands */
182 i40e_aqc_opc_lldp_get_mib = 0x0A00,
183 i40e_aqc_opc_lldp_update_mib = 0x0A01,
184 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
185 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
186 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
187 i40e_aqc_opc_lldp_stop = 0x0A05,
188 i40e_aqc_opc_lldp_start = 0x0A06,
189 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
190 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
191 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
192 i40e_aqc_opc_lldp_restore = 0x0A0A,
193
194 /* Tunnel commands */
195 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
196 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
197 i40e_aqc_opc_set_rss_key = 0x0B02,
198 i40e_aqc_opc_set_rss_lut = 0x0B03,
199 i40e_aqc_opc_get_rss_key = 0x0B04,
200 i40e_aqc_opc_get_rss_lut = 0x0B05,
201
202 /* Async Events */
203 i40e_aqc_opc_event_lan_overflow = 0x1001,
204
205 /* OEM commands */
206 i40e_aqc_opc_oem_parameter_change = 0xFE00,
207 i40e_aqc_opc_oem_device_status_change = 0xFE01,
208 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
209 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
210
211 /* debug commands */
212 i40e_aqc_opc_debug_read_reg = 0xFF03,
213 i40e_aqc_opc_debug_write_reg = 0xFF04,
214 i40e_aqc_opc_debug_modify_reg = 0xFF07,
215 i40e_aqc_opc_debug_dump_internals = 0xFF08,
216};
217
218/* command structures and indirect data structures */
219
220/* Structure naming conventions:
221 * - no suffix for direct command descriptor structures
222 * - _data for indirect sent data
223 * - _resp for indirect return data (data which is both will use _data)
224 * - _completion for direct return data
225 * - _element_ for repeated elements (may also be _data or _resp)
226 *
227 * Command structures are expected to overlay the params.raw member of the basic
228 * descriptor, and as such cannot exceed 16 bytes in length.
229 */
230
231/* This macro is used to generate a compilation error if a structure
232 * is not exactly the correct length. It gives a divide by zero error if the
233 * structure is not of the correct size, otherwise it creates an enum that is
234 * never used.
235 */
236#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
237 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
238
239/* This macro is used extensively to ensure that command structures are 16
240 * bytes in length as they have to map to the raw array of that size.
241 */
242#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
243
244/* internal (0x00XX) commands */
245
246/* Get version (direct 0x0001) */
247struct i40e_aqc_get_version {
248 __le32 rom_ver;
249 __le32 fw_build;
250 __le16 fw_major;
251 __le16 fw_minor;
252 __le16 api_major;
253 __le16 api_minor;
254};
255
256/* Queue Shutdown (direct 0x0003) */
257struct i40e_aqc_queue_shutdown {
258 __le32 driver_unloading;
259#define I40E_AQ_DRIVER_UNLOADING 0x1
260 u8 reserved[12];
261};
262
263I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
264
265/* Set PF context (0x0004, direct) */
266struct i40e_aqc_set_pf_context {
267 u8 pf_id;
268 u8 reserved[15];
269};
270
271I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
272
273/* Set CPPM Configuration (direct 0x0103) */
274struct i40e_aqc_cppm_configuration {
275 __le16 command_flags;
276 __le16 ttlx;
277 __le32 dmacr;
278 __le16 dmcth;
279 u8 hptc;
280 u8 reserved;
281 __le32 pfltrc;
282};
283
284I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
285
286/* Set ARP Proxy command / response (indirect 0x0104) */
287struct i40e_aqc_arp_proxy_data {
288 __le16 command_flags;
289 __le16 table_id;
290 __le32 enabled_offloads;
291 __le32 ip_addr;
292 u8 mac_addr[6];
293 u8 reserved[2];
294};
295
296I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
297
298/* Set NS Proxy Table Entry Command (indirect 0x0105) */
299struct i40e_aqc_ns_proxy_data {
300 __le16 table_idx_mac_addr_0;
301 __le16 table_idx_mac_addr_1;
302 __le16 table_idx_ipv6_0;
303 __le16 table_idx_ipv6_1;
304 __le16 control;
305 u8 mac_addr_0[6];
306 u8 mac_addr_1[6];
307 u8 local_mac_addr[6];
308 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
309 u8 ipv6_addr_1[16];
310};
311
312I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
313
314/* Manage LAA Command (0x0106) - obsolete */
315struct i40e_aqc_mng_laa {
316 __le16 command_flags;
317 u8 reserved[2];
318 __le32 sal;
319 __le16 sah;
320 u8 reserved2[6];
321};
322
323I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
324
325/* Manage MAC Address Read Command (indirect 0x0107) */
326struct i40e_aqc_mac_address_read {
327 __le16 command_flags;
328#define I40E_AQC_LAN_ADDR_VALID 0x10
329#define I40E_AQC_PORT_ADDR_VALID 0x40
330 u8 reserved[6];
331 __le32 addr_high;
332 __le32 addr_low;
333};
334
335I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
336
337struct i40e_aqc_mac_address_read_data {
338 u8 pf_lan_mac[6];
339 u8 pf_san_mac[6];
340 u8 port_mac[6];
341 u8 pf_wol_mac[6];
342};
343
344I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
345
346/* Manage MAC Address Write Command (0x0108) */
347struct i40e_aqc_mac_address_write {
348 __le16 command_flags;
349#define I40E_AQC_MC_MAG_EN 0x0100
350#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
351#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
352#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
353#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
354
355 __le16 mac_sah;
356 __le32 mac_sal;
357 u8 reserved[8];
358};
359
360I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
361
362/* PXE commands (0x011x) */
363
364/* Clear PXE Command and response (direct 0x0110) */
365struct i40e_aqc_clear_pxe {
366 u8 rx_cnt;
367 u8 reserved[15];
368};
369
370I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
371
372/* Set WoL Filter (0x0120) */
373
374struct i40e_aqc_set_wol_filter {
375 __le16 filter_index;
376
377 __le16 cmd_flags;
378 __le16 valid_flags;
379 u8 reserved[2];
380 __le32 address_high;
381 __le32 address_low;
382};
383
384I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
385
386struct i40e_aqc_set_wol_filter_data {
387 u8 filter[128];
388 u8 mask[16];
389};
390
391I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
392
393/* Get Wake Reason (0x0121) */
394
395struct i40e_aqc_get_wake_reason_completion {
396 u8 reserved_1[2];
397 __le16 wake_reason;
398 u8 reserved_2[12];
399};
400
401I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
402
403/* Switch configuration commands (0x02xx) */
404
405/* Used by many indirect commands that only pass an seid and a buffer in the
406 * command
407 */
408struct i40e_aqc_switch_seid {
409 __le16 seid;
410 u8 reserved[6];
411 __le32 addr_high;
412 __le32 addr_low;
413};
414
415I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
416
417/* Get Switch Configuration command (indirect 0x0200)
418 * uses i40e_aqc_switch_seid for the descriptor
419 */
420struct i40e_aqc_get_switch_config_header_resp {
421 __le16 num_reported;
422 __le16 num_total;
423 u8 reserved[12];
424};
425
426I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
427
428struct i40e_aqc_switch_config_element_resp {
429 u8 element_type;
430 u8 revision;
431 __le16 seid;
432 __le16 uplink_seid;
433 __le16 downlink_seid;
434 u8 reserved[3];
435 u8 connection_type;
436 __le16 scheduler_id;
437 __le16 element_info;
438};
439
440I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
441
442/* Get Switch Configuration (indirect 0x0200)
443 * an array of elements are returned in the response buffer
444 * the first in the array is the header, remainder are elements
445 */
446struct i40e_aqc_get_switch_config_resp {
447 struct i40e_aqc_get_switch_config_header_resp header;
448 struct i40e_aqc_switch_config_element_resp element[1];
449};
450
451I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
452
453/* Add Statistics (direct 0x0201)
454 * Remove Statistics (direct 0x0202)
455 */
456struct i40e_aqc_add_remove_statistics {
457 __le16 seid;
458 __le16 vlan;
459 __le16 stat_index;
460 u8 reserved[10];
461};
462
463I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
464
465/* Set Port Parameters command (direct 0x0203) */
466struct i40e_aqc_set_port_parameters {
467 __le16 command_flags;
468 __le16 bad_frame_vsi;
469 __le16 default_seid; /* reserved for command */
470 u8 reserved[10];
471};
472
473I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
474
475/* Get Switch Resource Allocation (indirect 0x0204) */
476struct i40e_aqc_get_switch_resource_alloc {
477 u8 num_entries; /* reserved for command */
478 u8 reserved[7];
479 __le32 addr_high;
480 __le32 addr_low;
481};
482
483I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
484
485/* expect an array of these structs in the response buffer */
486struct i40e_aqc_switch_resource_alloc_element_resp {
487 u8 resource_type;
488 u8 reserved1;
489 __le16 guaranteed;
490 __le16 total;
491 __le16 used;
492 __le16 total_unalloced;
493 u8 reserved2[6];
494};
495
496I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
497
498/* Set Switch Configuration (direct 0x0205) */
499struct i40e_aqc_set_switch_config {
500 __le16 flags;
501/* flags used for both fields below */
502#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
503 __le16 valid_flags;
504 /* The ethertype in switch_tag is dropped on ingress and used
505 * internally by the switch. Set this to zero for the default
506 * of 0x88a8 (802.1ad). Should be zero for firmware API
507 * versions lower than 1.7.
508 */
509 __le16 switch_tag;
510 /* The ethertypes in first_tag and second_tag are used to
511 * match the outer and inner VLAN tags (respectively) when HW
512 * double VLAN tagging is enabled via the set port parameters
513 * AQ command. Otherwise these are both ignored. Set them to
514 * zero for their defaults of 0x8100 (802.1Q). Should be zero
515 * for firmware API versions lower than 1.7.
516 */
517 __le16 first_tag;
518 __le16 second_tag;
519 /* Next byte is split into following:
520 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
521 * Bit 6 : 0 : Destination Port, 1: source port
522 * Bit 5..4 : L4 type
523 * 0: rsvd
524 * 1: TCP
525 * 2: UDP
526 * 3: Both TCP and UDP
527 * Bits 3:0 Mode
528 * 0: default mode
529 * 1: L4 port only mode
530 * 2: non-tunneled mode
531 * 3: tunneled mode
532 */
533#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
534
535
536#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
537
538#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
539 u8 mode;
540 u8 rsvd5[5];
541};
542
543I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
544
545/* Read Receive control registers (direct 0x0206)
546 * Write Receive control registers (direct 0x0207)
547 * used for accessing Rx control registers that can be
548 * slow and need special handling when under high Rx load
549 */
550struct i40e_aqc_rx_ctl_reg_read_write {
551 __le32 reserved1;
552 __le32 address;
553 __le32 reserved2;
554 __le32 value;
555};
556
557I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
558
559/* Add VSI (indirect 0x0210)
560 * this indirect command uses struct i40e_aqc_vsi_properties_data
561 * as the indirect buffer (128 bytes)
562 *
563 * Update VSI (indirect 0x211)
564 * uses the same data structure as Add VSI
565 *
566 * Get VSI (indirect 0x0212)
567 * uses the same completion and data structure as Add VSI
568 */
569struct i40e_aqc_add_get_update_vsi {
570 __le16 uplink_seid;
571 u8 connection_type;
572#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
573 u8 reserved1;
574 u8 vf_id;
575 u8 reserved2;
576 __le16 vsi_flags;
577#define I40E_AQ_VSI_TYPE_VF 0x0
578#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
579#define I40E_AQ_VSI_TYPE_PF 0x2
580 __le32 addr_high;
581 __le32 addr_low;
582};
583
584I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
585
586struct i40e_aqc_add_get_update_vsi_completion {
587 __le16 seid;
588 __le16 vsi_number;
589 __le16 vsi_used;
590 __le16 vsi_free;
591 __le32 addr_high;
592 __le32 addr_low;
593};
594
595I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
596
597struct i40e_aqc_vsi_properties_data {
598 /* first 96 byte are written by SW */
599 __le16 valid_sections;
600#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
601#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
602#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
603#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
604#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
605#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
606 /* switch section */
607 __le16 switch_id; /* 12bit id combined with flags below */
608#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
609#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
610#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
611#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
612 u8 sw_reserved[2];
613 /* security section */
614 u8 sec_flags;
615#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
616#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
617 u8 sec_reserved;
618 /* VLAN section */
619 __le16 pvid; /* VLANS include priority bits */
620 __le16 fcoe_pvid;
621 u8 port_vlan_flags;
622#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
623#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
624 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
625#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
626#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
627#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
628#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
629#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
630 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
631#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
632#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
633#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
634 u8 pvlan_reserved[3];
635 /* ingress egress up sections */
636 __le32 ingress_table; /* bitmap, 3 bits per up */
637 __le32 egress_table; /* same defines as for ingress table */
638 /* cascaded PV section */
639 __le16 cas_pv_tag;
640 u8 cas_pv_flags;
641 u8 cas_pv_reserved;
642 /* queue mapping section */
643 __le16 mapping_flags;
644#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
645#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
646 __le16 queue_mapping[16];
647 __le16 tc_mapping[8];
648#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
649#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
650 /* queueing option section */
651 u8 queueing_opt_flags;
652#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
653#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
654 u8 queueing_opt_reserved[3];
655 /* scheduler section */
656 u8 up_enable_bits;
657 u8 sched_reserved;
658 /* outer up section */
659 __le32 outer_up_table; /* same structure and defines as ingress tbl */
660 u8 cmd_reserved[8];
661 /* last 32 bytes are written by FW */
662 __le16 qs_handle[8];
663#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
664 __le16 stat_counter_idx;
665 __le16 sched_id;
666 u8 resp_reserved[12];
667};
668
669I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
670
671/* Add Port Virtualizer (direct 0x0220)
672 * also used for update PV (direct 0x0221) but only flags are used
673 * (IS_CTRL_PORT only works on add PV)
674 */
675struct i40e_aqc_add_update_pv {
676 __le16 command_flags;
677 __le16 uplink_seid;
678 __le16 connected_seid;
679 u8 reserved[10];
680};
681
682I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
683
684struct i40e_aqc_add_update_pv_completion {
685 /* reserved for update; for add also encodes error if rc == ENOSPC */
686 __le16 pv_seid;
687 u8 reserved[14];
688};
689
690I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
691
692/* Get PV Params (direct 0x0222)
693 * uses i40e_aqc_switch_seid for the descriptor
694 */
695
696struct i40e_aqc_get_pv_params_completion {
697 __le16 seid;
698 __le16 default_stag;
699 __le16 pv_flags; /* same flags as add_pv */
700 u8 reserved[8];
701 __le16 default_port_seid;
702};
703
704I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
705
706/* Add VEB (direct 0x0230) */
707struct i40e_aqc_add_veb {
708 __le16 uplink_seid;
709 __le16 downlink_seid;
710 __le16 veb_flags;
711#define I40E_AQC_ADD_VEB_FLOATING 0x1
712#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
713#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
714#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
715 u8 enable_tcs;
716 u8 reserved[9];
717};
718
719I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
720
721struct i40e_aqc_add_veb_completion {
722 u8 reserved[6];
723 __le16 switch_seid;
724 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
725 __le16 veb_seid;
726 __le16 statistic_index;
727 __le16 vebs_used;
728 __le16 vebs_free;
729};
730
731I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
732
733/* Get VEB Parameters (direct 0x0232)
734 * uses i40e_aqc_switch_seid for the descriptor
735 */
736struct i40e_aqc_get_veb_parameters_completion {
737 __le16 seid;
738 __le16 switch_id;
739 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
740 __le16 statistic_index;
741 __le16 vebs_used;
742 __le16 vebs_free;
743 u8 reserved[4];
744};
745
746I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
747
748/* Delete Element (direct 0x0243)
749 * uses the generic i40e_aqc_switch_seid
750 */
751
752/* Add MAC-VLAN (indirect 0x0250) */
753
754/* used for the command for most vlan commands */
755struct i40e_aqc_macvlan {
756 __le16 num_addresses;
757 __le16 seid[3];
758#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
759 __le32 addr_high;
760 __le32 addr_low;
761};
762
763I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
764
765/* indirect data for command and response */
766struct i40e_aqc_add_macvlan_element_data {
767 u8 mac_addr[6];
768 __le16 vlan_tag;
769 __le16 flags;
770#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
771#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
772#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
773 __le16 queue_number;
774 /* response section */
775 u8 match_method;
776#define I40E_AQC_MM_ERR_NO_RES 0xFF
777 u8 reserved1[3];
778};
779
780struct i40e_aqc_add_remove_macvlan_completion {
781 __le16 perfect_mac_used;
782 __le16 perfect_mac_free;
783 __le16 unicast_hash_free;
784 __le16 multicast_hash_free;
785 __le32 addr_high;
786 __le32 addr_low;
787};
788
789I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
790
791/* Remove MAC-VLAN (indirect 0x0251)
792 * uses i40e_aqc_macvlan for the descriptor
793 * data points to an array of num_addresses of elements
794 */
795
796struct i40e_aqc_remove_macvlan_element_data {
797 u8 mac_addr[6];
798 __le16 vlan_tag;
799 u8 flags;
800#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
801#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
802 u8 reserved[3];
803 /* reply section */
804 u8 error_code;
805 u8 reply_reserved[3];
806};
807
808/* Add VLAN (indirect 0x0252)
809 * Remove VLAN (indirect 0x0253)
810 * use the generic i40e_aqc_macvlan for the command
811 */
812struct i40e_aqc_add_remove_vlan_element_data {
813 __le16 vlan_tag;
814 u8 vlan_flags;
815 u8 reserved;
816 u8 result;
817 u8 reserved1[3];
818};
819
820struct i40e_aqc_add_remove_vlan_completion {
821 u8 reserved[4];
822 __le16 vlans_used;
823 __le16 vlans_free;
824 __le32 addr_high;
825 __le32 addr_low;
826};
827
828/* Set VSI Promiscuous Modes (direct 0x0254) */
829struct i40e_aqc_set_vsi_promiscuous_modes {
830 __le16 promiscuous_flags;
831 __le16 valid_flags;
832/* flags used for both fields above */
833#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
834#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
835#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
836#define I40E_AQC_SET_VSI_DEFAULT 0x08
837#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
838#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
839 __le16 seid;
840 __le16 vlan_tag;
841#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
842 u8 reserved[8];
843};
844
845I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
846
847/* Add S/E-tag command (direct 0x0255)
848 * Uses generic i40e_aqc_add_remove_tag_completion for completion
849 */
850struct i40e_aqc_add_tag {
851 __le16 flags;
852 __le16 seid;
853 __le16 tag;
854 __le16 queue_number;
855 u8 reserved[8];
856};
857
858I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
859
860struct i40e_aqc_add_remove_tag_completion {
861 u8 reserved[12];
862 __le16 tags_used;
863 __le16 tags_free;
864};
865
866I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
867
868/* Remove S/E-tag command (direct 0x0256)
869 * Uses generic i40e_aqc_add_remove_tag_completion for completion
870 */
871struct i40e_aqc_remove_tag {
872 __le16 seid;
873 __le16 tag;
874 u8 reserved[12];
875};
876
877I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
878
879/* Add multicast E-Tag (direct 0x0257)
880 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
881 * and no external data
882 */
883struct i40e_aqc_add_remove_mcast_etag {
884 __le16 pv_seid;
885 __le16 etag;
886 u8 num_unicast_etags;
887 u8 reserved[3];
888 __le32 addr_high; /* address of array of 2-byte s-tags */
889 __le32 addr_low;
890};
891
892I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
893
894struct i40e_aqc_add_remove_mcast_etag_completion {
895 u8 reserved[4];
896 __le16 mcast_etags_used;
897 __le16 mcast_etags_free;
898 __le32 addr_high;
899 __le32 addr_low;
900
901};
902
903I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
904
905/* Update S/E-Tag (direct 0x0259) */
906struct i40e_aqc_update_tag {
907 __le16 seid;
908 __le16 old_tag;
909 __le16 new_tag;
910 u8 reserved[10];
911};
912
913I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
914
915struct i40e_aqc_update_tag_completion {
916 u8 reserved[12];
917 __le16 tags_used;
918 __le16 tags_free;
919};
920
921I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
922
923/* Add Control Packet filter (direct 0x025A)
924 * Remove Control Packet filter (direct 0x025B)
925 * uses the i40e_aqc_add_oveb_cloud,
926 * and the generic direct completion structure
927 */
928struct i40e_aqc_add_remove_control_packet_filter {
929 u8 mac[6];
930 __le16 etype;
931 __le16 flags;
932#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
933#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
934#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
935#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
936 __le16 seid;
937 __le16 queue;
938 u8 reserved[2];
939};
940
941I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
942
943struct i40e_aqc_add_remove_control_packet_filter_completion {
944 __le16 mac_etype_used;
945 __le16 etype_used;
946 __le16 mac_etype_free;
947 __le16 etype_free;
948 u8 reserved[8];
949};
950
951I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
952
953/* Add Cloud filters (indirect 0x025C)
954 * Remove Cloud filters (indirect 0x025D)
955 * uses the i40e_aqc_add_remove_cloud_filters,
956 * and the generic indirect completion structure
957 */
958struct i40e_aqc_add_remove_cloud_filters {
959 u8 num_filters;
960 u8 reserved;
961 __le16 seid;
962 u8 big_buffer_flag;
963#define I40E_AQC_ADD_CLOUD_CMD_BB 1
964 u8 reserved2[3];
965 __le32 addr_high;
966 __le32 addr_low;
967};
968
969I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
970
971struct i40e_aqc_cloud_filters_element_data {
972 u8 outer_mac[6];
973 u8 inner_mac[6];
974 __le16 inner_vlan;
975 union {
976 struct {
977 u8 reserved[12];
978 u8 data[4];
979 } v4;
980 struct {
981 u8 data[16];
982 } v6;
983 struct {
984 __le16 data[8];
985 } raw_v6;
986 } ipaddr;
987 __le16 flags;
988/* 0x0000 reserved */
989/* 0x0001 reserved */
990/* 0x0002 reserved */
991#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
992#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
993/* 0x0005 reserved */
994#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
995/* 0x0007 reserved */
996/* 0x0008 reserved */
997#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
998#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
999#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1000#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1001/* 0x000D reserved */
1002/* 0x000E reserved */
1003/* 0x000F reserved */
1004/* 0x0010 to 0x0017 is for custom filters */
1005#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1006#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1007#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1008
1009#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1010#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1011
1012#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1013#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1014#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1015
1016
1017 __le32 tenant_id;
1018 u8 reserved[4];
1019 __le16 queue_number;
1020 u8 reserved2[14];
1021 /* response section */
1022 u8 allocation_result;
1023 u8 response_reserved[7];
1024};
1025
1026I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1027
1028/* i40e_aqc_cloud_filters_element_bb is used when
1029 * I40E_AQC_CLOUD_CMD_BB flag is set.
1030 */
1031struct i40e_aqc_cloud_filters_element_bb {
1032 struct i40e_aqc_cloud_filters_element_data element;
1033 u16 general_fields[32];
1034#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1035};
1036
1037I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1038
1039struct i40e_aqc_remove_cloud_filters_completion {
1040 __le16 perfect_ovlan_used;
1041 __le16 perfect_ovlan_free;
1042 __le16 vlan_used;
1043 __le16 vlan_free;
1044 __le32 addr_high;
1045 __le32 addr_low;
1046};
1047
1048I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1049
1050/* Replace filter Command 0x025F
1051 * uses the i40e_aqc_replace_cloud_filters,
1052 * and the generic indirect completion structure
1053 */
1054struct i40e_filter_data {
1055 u8 filter_type;
1056 u8 input[3];
1057};
1058
1059I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1060
1061struct i40e_aqc_replace_cloud_filters_cmd {
1062 u8 valid_flags;
1063 u8 old_filter_type;
1064 u8 new_filter_type;
1065 u8 tr_bit;
1066 u8 reserved[4];
1067 __le32 addr_high;
1068 __le32 addr_low;
1069};
1070
1071I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1072
1073struct i40e_aqc_replace_cloud_filters_cmd_buf {
1074 u8 data[32];
1075 struct i40e_filter_data filters[8];
1076};
1077
1078I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1079
1080/* Add Mirror Rule (indirect or direct 0x0260)
1081 * Delete Mirror Rule (indirect or direct 0x0261)
1082 * note: some rule types (4,5) do not use an external buffer.
1083 * take care to set the flags correctly.
1084 */
1085struct i40e_aqc_add_delete_mirror_rule {
1086 __le16 seid;
1087 __le16 rule_type;
1088#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1089#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1090 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1091#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1092#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1093#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1094 __le16 num_entries;
1095 __le16 destination; /* VSI for add, rule id for delete */
1096 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1097 __le32 addr_low;
1098};
1099
1100I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1101
1102struct i40e_aqc_add_delete_mirror_rule_completion {
1103 u8 reserved[2];
1104 __le16 rule_id; /* only used on add */
1105 __le16 mirror_rules_used;
1106 __le16 mirror_rules_free;
1107 __le32 addr_high;
1108 __le32 addr_low;
1109};
1110
1111I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1112
1113/* Dynamic Device Personalization */
1114struct i40e_aqc_write_personalization_profile {
1115 u8 flags;
1116 u8 reserved[3];
1117 __le32 profile_track_id;
1118 __le32 addr_high;
1119 __le32 addr_low;
1120};
1121
1122I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1123
1124struct i40e_aqc_write_ddp_resp {
1125 __le32 error_offset;
1126 __le32 error_info;
1127 __le32 addr_high;
1128 __le32 addr_low;
1129};
1130
1131struct i40e_aqc_get_applied_profiles {
1132 u8 flags;
1133 u8 rsv[3];
1134 __le32 reserved;
1135 __le32 addr_high;
1136 __le32 addr_low;
1137};
1138
1139I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1140
1141/* DCB 0x03xx*/
1142
1143/* PFC Ignore (direct 0x0301)
1144 * the command and response use the same descriptor structure
1145 */
1146struct i40e_aqc_pfc_ignore {
1147 u8 tc_bitmap;
1148 u8 command_flags; /* unused on response */
1149 u8 reserved[14];
1150};
1151
1152I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1153
1154/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1155 * with no parameters
1156 */
1157
1158/* TX scheduler 0x04xx */
1159
1160/* Almost all the indirect commands use
1161 * this generic struct to pass the SEID in param0
1162 */
1163struct i40e_aqc_tx_sched_ind {
1164 __le16 vsi_seid;
1165 u8 reserved[6];
1166 __le32 addr_high;
1167 __le32 addr_low;
1168};
1169
1170I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1171
1172/* Several commands respond with a set of queue set handles */
1173struct i40e_aqc_qs_handles_resp {
1174 __le16 qs_handles[8];
1175};
1176
1177/* Configure VSI BW limits (direct 0x0400) */
1178struct i40e_aqc_configure_vsi_bw_limit {
1179 __le16 vsi_seid;
1180 u8 reserved[2];
1181 __le16 credit;
1182 u8 reserved1[2];
1183 u8 max_credit; /* 0-3, limit = 2^max */
1184 u8 reserved2[7];
1185};
1186
1187I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1188
1189/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1190 * responds with i40e_aqc_qs_handles_resp
1191 */
1192struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1193 u8 tc_valid_bits;
1194 u8 reserved[15];
1195 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1196
1197 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1198 __le16 tc_bw_max[2];
1199 u8 reserved1[28];
1200};
1201
1202I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1203
1204/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1205 * responds with i40e_aqc_qs_handles_resp
1206 */
1207struct i40e_aqc_configure_vsi_tc_bw_data {
1208 u8 tc_valid_bits;
1209 u8 reserved[3];
1210 u8 tc_bw_credits[8];
1211 u8 reserved1[4];
1212 __le16 qs_handles[8];
1213};
1214
1215I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1216
1217/* Query vsi bw configuration (indirect 0x0408) */
1218struct i40e_aqc_query_vsi_bw_config_resp {
1219 u8 tc_valid_bits;
1220 u8 tc_suspended_bits;
1221 u8 reserved[14];
1222 __le16 qs_handles[8];
1223 u8 reserved1[4];
1224 __le16 port_bw_limit;
1225 u8 reserved2[2];
1226 u8 max_bw; /* 0-3, limit = 2^max */
1227 u8 reserved3[23];
1228};
1229
1230I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1231
1232/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1233struct i40e_aqc_query_vsi_ets_sla_config_resp {
1234 u8 tc_valid_bits;
1235 u8 reserved[3];
1236 u8 share_credits[8];
1237 __le16 credits[8];
1238
1239 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1240 __le16 tc_bw_max[2];
1241};
1242
1243I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1244
1245/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1246struct i40e_aqc_configure_switching_comp_bw_limit {
1247 __le16 seid;
1248 u8 reserved[2];
1249 __le16 credit;
1250 u8 reserved1[2];
1251 u8 max_bw; /* 0-3, limit = 2^max */
1252 u8 reserved2[7];
1253};
1254
1255I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1256
1257/* Enable Physical Port ETS (indirect 0x0413)
1258 * Modify Physical Port ETS (indirect 0x0414)
1259 * Disable Physical Port ETS (indirect 0x0415)
1260 */
1261struct i40e_aqc_configure_switching_comp_ets_data {
1262 u8 reserved[4];
1263 u8 tc_valid_bits;
1264 u8 seepage;
1265 u8 tc_strict_priority_flags;
1266 u8 reserved1[17];
1267 u8 tc_bw_share_credits[8];
1268 u8 reserved2[96];
1269};
1270
1271I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1272
1273/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1274struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1275 u8 tc_valid_bits;
1276 u8 reserved[15];
1277 __le16 tc_bw_credit[8];
1278
1279 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1280 __le16 tc_bw_max[2];
1281 u8 reserved1[28];
1282};
1283
1284I40E_CHECK_STRUCT_LEN(0x40,
1285 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1286
1287/* Configure Switching Component Bandwidth Allocation per Tc
1288 * (indirect 0x0417)
1289 */
1290struct i40e_aqc_configure_switching_comp_bw_config_data {
1291 u8 tc_valid_bits;
1292 u8 reserved[2];
1293 u8 absolute_credits; /* bool */
1294 u8 tc_bw_share_credits[8];
1295 u8 reserved1[20];
1296};
1297
1298I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1299
1300/* Query Switching Component Configuration (indirect 0x0418) */
1301struct i40e_aqc_query_switching_comp_ets_config_resp {
1302 u8 tc_valid_bits;
1303 u8 reserved[35];
1304 __le16 port_bw_limit;
1305 u8 reserved1[2];
1306 u8 tc_bw_max; /* 0-3, limit = 2^max */
1307 u8 reserved2[23];
1308};
1309
1310I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1311
1312/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1313struct i40e_aqc_query_port_ets_config_resp {
1314 u8 reserved[4];
1315 u8 tc_valid_bits;
1316 u8 reserved1;
1317 u8 tc_strict_priority_bits;
1318 u8 reserved2;
1319 u8 tc_bw_share_credits[8];
1320 __le16 tc_bw_limits[8];
1321
1322 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1323 __le16 tc_bw_max[2];
1324 u8 reserved3[32];
1325};
1326
1327I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1328
1329/* Query Switching Component Bandwidth Allocation per Traffic Type
1330 * (indirect 0x041A)
1331 */
1332struct i40e_aqc_query_switching_comp_bw_config_resp {
1333 u8 tc_valid_bits;
1334 u8 reserved[2];
1335 u8 absolute_credits_enable; /* bool */
1336 u8 tc_bw_share_credits[8];
1337 __le16 tc_bw_limits[8];
1338
1339 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1340 __le16 tc_bw_max[2];
1341};
1342
1343I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1344
1345/* Suspend/resume port TX traffic
1346 * (direct 0x041B and 0x041C) uses the generic SEID struct
1347 */
1348
1349/* Configure partition BW
1350 * (indirect 0x041D)
1351 */
1352struct i40e_aqc_configure_partition_bw_data {
1353 __le16 pf_valid_bits;
1354 u8 min_bw[16]; /* guaranteed bandwidth */
1355 u8 max_bw[16]; /* bandwidth limit */
1356};
1357
1358I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1359
1360/* Get and set the active HMC resource profile and status.
1361 * (direct 0x0500) and (direct 0x0501)
1362 */
1363struct i40e_aq_get_set_hmc_resource_profile {
1364 u8 pm_profile;
1365 u8 pe_vf_enabled;
1366 u8 reserved[14];
1367};
1368
1369I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1370
1371enum i40e_aq_hmc_profile {
1372 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1373 I40E_HMC_PROFILE_DEFAULT = 1,
1374 I40E_HMC_PROFILE_FAVOR_VF = 2,
1375 I40E_HMC_PROFILE_EQUAL = 3,
1376};
1377
1378/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1379
1380/* set in param0 for get phy abilities to report qualified modules */
1381#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1382#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1383
1384enum i40e_aq_phy_type {
1385 I40E_PHY_TYPE_SGMII = 0x0,
1386 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1387 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1388 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1389 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1390 I40E_PHY_TYPE_XAUI = 0x5,
1391 I40E_PHY_TYPE_XFI = 0x6,
1392 I40E_PHY_TYPE_SFI = 0x7,
1393 I40E_PHY_TYPE_XLAUI = 0x8,
1394 I40E_PHY_TYPE_XLPPI = 0x9,
1395 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1396 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1397 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1398 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1399 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1400 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1401 I40E_PHY_TYPE_100BASE_TX = 0x11,
1402 I40E_PHY_TYPE_1000BASE_T = 0x12,
1403 I40E_PHY_TYPE_10GBASE_T = 0x13,
1404 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1405 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1406 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1407 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1408 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1409 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1410 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1411 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1412 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1413 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1414 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1415 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1416 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1417 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1418 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1419 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1420 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1421 I40E_PHY_TYPE_2_5GBASE_T = 0x26,
1422 I40E_PHY_TYPE_5GBASE_T = 0x27,
1423 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
1424 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
1425 I40E_PHY_TYPE_MAX,
1426 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1427 I40E_PHY_TYPE_EMPTY = 0xFE,
1428 I40E_PHY_TYPE_DEFAULT = 0xFF,
1429};
1430
1431#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1432 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1433 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1434 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1435 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1436 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1437 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1438 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1439 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1440 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1441 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1442 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1443 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1444 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1445 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1446 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1447 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1448 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1449 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1450 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1451 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1452 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1453 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1454 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1455 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1456 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1457 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1458 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1459 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1460 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1461 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1462 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1463 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1464 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1465 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1466 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1467 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1468 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1469
1470#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1471#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1472#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1473#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1474#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1475#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1476#define I40E_LINK_SPEED_25GB_SHIFT 0x6
1477#define I40E_LINK_SPEED_5GB_SHIFT 0x7
1478
1479enum i40e_aq_link_speed {
1480 I40E_LINK_SPEED_UNKNOWN = 0,
1481 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1482 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1483 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1484 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1485 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1486 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1487 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1488 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1489};
1490
1491struct i40e_aqc_module_desc {
1492 u8 oui[3];
1493 u8 reserved1;
1494 u8 part_number[16];
1495 u8 revision[4];
1496 u8 reserved2[8];
1497};
1498
1499I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1500
1501struct i40e_aq_get_phy_abilities_resp {
1502 __le32 phy_type; /* bitmap using the above enum for offsets */
1503 u8 link_speed; /* bitmap using the above enum bit patterns */
1504 u8 abilities;
1505#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1506#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1507 __le16 eee_capability;
1508 __le32 eeer_val;
1509 u8 d3_lpan;
1510 u8 phy_type_ext;
1511#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1512#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1513#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1514#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1515 u8 fec_cfg_curr_mod_ext_info;
1516#define I40E_AQ_REQUEST_FEC_KR 0x04
1517#define I40E_AQ_REQUEST_FEC_RS 0x08
1518#define I40E_AQ_ENABLE_FEC_AUTO 0x10
1519
1520 u8 ext_comp_code;
1521 u8 phy_id[4];
1522 u8 module_type[3];
1523 u8 qualified_module_count;
1524#define I40E_AQ_PHY_MAX_QMS 16
1525 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1526};
1527
1528I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1529
1530/* Set PHY Config (direct 0x0601) */
1531struct i40e_aq_set_phy_config { /* same bits as above in all */
1532 __le32 phy_type;
1533 u8 link_speed;
1534 u8 abilities;
1535/* bits 0-2 use the values from get_phy_abilities_resp */
1536#define I40E_AQ_PHY_ENABLE_LINK 0x08
1537#define I40E_AQ_PHY_ENABLE_AN 0x10
1538#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1539 __le16 eee_capability;
1540 __le32 eeer;
1541 u8 low_power_ctrl;
1542 u8 phy_type_ext;
1543#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1544#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1545#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1546#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1547 u8 fec_config;
1548#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1549#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1550#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1551#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1552#define I40E_AQ_SET_FEC_AUTO BIT(4)
1553#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1554#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1555 u8 reserved;
1556};
1557
1558I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1559
1560/* Set MAC Config command data structure (direct 0x0603) */
1561struct i40e_aq_set_mac_config {
1562 __le16 max_frame_size;
1563 u8 params;
1564#define I40E_AQ_SET_MAC_CONFIG_CRC_EN BIT(2)
1565 u8 tx_timer_priority; /* bitmap */
1566 __le16 tx_timer_value;
1567 __le16 fc_refresh_threshold;
1568 u8 reserved[8];
1569};
1570
1571I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1572
1573/* Restart Auto-Negotiation (direct 0x605) */
1574struct i40e_aqc_set_link_restart_an {
1575 u8 command;
1576#define I40E_AQ_PHY_RESTART_AN 0x02
1577#define I40E_AQ_PHY_LINK_ENABLE 0x04
1578 u8 reserved[15];
1579};
1580
1581I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1582
1583/* Get Link Status cmd & response data structure (direct 0x0607) */
1584struct i40e_aqc_get_link_status {
1585 __le16 command_flags; /* only field set on command */
1586#define I40E_AQ_LSE_DISABLE 0x2
1587#define I40E_AQ_LSE_ENABLE 0x3
1588/* only response uses this flag */
1589#define I40E_AQ_LSE_IS_ENABLED 0x1
1590 u8 phy_type; /* i40e_aq_phy_type */
1591 u8 link_speed; /* i40e_aq_link_speed */
1592 u8 link_info;
1593#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1594#define I40E_AQ_MEDIA_AVAILABLE 0x40
1595 u8 an_info;
1596#define I40E_AQ_AN_COMPLETED 0x01
1597#define I40E_AQ_LINK_PAUSE_TX 0x20
1598#define I40E_AQ_LINK_PAUSE_RX 0x40
1599#define I40E_AQ_QUALIFIED_MODULE 0x80
1600 u8 ext_info;
1601 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1602/* Since firmware API 1.7 loopback field keeps power class info as well */
1603#define I40E_AQ_LOOPBACK_MASK 0x07
1604 __le16 max_frame_size;
1605 u8 config;
1606#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1607#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1608#define I40E_AQ_CONFIG_CRC_ENA 0x04
1609#define I40E_AQ_CONFIG_PACING_MASK 0x78
1610 union {
1611 struct {
1612 u8 power_desc;
1613 u8 reserved[4];
1614 };
1615 struct {
1616 u8 link_type[4];
1617 u8 link_type_ext;
1618 };
1619 };
1620};
1621
1622I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1623
1624/* Set event mask command (direct 0x613) */
1625struct i40e_aqc_set_phy_int_mask {
1626 u8 reserved[8];
1627 __le16 event_mask;
1628#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1629#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1630#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1631 u8 reserved1[6];
1632};
1633
1634I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1635
1636/* Get Local AN advt register (direct 0x0614)
1637 * Set Local AN advt register (direct 0x0615)
1638 * Get Link Partner AN advt register (direct 0x0616)
1639 */
1640struct i40e_aqc_an_advt_reg {
1641 __le32 local_an_reg0;
1642 __le16 local_an_reg1;
1643 u8 reserved[10];
1644};
1645
1646I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1647
1648/* Set Loopback mode (0x0618) */
1649struct i40e_aqc_set_lb_mode {
1650 __le16 lb_mode;
1651#define I40E_LEGACY_LOOPBACK_NVM_VER 0x6000
1652#define I40E_AQ_LB_MAC_LOCAL 0x01
1653#define I40E_AQ_LB_PHY_LOCAL 0x05
1654#define I40E_AQ_LB_PHY_REMOTE 0x06
1655#define I40E_AQ_LB_MAC_LOCAL_LEGACY 0x04
1656 u8 reserved[14];
1657};
1658
1659I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1660
1661/* Set PHY Debug command (0x0622) */
1662struct i40e_aqc_set_phy_debug {
1663 u8 command_flags;
1664/* Disable link manageability on a single port */
1665#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1666/* Disable link manageability on all ports */
1667#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1668 u8 reserved[15];
1669};
1670
1671I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1672
1673enum i40e_aq_phy_reg_type {
1674 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1675 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1676 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1677};
1678
1679/* Run PHY Activity (0x0626) */
1680struct i40e_aqc_run_phy_activity {
1681 __le16 activity_id;
1682 u8 flags;
1683 u8 reserved1;
1684 __le32 control;
1685 __le32 data;
1686 u8 reserved2[4];
1687};
1688
1689I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1690
1691/* Set PHY Register command (0x0628) */
1692/* Get PHY Register command (0x0629) */
1693struct i40e_aqc_phy_register_access {
1694 u8 phy_interface;
1695#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
1696#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
1697 u8 dev_address;
1698 u8 cmd_flags;
1699#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1700#define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1701#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
1702#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1703 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1704 u8 reserved1;
1705 __le32 reg_address;
1706 __le32 reg_value;
1707 u8 reserved2[4];
1708};
1709
1710I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1711
1712/* NVM Read command (indirect 0x0701)
1713 * NVM Erase commands (direct 0x0702)
1714 * NVM Update commands (indirect 0x0703)
1715 */
1716struct i40e_aqc_nvm_update {
1717 u8 command_flags;
1718#define I40E_AQ_NVM_LAST_CMD 0x01
1719#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1720#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1721#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
1722#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1723#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1724 u8 module_pointer;
1725 __le16 length;
1726 __le32 offset;
1727 __le32 addr_high;
1728 __le32 addr_low;
1729};
1730
1731I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1732
1733/* NVM Config Read (indirect 0x0704) */
1734struct i40e_aqc_nvm_config_read {
1735 __le16 cmd_flags;
1736 __le16 element_count;
1737 __le16 element_id; /* Feature/field ID */
1738 __le16 element_id_msw; /* MSWord of field ID */
1739 __le32 address_high;
1740 __le32 address_low;
1741};
1742
1743I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1744
1745/* NVM Config Write (indirect 0x0705) */
1746struct i40e_aqc_nvm_config_write {
1747 __le16 cmd_flags;
1748 __le16 element_count;
1749 u8 reserved[4];
1750 __le32 address_high;
1751 __le32 address_low;
1752};
1753
1754I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1755
1756/* Used for 0x0704 as well as for 0x0705 commands */
1757struct i40e_aqc_nvm_config_data_feature {
1758 __le16 feature_id;
1759 __le16 feature_options;
1760 __le16 feature_selection;
1761};
1762
1763I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1764
1765struct i40e_aqc_nvm_config_data_immediate_field {
1766 __le32 field_id;
1767 __le32 field_value;
1768 __le16 field_options;
1769 __le16 reserved;
1770};
1771
1772I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1773
1774/* OEM Post Update (indirect 0x0720)
1775 * no command data struct used
1776 */
1777struct i40e_aqc_nvm_oem_post_update {
1778 u8 sel_data;
1779 u8 reserved[7];
1780};
1781
1782I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1783
1784struct i40e_aqc_nvm_oem_post_update_buffer {
1785 u8 str_len;
1786 u8 dev_addr;
1787 __le16 eeprom_addr;
1788 u8 data[36];
1789};
1790
1791I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1792
1793/* Thermal Sensor (indirect 0x0721)
1794 * read or set thermal sensor configs and values
1795 * takes a sensor and command specific data buffer, not detailed here
1796 */
1797struct i40e_aqc_thermal_sensor {
1798 u8 sensor_action;
1799 u8 reserved[7];
1800 __le32 addr_high;
1801 __le32 addr_low;
1802};
1803
1804I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1805
1806/* Send to PF command (indirect 0x0801) id is only used by PF
1807 * Send to VF command (indirect 0x0802) id is only used by PF
1808 * Send to Peer PF command (indirect 0x0803)
1809 */
1810struct i40e_aqc_pf_vf_message {
1811 __le32 id;
1812 u8 reserved[4];
1813 __le32 addr_high;
1814 __le32 addr_low;
1815};
1816
1817I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1818
1819/* Alternate structure */
1820
1821/* Direct write (direct 0x0900)
1822 * Direct read (direct 0x0902)
1823 */
1824struct i40e_aqc_alternate_write {
1825 __le32 address0;
1826 __le32 data0;
1827 __le32 address1;
1828 __le32 data1;
1829};
1830
1831I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1832
1833/* Indirect write (indirect 0x0901)
1834 * Indirect read (indirect 0x0903)
1835 */
1836
1837struct i40e_aqc_alternate_ind_write {
1838 __le32 address;
1839 __le32 length;
1840 __le32 addr_high;
1841 __le32 addr_low;
1842};
1843
1844I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1845
1846/* Done alternate write (direct 0x0904)
1847 * uses i40e_aq_desc
1848 */
1849struct i40e_aqc_alternate_write_done {
1850 __le16 cmd_flags;
1851 u8 reserved[14];
1852};
1853
1854I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1855
1856/* Set OEM mode (direct 0x0905) */
1857struct i40e_aqc_alternate_set_mode {
1858 __le32 mode;
1859 u8 reserved[12];
1860};
1861
1862I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1863
1864/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1865
1866/* async events 0x10xx */
1867
1868/* Lan Queue Overflow Event (direct, 0x1001) */
1869struct i40e_aqc_lan_overflow {
1870 __le32 prtdcb_rupto;
1871 __le32 otx_ctl;
1872 u8 reserved[8];
1873};
1874
1875I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1876
1877/* Get LLDP MIB (indirect 0x0A00) */
1878struct i40e_aqc_lldp_get_mib {
1879 u8 type;
1880 u8 reserved1;
1881#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1882#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1883#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1884#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1885#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1886#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1887/* TX pause flags use I40E_AQ_LINK_TX_* above */
1888 __le16 local_len;
1889 __le16 remote_len;
1890 u8 reserved2[2];
1891 __le32 addr_high;
1892 __le32 addr_low;
1893};
1894
1895I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1896
1897/* Configure LLDP MIB Change Event (direct 0x0A01)
1898 * also used for the event (with type in the command field)
1899 */
1900struct i40e_aqc_lldp_update_mib {
1901 u8 command;
1902#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1903 u8 reserved[7];
1904 __le32 addr_high;
1905 __le32 addr_low;
1906};
1907
1908I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1909
1910/* Add LLDP TLV (indirect 0x0A02)
1911 * Delete LLDP TLV (indirect 0x0A04)
1912 */
1913struct i40e_aqc_lldp_add_tlv {
1914 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1915 u8 reserved1[1];
1916 __le16 len;
1917 u8 reserved2[4];
1918 __le32 addr_high;
1919 __le32 addr_low;
1920};
1921
1922I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1923
1924/* Update LLDP TLV (indirect 0x0A03) */
1925struct i40e_aqc_lldp_update_tlv {
1926 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1927 u8 reserved;
1928 __le16 old_len;
1929 __le16 new_offset;
1930 __le16 new_len;
1931 __le32 addr_high;
1932 __le32 addr_low;
1933};
1934
1935I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1936
1937/* Stop LLDP (direct 0x0A05) */
1938struct i40e_aqc_lldp_stop {
1939 u8 command;
1940#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1941#define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
1942 u8 reserved[15];
1943};
1944
1945I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1946
1947/* Start LLDP (direct 0x0A06) */
1948struct i40e_aqc_lldp_start {
1949 u8 command;
1950#define I40E_AQ_LLDP_AGENT_START 0x1
1951#define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
1952 u8 reserved[15];
1953};
1954
1955I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1956
1957/* Set DCB (direct 0x0303) */
1958struct i40e_aqc_set_dcb_parameters {
1959 u8 command;
1960#define I40E_AQ_DCB_SET_AGENT 0x1
1961#define I40E_DCB_VALID 0x1
1962 u8 valid_flags;
1963 u8 reserved[14];
1964};
1965
1966I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
1967
1968/* Get CEE DCBX Oper Config (0x0A07)
1969 * uses the generic descriptor struct
1970 * returns below as indirect response
1971 */
1972
1973#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
1974#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
1975#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
1976#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
1977#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
1978#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
1979
1980#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
1981#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
1982#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
1983#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
1984#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
1985#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
1986#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
1987#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
1988#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
1989#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
1990#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
1991#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
1992
1993/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
1994 * word boundary layout issues, which the Linux compilers silently deal
1995 * with by adding padding, making the actual struct larger than designed.
1996 * However, the FW compiler for the NIC is less lenient and complains
1997 * about the struct. Hence, the struct defined here has an extra byte in
1998 * fields reserved3 and reserved4 to directly acknowledge that padding,
1999 * and the new length is used in the length check macro.
2000 */
2001struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2002 u8 reserved1;
2003 u8 oper_num_tc;
2004 u8 oper_prio_tc[4];
2005 u8 reserved2;
2006 u8 oper_tc_bw[8];
2007 u8 oper_pfc_en;
2008 u8 reserved3[2];
2009 __le16 oper_app_prio;
2010 u8 reserved4[2];
2011 __le16 tlv_status;
2012};
2013
2014I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2015
2016struct i40e_aqc_get_cee_dcb_cfg_resp {
2017 u8 oper_num_tc;
2018 u8 oper_prio_tc[4];
2019 u8 oper_tc_bw[8];
2020 u8 oper_pfc_en;
2021 __le16 oper_app_prio;
2022#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2023#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2024#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2025#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2026#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2027#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2028#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2029 __le32 tlv_status;
2030#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2031#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2032#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2033#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2034#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2035#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2036 u8 reserved[12];
2037};
2038
2039I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2040
2041/* Set Local LLDP MIB (indirect 0x0A08)
2042 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2043 */
2044struct i40e_aqc_lldp_set_local_mib {
2045#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2046#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2047 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2048#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2049#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2050#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2051 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2052#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2053 u8 type;
2054 u8 reserved0;
2055 __le16 length;
2056 u8 reserved1[4];
2057 __le32 address_high;
2058 __le32 address_low;
2059};
2060
2061I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2062
2063/* Stop/Start LLDP Agent (direct 0x0A09)
2064 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2065 */
2066struct i40e_aqc_lldp_stop_start_specific_agent {
2067 u8 command;
2068 u8 reserved[15];
2069};
2070
2071I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2072
2073/* Restore LLDP Agent factory settings (direct 0x0A0A) */
2074struct i40e_aqc_lldp_restore {
2075 u8 command;
2076#define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2077 u8 reserved[15];
2078};
2079
2080I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2081
2082/* Add Udp Tunnel command and completion (direct 0x0B00) */
2083struct i40e_aqc_add_udp_tunnel {
2084 __le16 udp_port;
2085 u8 reserved0[3];
2086 u8 protocol_type;
2087#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2088#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2089 u8 reserved1[10];
2090};
2091
2092I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2093
2094struct i40e_aqc_add_udp_tunnel_completion {
2095 __le16 udp_port;
2096 u8 filter_entry_index;
2097 u8 multiple_pfs;
2098 u8 total_filters;
2099 u8 reserved[11];
2100};
2101
2102I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2103
2104/* remove UDP Tunnel command (0x0B01) */
2105struct i40e_aqc_remove_udp_tunnel {
2106 u8 reserved[2];
2107 u8 index; /* 0 to 15 */
2108 u8 reserved2[13];
2109};
2110
2111I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2112
2113struct i40e_aqc_del_udp_tunnel_completion {
2114 __le16 udp_port;
2115 u8 index; /* 0 to 15 */
2116 u8 multiple_pfs;
2117 u8 total_filters_used;
2118 u8 reserved1[11];
2119};
2120
2121I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2122
2123struct i40e_aqc_get_set_rss_key {
2124#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2125#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2126#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2127 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2128 __le16 vsi_id;
2129 u8 reserved[6];
2130 __le32 addr_high;
2131 __le32 addr_low;
2132};
2133
2134I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2135
2136struct i40e_aqc_get_set_rss_key_data {
2137 u8 standard_rss_key[0x28];
2138 u8 extended_hash_key[0xc];
2139};
2140
2141I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2142
2143struct i40e_aqc_get_set_rss_lut {
2144#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2145#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2146#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2147 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2148 __le16 vsi_id;
2149#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2150#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2151
2152#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2153#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2154 __le16 flags;
2155 u8 reserved[4];
2156 __le32 addr_high;
2157 __le32 addr_low;
2158};
2159
2160I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2161
2162/* tunnel key structure 0x0B10 */
2163
2164struct i40e_aqc_tunnel_key_structure {
2165 u8 key1_off;
2166 u8 key2_off;
2167 u8 key1_len; /* 0 to 15 */
2168 u8 key2_len; /* 0 to 15 */
2169 u8 flags;
2170 u8 network_key_index;
2171 u8 reserved[10];
2172};
2173
2174I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2175
2176/* OEM mode commands (direct 0xFE0x) */
2177struct i40e_aqc_oem_param_change {
2178 __le32 param_type;
2179 __le32 param_value1;
2180 __le16 param_value2;
2181 u8 reserved[6];
2182};
2183
2184I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2185
2186struct i40e_aqc_oem_state_change {
2187 __le32 state;
2188 u8 reserved[12];
2189};
2190
2191I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2192
2193/* Initialize OCSD (0xFE02, direct) */
2194struct i40e_aqc_opc_oem_ocsd_initialize {
2195 u8 type_status;
2196 u8 reserved1[3];
2197 __le32 ocsd_memory_block_addr_high;
2198 __le32 ocsd_memory_block_addr_low;
2199 __le32 requested_update_interval;
2200};
2201
2202I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2203
2204/* Initialize OCBB (0xFE03, direct) */
2205struct i40e_aqc_opc_oem_ocbb_initialize {
2206 u8 type_status;
2207 u8 reserved1[3];
2208 __le32 ocbb_memory_block_addr_high;
2209 __le32 ocbb_memory_block_addr_low;
2210 u8 reserved2[4];
2211};
2212
2213I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2214
2215/* debug commands */
2216
2217/* get device id (0xFF00) uses the generic structure */
2218
2219/* set test more (0xFF01, internal) */
2220
2221struct i40e_acq_set_test_mode {
2222 u8 mode;
2223 u8 reserved[3];
2224 u8 command;
2225 u8 reserved2[3];
2226 __le32 address_high;
2227 __le32 address_low;
2228};
2229
2230I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2231
2232/* Debug Read Register command (0xFF03)
2233 * Debug Write Register command (0xFF04)
2234 */
2235struct i40e_aqc_debug_reg_read_write {
2236 __le32 reserved;
2237 __le32 address;
2238 __le32 value_high;
2239 __le32 value_low;
2240};
2241
2242I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2243
2244/* Scatter/gather Reg Read (indirect 0xFF05)
2245 * Scatter/gather Reg Write (indirect 0xFF06)
2246 */
2247
2248/* i40e_aq_desc is used for the command */
2249struct i40e_aqc_debug_reg_sg_element_data {
2250 __le32 address;
2251 __le32 value;
2252};
2253
2254/* Debug Modify register (direct 0xFF07) */
2255struct i40e_aqc_debug_modify_reg {
2256 __le32 address;
2257 __le32 value;
2258 __le32 clear_mask;
2259 __le32 set_mask;
2260};
2261
2262I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2263
2264/* dump internal data (0xFF08, indirect) */
2265struct i40e_aqc_debug_dump_internals {
2266 u8 cluster_id;
2267 u8 table_id;
2268 __le16 data_size;
2269 __le32 idx;
2270 __le32 address_high;
2271 __le32 address_low;
2272};
2273
2274I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2275
2276struct i40e_aqc_debug_modify_internals {
2277 u8 cluster_id;
2278 u8 cluster_specific_params[7];
2279 __le32 address_high;
2280 __le32 address_low;
2281};
2282
2283I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2284
2285#endif /* _I40E_ADMINQ_CMD_H_ */
2286

source code of linux/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h