1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
4	*
5	* Author Andreas Eversberg (jolly@eversberg.eu)
6	* ported to mqueue mechanism:
7	* Peter Sprenger (sprengermoving-bytes.de)
8	*
9	* inspired by existing hfc-pci driver:
10	* Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
11	* Copyright 2008 by Karsten Keil (kkeil@suse.de)
12	* Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
13	*
14	* Thanks to Cologne Chip AG for this great controller!
15	*/
16
17	/*
18	* module parameters:
19	* type:
20	* By default (0), the card is automatically detected.
21	* Or use the following combinations:
22	* Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23	* or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24	* or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
25	* Bit 8 = 0x00100 = uLaw (instead of aLaw)
26	* Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
27	* Bit 10 = spare
28	* Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwise auto)
29	* or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwise auto)
30	* Bit 13 = spare
31	* Bit 14 = 0x04000 = Use external ram (128K)
32	* Bit 15 = 0x08000 = Use external ram (512K)
33	* Bit 16 = 0x10000 = Use 64 timeslots instead of 32
34	* or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
35	* Bit 18 = spare
36	* Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
37	* (all other bits are reserved and shall be 0)
38	* example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
39	* bus (PCM master)
40	*
41	* port: (optional or required for all ports on all installed cards)
42	* HFC-4S/HFC-8S only bits:
43	* Bit 0 = 0x001 = Use master clock for this S/T interface
44	* (only once per chip).
45	* Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
46	* Don't use this unless you know what you are doing!
47	* Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
48	* example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
49	* received from port 1
50	*
51	* HFC-E1 only bits:
52	* Bit 0 = 0x0001 = interface: 0=copper, 1=optical
53	* Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
54	* Bit 2 = 0x0004 = Report LOS
55	* Bit 3 = 0x0008 = Report AIS
56	* Bit 4 = 0x0010 = Report SLIP
57	* Bit 5 = 0x0020 = Report RDI
58	* Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
59	* mode instead.
60	* Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
61	* or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
62	* Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
63	* (E1 only)
64	* Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
65	* for default.
66	* (all other bits are reserved and shall be 0)
67	*
68	* debug:
69	* NOTE: only one debug value must be given for all cards
70	* enable debugging (see hfc_multi.h for debug options)
71	*
72	* poll:
73	* NOTE: only one poll value must be given for all cards
74	* Give the number of samples for each fifo process.
75	* By default 128 is used. Decrease to reduce delay, increase to
76	* reduce cpu load. If unsure, don't mess with it!
77	* Valid is 8, 16, 32, 64, 128, 256.
78	*
79	* pcm:
80	* NOTE: only one pcm value must be given for every card.
81	* The PCM bus id tells the mISDNdsp module about the connected PCM bus.
82	* By default (0), the PCM bus id is 100 for the card that is PCM master.
83	* If multiple cards are PCM master (because they are not interconnected),
84	* each card with PCM master will have increasing PCM id.
85	* All PCM buses with the same ID are expected to be connected and have
86	* common time slots slots.
87	* Only one chip of the PCM bus must be master, the others slave.
88	* -1 means no support of PCM bus not even.
89	* Omit this value, if all cards are interconnected or none is connected.
90	* If unsure, don't give this parameter.
91	*
92	* dmask and bmask:
93	* NOTE: One dmask value must be given for every HFC-E1 card.
94	* If omitted, the E1 card has D-channel on time slot 16, which is default.
95	* dmask is a 32 bit mask. The bit must be set for an alternate time slot.
96	* If multiple bits are set, multiple virtual card fragments are created.
97	* For each bit set, a bmask value must be given. Each bit on the bmask
98	* value stands for a B-channel. The bmask may not overlap with dmask or
99	* with other bmask values for that card.
100	* Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
101	* This will create one fragment with D-channel on slot 1 with
102	* B-channels on slots 2..15, and a second fragment with D-channel
103	* on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
104	* If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
105	* not function.
106	* Example: dmask=0x00000001 bmask=0xfffffffe
107	* This will create a port with all 31 usable timeslots as
108	* B-channels.
109	* If no bits are set on bmask, no B-channel is created for that fragment.
110	* Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
111	* This will create 31 ports with one D-channel only.
112	* If you don't know how to use it, you don't need it!
113	*
114	* iomode:
115	* NOTE: only one mode value must be given for every card.
116	* -> See hfc_multi.h for HFC_IO_MODE_* values
117	* By default, the IO mode is pci memory IO (MEMIO).
118	* Some cards require specific IO mode, so it cannot be changed.
119	* It may be useful to set IO mode to register io (REGIO) to solve
120	* PCI bridge problems.
121	* If unsure, don't give this parameter.
122	*
123	* clockdelay_nt:
124	* NOTE: only one clockdelay_nt value must be given once for all cards.
125	* Give the value of the clock control register (A_ST_CLK_DLY)
126	* of the S/T interfaces in NT mode.
127	* This register is needed for the TBR3 certification, so don't change it.
128	*
129	* clockdelay_te:
130	* NOTE: only one clockdelay_te value must be given once
131	* Give the value of the clock control register (A_ST_CLK_DLY)
132	* of the S/T interfaces in TE mode.
133	* This register is needed for the TBR3 certification, so don't change it.
134	*
135	* clock:
136	* NOTE: only one clock value must be given once
137	* Selects interface with clock source for mISDN and applications.
138	* Set to card number starting with 1. Set to -1 to disable.
139	* By default, the first card is used as clock source.
140	*
141	* hwid:
142	* NOTE: only one hwid value must be given once
143	* Enable special embedded devices with XHFC controllers.
144	*/
145
146	/*
147	* debug register access (never use this, it will flood your system log)
148	* #define HFC_REGISTER_DEBUG
149	*/
150
151	#define HFC_MULTI_VERSION "2.03"
152
153	#include <linux/interrupt.h>
154	#include <linux/module.h>
155	#include <linux/slab.h>
156	#include <linux/pci.h>
157	#include <linux/delay.h>
158	#include <linux/mISDNhw.h>
159	#include <linux/mISDNdsp.h>
160
161	/*
162	#define IRQCOUNT_DEBUG
163	#define IRQ_DEBUG
164	*/
165
166	#include "hfc_multi.h"
167	#ifdef ECHOPREP
168	#include "gaintab.h"
169	#endif
170
171	#define MAX_CARDS 8
172	#define MAX_PORTS (8 * MAX_CARDS)
173	#define MAX_FRAGS (32 * MAX_CARDS)
174
175	static LIST_HEAD(HFClist);
176	static DEFINE_SPINLOCK(HFClock); /* global hfc list lock */
177
178	static void ph_state_change(struct dchannel *);
179
180	static struct hfc_multi *syncmaster;
181	static int plxsd_master; /* if we have a master card (yet) */
182	static DEFINE_SPINLOCK(plx_lock); /* may not acquire other lock inside */
183
184	#define TYP_E1 1
185	#define TYP_4S 4
186	#define TYP_8S 8
187
188	static int poll_timer = 6; /* default = 128 samples = 16ms */
189	/* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
190	static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
191	#define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
192	#define CLKDEL_NT 0x6c /* CLKDEL in NT mode
193	(0x60 MUST be included!) */
194
195	#define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
196	#define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
197	#define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
198
199	/*
200	* module stuff
201	*/
202
203	static uint type[MAX_CARDS];
204	static int pcm[MAX_CARDS];
205	static uint dmask[MAX_CARDS];
206	static uint bmask[MAX_FRAGS];
207	static uint iomode[MAX_CARDS];
208	static uint port[MAX_PORTS];
209	static uint debug;
210	static uint poll;
211	static int clock;
212	static uint timer;
213	static uint clockdelay_te = CLKDEL_TE;
214	static uint clockdelay_nt = CLKDEL_NT;
215	#define HWID_NONE 0
216	#define HWID_MINIP4 1
217	#define HWID_MINIP8 2
218	#define HWID_MINIP16 3
219	static uint hwid = HWID_NONE;
220
221	static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
222
223	MODULE_AUTHOR("Andreas Eversberg");
224	MODULE_DESCRIPTION("mISDN driver for hfc-4s/hfc-8s/hfc-e1 based cards");
225	MODULE_LICENSE("GPL");
226	MODULE_VERSION(HFC_MULTI_VERSION);
227	module_param(debug, uint, S_IRUGO | S_IWUSR);
228	module_param(poll, uint, S_IRUGO | S_IWUSR);
229	module_param(clock, int, S_IRUGO | S_IWUSR);
230	module_param(timer, uint, S_IRUGO | S_IWUSR);
231	module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
232	module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
233	module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
234	module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
235	module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
236	module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
237	module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
238	module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
239	module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
240
241	#ifdef HFC_REGISTER_DEBUG
242	#define HFC_outb(hc, reg, val) \
243	(hc->HFC_outb(hc, reg, val, __func__, __LINE__))
244	#define HFC_outb_nodebug(hc, reg, val) \
245	(hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
246	#define HFC_inb(hc, reg) \
247	(hc->HFC_inb(hc, reg, __func__, __LINE__))
248	#define HFC_inb_nodebug(hc, reg) \
249	(hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
250	#define HFC_inw(hc, reg) \
251	(hc->HFC_inw(hc, reg, __func__, __LINE__))
252	#define HFC_inw_nodebug(hc, reg) \
253	(hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
254	#define HFC_wait(hc) \
255	(hc->HFC_wait(hc, __func__, __LINE__))
256	#define HFC_wait_nodebug(hc) \
257	(hc->HFC_wait_nodebug(hc, __func__, __LINE__))
258	#else
259	#define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
260	#define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
261	#define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
262	#define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
263	#define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
264	#define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
265	#define HFC_wait(hc) (hc->HFC_wait(hc))
266	#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
267	#endif
268
269	#ifdef CONFIG_MISDN_HFCMULTI_8xx
270	#include "hfc_multi_8xx.h"
271	#endif
272
273	/* HFC_IO_MODE_PCIMEM */
274	static void
275	#ifdef HFC_REGISTER_DEBUG
276	HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
277	const char *function, int line)
278	#else
279	HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
280	#endif
281	{
282	writeb(val, addr: hc->pci_membase + reg);
283	}
284	static u_char
285	#ifdef HFC_REGISTER_DEBUG
286	HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
287	#else
288	HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
289	#endif
290	{
291	return readb(addr: hc->pci_membase + reg);
292	}
293	static u_short
294	#ifdef HFC_REGISTER_DEBUG
295	HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
296	#else
297	HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
298	#endif
299	{
300	return readw(addr: hc->pci_membase + reg);
301	}
302	static void
303	#ifdef HFC_REGISTER_DEBUG
304	HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
305	#else
306	HFC_wait_pcimem(struct hfc_multi *hc)
307	#endif
308	{
309	while (readb(addr: hc->pci_membase + R_STATUS) & V_BUSY)
310	cpu_relax();
311	}
312
313	/* HFC_IO_MODE_REGIO */
314	static void
315	#ifdef HFC_REGISTER_DEBUG
316	HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
317	const char *function, int line)
318	#else
319	HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
320	#endif
321	{
322	outb(value: reg, port: hc->pci_iobase + 4);
323	outb(value: val, port: hc->pci_iobase);
324	}
325	static u_char
326	#ifdef HFC_REGISTER_DEBUG
327	HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
328	#else
329	HFC_inb_regio(struct hfc_multi *hc, u_char reg)
330	#endif
331	{
332	outb(value: reg, port: hc->pci_iobase + 4);
333	return inb(port: hc->pci_iobase);
334	}
335	static u_short
336	#ifdef HFC_REGISTER_DEBUG
337	HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
338	#else
339	HFC_inw_regio(struct hfc_multi *hc, u_char reg)
340	#endif
341	{
342	outb(value: reg, port: hc->pci_iobase + 4);
343	return inw(port: hc->pci_iobase);
344	}
345	static void
346	#ifdef HFC_REGISTER_DEBUG
347	HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
348	#else
349	HFC_wait_regio(struct hfc_multi *hc)
350	#endif
351	{
352	outb(R_STATUS, port: hc->pci_iobase + 4);
353	while (inb(port: hc->pci_iobase) & V_BUSY)
354	cpu_relax();
355	}
356
357	#ifdef HFC_REGISTER_DEBUG
358	static void
359	HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
360	const char *function, int line)
361	{
362	char regname[256] = "", bits[9] = "xxxxxxxx";
363	int i;
364
365	i = -1;
366	while (hfc_register_names[++i].name) {
367	if (hfc_register_names[i].reg == reg)
368	strcat(regname, hfc_register_names[i].name);
369	}
370	if (regname[0] == '\0')
371	strcpy(regname, "register");
372
373	bits[7] = '0' + (!!(val & 1));
374	bits[6] = '0' + (!!(val & 2));
375	bits[5] = '0' + (!!(val & 4));
376	bits[4] = '0' + (!!(val & 8));
377	bits[3] = '0' + (!!(val & 16));
378	bits[2] = '0' + (!!(val & 32));
379	bits[1] = '0' + (!!(val & 64));
380	bits[0] = '0' + (!!(val & 128));
381	printk(KERN_DEBUG
382	"HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
383	hc->id, reg, regname, val, bits, function, line);
384	HFC_outb_nodebug(hc, reg, val);
385	}
386	static u_char
387	HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
388	{
389	char regname[256] = "", bits[9] = "xxxxxxxx";
390	u_char val = HFC_inb_nodebug(hc, reg);
391	int i;
392
393	i = 0;
394	while (hfc_register_names[i++].name)
395	;
396	while (hfc_register_names[++i].name) {
397	if (hfc_register_names[i].reg == reg)
398	strcat(regname, hfc_register_names[i].name);
399	}
400	if (regname[0] == '\0')
401	strcpy(regname, "register");
402
403	bits[7] = '0' + (!!(val & 1));
404	bits[6] = '0' + (!!(val & 2));
405	bits[5] = '0' + (!!(val & 4));
406	bits[4] = '0' + (!!(val & 8));
407	bits[3] = '0' + (!!(val & 16));
408	bits[2] = '0' + (!!(val & 32));
409	bits[1] = '0' + (!!(val & 64));
410	bits[0] = '0' + (!!(val & 128));
411	printk(KERN_DEBUG
412	"HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
413	hc->id, reg, regname, val, bits, function, line);
414	return val;
415	}
416	static u_short
417	HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
418	{
419	char regname[256] = "";
420	u_short val = HFC_inw_nodebug(hc, reg);
421	int i;
422
423	i = 0;
424	while (hfc_register_names[i++].name)
425	;
426	while (hfc_register_names[++i].name) {
427	if (hfc_register_names[i].reg == reg)
428	strcat(regname, hfc_register_names[i].name);
429	}
430	if (regname[0] == '\0')
431	strcpy(regname, "register");
432
433	printk(KERN_DEBUG
434	"HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
435	hc->id, reg, regname, val, function, line);
436	return val;
437	}
438	static void
439	HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
440	{
441	printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
442	hc->id, function, line);
443	HFC_wait_nodebug(hc);
444	}
445	#endif
446
447	/* write fifo data (REGIO) */
448	static void
449	write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
450	{
451	outb(A_FIFO_DATA0, port: (hc->pci_iobase) + 4);
452	while (len >> 2) {
453	outl(cpu_to_le32(*(u32 *)data), port: hc->pci_iobase);
454	data += 4;
455	len -= 4;
456	}
457	while (len >> 1) {
458	outw(cpu_to_le16(*(u16 *)data), port: hc->pci_iobase);
459	data += 2;
460	len -= 2;
461	}
462	while (len) {
463	outb(value: *data, port: hc->pci_iobase);
464	data++;
465	len--;
466	}
467	}
468	/* write fifo data (PCIMEM) */
469	static void
470	write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
471	{
472	while (len >> 2) {
473	writel(cpu_to_le32(*(u32 *)data),
474	addr: hc->pci_membase + A_FIFO_DATA0);
475	data += 4;
476	len -= 4;
477	}
478	while (len >> 1) {
479	writew(cpu_to_le16(*(u16 *)data),
480	addr: hc->pci_membase + A_FIFO_DATA0);
481	data += 2;
482	len -= 2;
483	}
484	while (len) {
485	writeb(val: *data, addr: hc->pci_membase + A_FIFO_DATA0);
486	data++;
487	len--;
488	}
489	}
490
491	/* read fifo data (REGIO) */
492	static void
493	read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
494	{
495	outb(A_FIFO_DATA0, port: (hc->pci_iobase) + 4);
496	while (len >> 2) {
497	*(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
498	data += 4;
499	len -= 4;
500	}
501	while (len >> 1) {
502	*(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
503	data += 2;
504	len -= 2;
505	}
506	while (len) {
507	*data = inb(port: hc->pci_iobase);
508	data++;
509	len--;
510	}
511	}
512
513	/* read fifo data (PCIMEM) */
514	static void
515	read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
516	{
517	while (len >> 2) {
518	*(u32 *)data =
519	le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
520	data += 4;
521	len -= 4;
522	}
523	while (len >> 1) {
524	*(u16 *)data =
525	le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
526	data += 2;
527	len -= 2;
528	}
529	while (len) {
530	*data = readb(addr: hc->pci_membase + A_FIFO_DATA0);
531	data++;
532	len--;
533	}
534	}
535
536	static void
537	enable_hwirq(struct hfc_multi *hc)
538	{
539	hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
540	HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
541	}
542
543	static void
544	disable_hwirq(struct hfc_multi *hc)
545	{
546	hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
547	HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
548	}
549
550	#define NUM_EC 2
551	#define MAX_TDM_CHAN 32
552
553
554	static inline void
555	enablepcibridge(struct hfc_multi *c)
556	{
557	HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
558	}
559
560	static inline void
561	disablepcibridge(struct hfc_multi *c)
562	{
563	HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
564	}
565
566	static inline unsigned char
567	readpcibridge(struct hfc_multi *hc, unsigned char address)
568	{
569	unsigned short cipv;
570	unsigned char data;
571
572	if (!hc->pci_iobase)
573	return 0;
574
575	/* slow down a PCI read access by 1 PCI clock cycle */
576	HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
577
578	if (address == 0)
579	cipv = 0x4000;
580	else
581	cipv = 0x5800;
582
583	/* select local bridge port address by writing to CIP port */
584	/* data = HFC_inb(c, cipv); * was _io before */
585	outw(value: cipv, port: hc->pci_iobase + 4);
586	data = inb(port: hc->pci_iobase);
587
588	/* restore R_CTRL for normal PCI read cycle speed */
589	HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
590
591	return data;
592	}
593
594	static inline void
595	writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
596	{
597	unsigned short cipv;
598	unsigned int datav;
599
600	if (!hc->pci_iobase)
601	return;
602
603	if (address == 0)
604	cipv = 0x4000;
605	else
606	cipv = 0x5800;
607
608	/* select local bridge port address by writing to CIP port */
609	outw(value: cipv, port: hc->pci_iobase + 4);
610	/* define a 32 bit dword with 4 identical bytes for write sequence */
611	datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
612	((__u32) data << 24);
613
614	/*
615	* write this 32 bit dword to the bridge data port
616	* this will initiate a write sequence of up to 4 writes to the same
617	* address on the local bus interface the number of write accesses
618	* is undefined but >=1 and depends on the next PCI transaction
619	* during write sequence on the local bus
620	*/
621	outl(value: datav, port: hc->pci_iobase);
622	}
623
624	static inline void
625	cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
626	{
627	/* Do data pin read low byte */
628	HFC_outb(hc, R_GPIO_OUT1, reg);
629	}
630
631	static inline void
632	cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
633	{
634	cpld_set_reg(hc, reg);
635
636	enablepcibridge(c: hc);
637	writepcibridge(hc, address: 1, data: val);
638	disablepcibridge(c: hc);
639
640	return;
641	}
642
643	static inline void
644	vpm_write_address(struct hfc_multi *hc, unsigned short addr)
645	{
646	cpld_write_reg(hc, reg: 0, val: 0xff & addr);
647	cpld_write_reg(hc, reg: 1, val: 0x01 & (addr >> 8));
648	}
649
650	static inline unsigned char
651	vpm_in(struct hfc_multi *c, int which, unsigned short addr)
652	{
653	unsigned char res;
654
655	vpm_write_address(hc: c, addr);
656
657	if (!which)
658	cpld_set_reg(hc: c, reg: 2);
659	else
660	cpld_set_reg(hc: c, reg: 3);
661
662	enablepcibridge(c);
663	res = readpcibridge(hc: c, address: 1);
664	disablepcibridge(c);
665
666	cpld_set_reg(hc: c, reg: 0);
667
668	return res;
669	}
670
671	static inline void
672	vpm_out(struct hfc_multi *c, int which, unsigned short addr,
673	unsigned char data)
674	{
675	vpm_write_address(hc: c, addr);
676
677	enablepcibridge(c);
678
679	if (!which)
680	cpld_set_reg(hc: c, reg: 2);
681	else
682	cpld_set_reg(hc: c, reg: 3);
683
684	writepcibridge(hc: c, address: 1, data);
685
686	cpld_set_reg(hc: c, reg: 0);
687
688	disablepcibridge(c);
689
690	{
691	unsigned char regin;
692	regin = vpm_in(c, which, addr);
693	if (regin != data)
694	printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
695	"0x%x\n", data, addr, regin);
696	}
697
698	}
699
700
701	static void
702	vpm_init(struct hfc_multi *wc)
703	{
704	unsigned char reg;
705	unsigned int mask;
706	unsigned int i, x, y;
707	unsigned int ver;
708
709	for (x = 0; x < NUM_EC; x++) {
710	/* Setup GPIO's */
711	if (!x) {
712	ver = vpm_in(c: wc, which: x, addr: 0x1a0);
713	printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
714	}
715
716	for (y = 0; y < 4; y++) {
717	vpm_out(c: wc, which: x, addr: 0x1a8 + y, data: 0x00); /* GPIO out */
718	vpm_out(c: wc, which: x, addr: 0x1ac + y, data: 0x00); /* GPIO dir */
719	vpm_out(c: wc, which: x, addr: 0x1b0 + y, data: 0x00); /* GPIO sel */
720	}
721
722	/* Setup TDM path - sets fsync and tdm_clk as inputs */
723	reg = vpm_in(c: wc, which: x, addr: 0x1a3); /* misc_con */
724	vpm_out(c: wc, which: x, addr: 0x1a3, data: reg & ~2);
725
726	/* Setup Echo length (256 taps) */
727	vpm_out(c: wc, which: x, addr: 0x022, data: 1);
728	vpm_out(c: wc, which: x, addr: 0x023, data: 0xff);
729
730	/* Setup timeslots */
731	vpm_out(c: wc, which: x, addr: 0x02f, data: 0x00);
732	mask = 0x02020202 << (x * 4);
733
734	/* Setup the tdm channel masks for all chips */
735	for (i = 0; i < 4; i++)
736	vpm_out(c: wc, which: x, addr: 0x33 - i, data: (mask >> (i << 3)) & 0xff);
737
738	/* Setup convergence rate */
739	printk(KERN_DEBUG "VPM: A-law mode\n");
740	reg = 0x00 | 0x10 | 0x01;
741	vpm_out(c: wc, which: x, addr: 0x20, data: reg);
742	printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
743	/*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
744
745	vpm_out(c: wc, which: x, addr: 0x24, data: 0x02);
746	reg = vpm_in(c: wc, which: x, addr: 0x24);
747	printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
748
749	/* Initialize echo cans */
750	for (i = 0; i < MAX_TDM_CHAN; i++) {
751	if (mask & (0x00000001 << i))
752	vpm_out(c: wc, which: x, addr: i, data: 0x00);
753	}
754
755	/*
756	* ARM arch at least disallows a udelay of
757	* more than 2ms... it gives a fake "__bad_udelay"
758	* reference at link-time.
759	* long delays in kernel code are pretty sucky anyway
760	* for now work around it using 5 x 2ms instead of 1 x 10ms
761	*/
762
763	udelay(usec: 2000);
764	udelay(usec: 2000);
765	udelay(usec: 2000);
766	udelay(usec: 2000);
767	udelay(usec: 2000);
768
769	/* Put in bypass mode */
770	for (i = 0; i < MAX_TDM_CHAN; i++) {
771	if (mask & (0x00000001 << i))
772	vpm_out(c: wc, which: x, addr: i, data: 0x01);
773	}
774
775	/* Enable bypass */
776	for (i = 0; i < MAX_TDM_CHAN; i++) {
777	if (mask & (0x00000001 << i))
778	vpm_out(c: wc, which: x, addr: 0x78 + i, data: 0x01);
779	}
780
781	}
782	}
783
784	#ifdef UNUSED
785	static void
786	vpm_check(struct hfc_multi *hctmp)
787	{
788	unsigned char gpi2;
789
790	gpi2 = HFC_inb(hctmp, R_GPI_IN2);
791
792	if ((gpi2 & 0x3) != 0x3)
793	printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
794	}
795	#endif /* UNUSED */
796
797
798	/*
799	* Interface to enable/disable the HW Echocan
800	*
801	* these functions are called within a spin_lock_irqsave on
802	* the channel instance lock, so we are not disturbed by irqs
803	*
804	* we can later easily change the interface to make other
805	* things configurable, for now we configure the taps
806	*
807	*/
808
809	static void
810	vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
811	{
812	unsigned int timeslot;
813	unsigned int unit;
814	struct bchannel *bch = hc->chan[ch].bch;
815	#ifdef TXADJ
816	int txadj = -4;
817	struct sk_buff *skb;
818	#endif
819	if (hc->chan[ch].protocol != ISDN_P_B_RAW)
820	return;
821
822	if (!bch)
823	return;
824
825	#ifdef TXADJ
826	skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
827	sizeof(int), &txadj, GFP_ATOMIC);
828	if (skb)
829	recv_Bchannel_skb(bch, skb);
830	#endif
831
832	timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
833	unit = ch % 4;
834
835	printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
836	taps, timeslot);
837
838	vpm_out(c: hc, which: unit, addr: timeslot, data: 0x7e);
839	}
840
841	static void
842	vpm_echocan_off(struct hfc_multi *hc, int ch)
843	{
844	unsigned int timeslot;
845	unsigned int unit;
846	struct bchannel *bch = hc->chan[ch].bch;
847	#ifdef TXADJ
848	int txadj = 0;
849	struct sk_buff *skb;
850	#endif
851
852	if (hc->chan[ch].protocol != ISDN_P_B_RAW)
853	return;
854
855	if (!bch)
856	return;
857
858	#ifdef TXADJ
859	skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
860	sizeof(int), &txadj, GFP_ATOMIC);
861	if (skb)
862	recv_Bchannel_skb(bch, skb);
863	#endif
864
865	timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
866	unit = ch % 4;
867
868	printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
869	timeslot);
870	/* FILLME */
871	vpm_out(c: hc, which: unit, addr: timeslot, data: 0x01);
872	}
873
874
875	/*
876	* Speech Design resync feature
877	* NOTE: This is called sometimes outside interrupt handler.
878	* We must lock irqsave, so no other interrupt (other card) will occur!
879	* Also multiple interrupts may nest, so must lock each access (lists, card)!
880	*/
881	static inline void
882	hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
883	{
884	struct hfc_multi *hc, *next, *pcmmaster = NULL;
885	void __iomem *plx_acc_32;
886	u_int pv;
887	u_long flags;
888
889	spin_lock_irqsave(&HFClock, flags);
890	spin_lock(lock: &plx_lock); /* must be locked inside other locks */
891
892	if (debug & DEBUG_HFCMULTI_PLXSD)
893	printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
894	__func__, syncmaster);
895
896	/* select new master */
897	if (newmaster) {
898	if (debug & DEBUG_HFCMULTI_PLXSD)
899	printk(KERN_DEBUG "using provided controller\n");
900	} else {
901	list_for_each_entry_safe(hc, next, &HFClist, list) {
902	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
903	if (hc->syncronized) {
904	newmaster = hc;
905	break;
906	}
907	}
908	}
909	}
910
911	/* Disable sync of all cards */
912	list_for_each_entry_safe(hc, next, &HFClist, list) {
913	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
914	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
915	pv = readl(addr: plx_acc_32);
916	pv &= ~PLX_SYNC_O_EN;
917	writel(val: pv, addr: plx_acc_32);
918	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
919	pcmmaster = hc;
920	if (hc->ctype == HFC_TYPE_E1) {
921	if (debug & DEBUG_HFCMULTI_PLXSD)
922	printk(KERN_DEBUG
923	"Schedule SYNC_I\n");
924	hc->e1_resync |= 1; /* get SYNC_I */
925	}
926	}
927	}
928	}
929
930	if (newmaster) {
931	hc = newmaster;
932	if (debug & DEBUG_HFCMULTI_PLXSD)
933	printk(KERN_DEBUG "id=%d (0x%p) = synchronized with "
934	"interface.\n", hc->id, hc);
935	/* Enable new sync master */
936	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
937	pv = readl(addr: plx_acc_32);
938	pv |= PLX_SYNC_O_EN;
939	writel(val: pv, addr: plx_acc_32);
940	/* switch to jatt PLL, if not disabled by RX_SYNC */
941	if (hc->ctype == HFC_TYPE_E1
942	&& !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
943	if (debug & DEBUG_HFCMULTI_PLXSD)
944	printk(KERN_DEBUG "Schedule jatt PLL\n");
945	hc->e1_resync |= 2; /* switch to jatt */
946	}
947	} else {
948	if (pcmmaster) {
949	hc = pcmmaster;
950	if (debug & DEBUG_HFCMULTI_PLXSD)
951	printk(KERN_DEBUG
952	"id=%d (0x%p) = PCM master synchronized "
953	"with QUARTZ\n", hc->id, hc);
954	if (hc->ctype == HFC_TYPE_E1) {
955	/* Use the crystal clock for the PCM
956	master card */
957	if (debug & DEBUG_HFCMULTI_PLXSD)
958	printk(KERN_DEBUG
959	"Schedule QUARTZ for HFC-E1\n");
960	hc->e1_resync |= 4; /* switch quartz */
961	} else {
962	if (debug & DEBUG_HFCMULTI_PLXSD)
963	printk(KERN_DEBUG
964	"QUARTZ is automatically "
965	"enabled by HFC-%dS\n", hc->ctype);
966	}
967	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
968	pv = readl(addr: plx_acc_32);
969	pv |= PLX_SYNC_O_EN;
970	writel(val: pv, addr: plx_acc_32);
971	} else
972	if (!rm)
973	printk(KERN_ERR "%s no pcm master, this MUST "
974	"not happen!\n", __func__);
975	}
976	syncmaster = newmaster;
977
978	spin_unlock(lock: &plx_lock);
979	spin_unlock_irqrestore(lock: &HFClock, flags);
980	}
981
982	/* This must be called AND hc must be locked irqsave!!! */
983	static inline void
984	plxsd_checksync(struct hfc_multi *hc, int rm)
985	{
986	if (hc->syncronized) {
987	if (syncmaster == NULL) {
988	if (debug & DEBUG_HFCMULTI_PLXSD)
989	printk(KERN_DEBUG "%s: GOT sync on card %d"
990	" (id=%d)\n", __func__, hc->id + 1,
991	hc->id);
992	hfcmulti_resync(locked: hc, newmaster: hc, rm);
993	}
994	} else {
995	if (syncmaster == hc) {
996	if (debug & DEBUG_HFCMULTI_PLXSD)
997	printk(KERN_DEBUG "%s: LOST sync on card %d"
998	" (id=%d)\n", __func__, hc->id + 1,
999	hc->id);
1000	hfcmulti_resync(locked: hc, NULL, rm);
1001	}
1002	}
1003	}
1004
1005
1006	/*
1007	* free hardware resources used by driver
1008	*/
1009	static void
1010	release_io_hfcmulti(struct hfc_multi *hc)
1011	{
1012	void __iomem *plx_acc_32;
1013	u_int pv;
1014	u_long plx_flags;
1015
1016	if (debug & DEBUG_HFCMULTI_INIT)
1017	printk(KERN_DEBUG "%s: entered\n", __func__);
1018
1019	/* soft reset also masks all interrupts */
1020	hc->hw.r_cirm |= V_SRES;
1021	HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1022	udelay(usec: 1000);
1023	hc->hw.r_cirm &= ~V_SRES;
1024	HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1025	udelay(usec: 1000); /* instead of 'wait' that may cause locking */
1026
1027	/* release Speech Design card, if PLX was initialized */
1028	if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1029	if (debug & DEBUG_HFCMULTI_PLXSD)
1030	printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1031	__func__, hc->id + 1);
1032	spin_lock_irqsave(&plx_lock, plx_flags);
1033	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1034	writel(PLX_GPIOC_INIT, addr: plx_acc_32);
1035	pv = readl(addr: plx_acc_32);
1036	/* Termination off */
1037	pv &= ~PLX_TERM_ON;
1038	/* Disconnect the PCM */
1039	pv |= PLX_SLAVE_EN_N;
1040	pv &= ~PLX_MASTER_EN;
1041	pv &= ~PLX_SYNC_O_EN;
1042	/* Put the DSP in Reset */
1043	pv &= ~PLX_DSP_RES_N;
1044	writel(val: pv, addr: plx_acc_32);
1045	if (debug & DEBUG_HFCMULTI_INIT)
1046	printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1047	__func__, pv);
1048	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1049	}
1050
1051	/* disable memory mapped ports / io ports */
1052	test_and_clear_bit(HFC_CHIP_PLXSD, addr: &hc->chip); /* prevent resync */
1053	if (hc->pci_dev)
1054	pci_write_config_word(dev: hc->pci_dev, PCI_COMMAND, val: 0);
1055	if (hc->pci_membase)
1056	iounmap(addr: hc->pci_membase);
1057	if (hc->plx_membase)
1058	iounmap(addr: hc->plx_membase);
1059	if (hc->pci_iobase)
1060	release_region(hc->pci_iobase, 8);
1061	if (hc->xhfc_membase)
1062	iounmap(addr: (void *)hc->xhfc_membase);
1063
1064	if (hc->pci_dev) {
1065	pci_disable_device(dev: hc->pci_dev);
1066	pci_set_drvdata(pdev: hc->pci_dev, NULL);
1067	}
1068	if (debug & DEBUG_HFCMULTI_INIT)
1069	printk(KERN_DEBUG "%s: done\n", __func__);
1070	}
1071
1072	/*
1073	* function called to reset the HFC chip. A complete software reset of chip
1074	* and fifos is done. All configuration of the chip is done.
1075	*/
1076
1077	static int
1078	init_chip(struct hfc_multi *hc)
1079	{
1080	u_long flags, val, val2 = 0, rev;
1081	int i, err = 0;
1082	u_char r_conf_en, rval;
1083	void __iomem *plx_acc_32;
1084	u_int pv;
1085	u_long plx_flags, hfc_flags;
1086	int plx_count;
1087	struct hfc_multi *pos, *next, *plx_last_hc;
1088
1089	spin_lock_irqsave(&hc->lock, flags);
1090	/* reset all registers */
1091	memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1092
1093	/* revision check */
1094	if (debug & DEBUG_HFCMULTI_INIT)
1095	printk(KERN_DEBUG "%s: entered\n", __func__);
1096	val = HFC_inb(hc, R_CHIP_ID);
1097	if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1098	(val >> 1) != 0x31) {
1099	printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1100	err = -EIO;
1101	goto out;
1102	}
1103	rev = HFC_inb(hc, R_CHIP_RV);
1104	printk(KERN_INFO
1105	"HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1106	val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1107	" (old FIFO handling)" : "");
1108	if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1109	test_and_set_bit(HFC_CHIP_REVISION0, addr: &hc->chip);
1110	printk(KERN_WARNING
1111	"HFC_multi: NOTE: Your chip is revision 0, "
1112	"ask Cologne Chip for update. Newer chips "
1113	"have a better FIFO handling. Old chips "
1114	"still work but may have slightly lower "
1115	"HDLC transmit performance.\n");
1116	}
1117	if (rev > 1) {
1118	printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1119	"consider chip revision = %ld. The chip / "
1120	"bridge may not work.\n", rev);
1121	}
1122
1123	/* set s-ram size */
1124	hc->Flen = 0x10;
1125	hc->Zmin = 0x80;
1126	hc->Zlen = 384;
1127	hc->DTMFbase = 0x1000;
1128	if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1129	if (debug & DEBUG_HFCMULTI_INIT)
1130	printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1131	__func__);
1132	hc->hw.r_ctrl |= V_EXT_RAM;
1133	hc->hw.r_ram_sz = 1;
1134	hc->Flen = 0x20;
1135	hc->Zmin = 0xc0;
1136	hc->Zlen = 1856;
1137	hc->DTMFbase = 0x2000;
1138	}
1139	if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1140	if (debug & DEBUG_HFCMULTI_INIT)
1141	printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1142	__func__);
1143	hc->hw.r_ctrl |= V_EXT_RAM;
1144	hc->hw.r_ram_sz = 2;
1145	hc->Flen = 0x20;
1146	hc->Zmin = 0xc0;
1147	hc->Zlen = 8000;
1148	hc->DTMFbase = 0x2000;
1149	}
1150	if (hc->ctype == HFC_TYPE_XHFC) {
1151	hc->Flen = 0x8;
1152	hc->Zmin = 0x0;
1153	hc->Zlen = 64;
1154	hc->DTMFbase = 0x0;
1155	}
1156	hc->max_trans = poll << 1;
1157	if (hc->max_trans > hc->Zlen)
1158	hc->max_trans = hc->Zlen;
1159
1160	/* Speech Design PLX bridge */
1161	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1162	if (debug & DEBUG_HFCMULTI_PLXSD)
1163	printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1164	__func__, hc->id + 1);
1165	spin_lock_irqsave(&plx_lock, plx_flags);
1166	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1167	writel(PLX_GPIOC_INIT, addr: plx_acc_32);
1168	pv = readl(addr: plx_acc_32);
1169	/* The first and the last cards are terminating the PCM bus */
1170	pv |= PLX_TERM_ON; /* hc is currently the last */
1171	/* Disconnect the PCM */
1172	pv |= PLX_SLAVE_EN_N;
1173	pv &= ~PLX_MASTER_EN;
1174	pv &= ~PLX_SYNC_O_EN;
1175	/* Put the DSP in Reset */
1176	pv &= ~PLX_DSP_RES_N;
1177	writel(val: pv, addr: plx_acc_32);
1178	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1179	if (debug & DEBUG_HFCMULTI_INIT)
1180	printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1181	__func__, pv);
1182	/*
1183	* If we are the 3rd PLXSD card or higher, we must turn
1184	* termination of last PLXSD card off.
1185	*/
1186	spin_lock_irqsave(&HFClock, hfc_flags);
1187	plx_count = 0;
1188	plx_last_hc = NULL;
1189	list_for_each_entry_safe(pos, next, &HFClist, list) {
1190	if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1191	plx_count++;
1192	if (pos != hc)
1193	plx_last_hc = pos;
1194	}
1195	}
1196	if (plx_count >= 3) {
1197	if (debug & DEBUG_HFCMULTI_PLXSD)
1198	printk(KERN_DEBUG "%s: card %d is between, so "
1199	"we disable termination\n",
1200	__func__, plx_last_hc->id + 1);
1201	spin_lock_irqsave(&plx_lock, plx_flags);
1202	plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1203	pv = readl(addr: plx_acc_32);
1204	pv &= ~PLX_TERM_ON;
1205	writel(val: pv, addr: plx_acc_32);
1206	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1207	if (debug & DEBUG_HFCMULTI_INIT)
1208	printk(KERN_DEBUG
1209	"%s: term off: PLX_GPIO=%x\n",
1210	__func__, pv);
1211	}
1212	spin_unlock_irqrestore(lock: &HFClock, flags: hfc_flags);
1213	hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1214	}
1215
1216	if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1217	hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1218
1219	/* we only want the real Z2 read-pointer for revision > 0 */
1220	if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1221	hc->hw.r_ram_sz |= V_FZ_MD;
1222
1223	/* select pcm mode */
1224	if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1225	if (debug & DEBUG_HFCMULTI_INIT)
1226	printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1227	__func__);
1228	} else
1229	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1230	if (debug & DEBUG_HFCMULTI_INIT)
1231	printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1232	__func__);
1233	hc->hw.r_pcm_md0 |= V_PCM_MD;
1234	} else {
1235	if (debug & DEBUG_HFCMULTI_INIT)
1236	printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1237	__func__);
1238	}
1239
1240	/* soft reset */
1241	HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1242	if (hc->ctype == HFC_TYPE_XHFC)
1243	HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1244	0x11 /* 16 Bytes TX/RX */);
1245	else
1246	HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1247	HFC_outb(hc, R_FIFO_MD, 0);
1248	if (hc->ctype == HFC_TYPE_XHFC)
1249	hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1250	else
1251	hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1252	| V_RLD_EPR;
1253	HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1254	udelay(usec: 100);
1255	hc->hw.r_cirm = 0;
1256	HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1257	udelay(usec: 100);
1258	if (hc->ctype != HFC_TYPE_XHFC)
1259	HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1260
1261	/* Speech Design PLX bridge pcm and sync mode */
1262	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1263	spin_lock_irqsave(&plx_lock, plx_flags);
1264	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1265	pv = readl(addr: plx_acc_32);
1266	/* Connect PCM */
1267	if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1268	pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1269	pv |= PLX_SYNC_O_EN;
1270	if (debug & DEBUG_HFCMULTI_INIT)
1271	printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1272	__func__, pv);
1273	} else {
1274	pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1275	pv &= ~PLX_SYNC_O_EN;
1276	if (debug & DEBUG_HFCMULTI_INIT)
1277	printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1278	__func__, pv);
1279	}
1280	writel(val: pv, addr: plx_acc_32);
1281	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1282	}
1283
1284	/* PCM setup */
1285	HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1286	if (hc->slots == 32)
1287	HFC_outb(hc, R_PCM_MD1, 0x00);
1288	if (hc->slots == 64)
1289	HFC_outb(hc, R_PCM_MD1, 0x10);
1290	if (hc->slots == 128)
1291	HFC_outb(hc, R_PCM_MD1, 0x20);
1292	HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1293	if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1294	HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1295	else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1296	HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1297	else
1298	HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1299	HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1300	for (i = 0; i < 256; i++) {
1301	HFC_outb_nodebug(hc, R_SLOT, i);
1302	HFC_outb_nodebug(hc, A_SL_CFG, 0);
1303	if (hc->ctype != HFC_TYPE_XHFC)
1304	HFC_outb_nodebug(hc, A_CONF, 0);
1305	hc->slot_owner[i] = -1;
1306	}
1307
1308	/* set clock speed */
1309	if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1310	if (debug & DEBUG_HFCMULTI_INIT)
1311	printk(KERN_DEBUG
1312	"%s: setting double clock\n", __func__);
1313	HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1314	}
1315
1316	if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1317	HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1318
1319	/* B410P GPIO */
1320	if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1321	printk(KERN_NOTICE "Setting GPIOs\n");
1322	HFC_outb(hc, R_GPIO_SEL, 0x30);
1323	HFC_outb(hc, R_GPIO_EN1, 0x3);
1324	udelay(usec: 1000);
1325	printk(KERN_NOTICE "calling vpm_init\n");
1326	vpm_init(wc: hc);
1327	}
1328
1329	/* check if R_F0_CNT counts (8 kHz frame count) */
1330	val = HFC_inb(hc, R_F0_CNTL);
1331	val += HFC_inb(hc, R_F0_CNTH) << 8;
1332	if (debug & DEBUG_HFCMULTI_INIT)
1333	printk(KERN_DEBUG
1334	"HFC_multi F0_CNT %ld after reset\n", val);
1335	spin_unlock_irqrestore(lock: &hc->lock, flags);
1336	set_current_state(TASK_UNINTERRUPTIBLE);
1337	schedule_timeout(timeout: (HZ / 100) ? : 1); /* Timeout minimum 10ms */
1338	spin_lock_irqsave(&hc->lock, flags);
1339	val2 = HFC_inb(hc, R_F0_CNTL);
1340	val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1341	if (debug & DEBUG_HFCMULTI_INIT)
1342	printk(KERN_DEBUG
1343	"HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1344	val2);
1345	if (val2 >= val + 8) { /* 1 ms */
1346	/* it counts, so we keep the pcm mode */
1347	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1348	printk(KERN_INFO "controller is PCM bus MASTER\n");
1349	else
1350	if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1351	printk(KERN_INFO "controller is PCM bus SLAVE\n");
1352	else {
1353	test_and_set_bit(HFC_CHIP_PCM_SLAVE, addr: &hc->chip);
1354	printk(KERN_INFO "controller is PCM bus SLAVE "
1355	"(auto detected)\n");
1356	}
1357	} else {
1358	/* does not count */
1359	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1360	controller_fail:
1361	printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1362	"pulse. Seems that controller fails.\n");
1363	err = -EIO;
1364	goto out;
1365	}
1366	if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1367	printk(KERN_INFO "controller is PCM bus SLAVE "
1368	"(ignoring missing PCM clock)\n");
1369	} else {
1370	/* only one pcm master */
1371	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1372	&& plxsd_master) {
1373	printk(KERN_ERR "HFC_multi ERROR, no clock "
1374	"on another Speech Design card found. "
1375	"Please be sure to connect PCM cable.\n");
1376	err = -EIO;
1377	goto out;
1378	}
1379	/* retry with master clock */
1380	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1381	spin_lock_irqsave(&plx_lock, plx_flags);
1382	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1383	pv = readl(addr: plx_acc_32);
1384	pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1385	pv |= PLX_SYNC_O_EN;
1386	writel(val: pv, addr: plx_acc_32);
1387	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1388	if (debug & DEBUG_HFCMULTI_INIT)
1389	printk(KERN_DEBUG "%s: master: "
1390	"PLX_GPIO=%x\n", __func__, pv);
1391	}
1392	hc->hw.r_pcm_md0 |= V_PCM_MD;
1393	HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1394	spin_unlock_irqrestore(lock: &hc->lock, flags);
1395	set_current_state(TASK_UNINTERRUPTIBLE);
1396	schedule_timeout(timeout: (HZ / 100) ?: 1); /* Timeout min. 10ms */
1397	spin_lock_irqsave(&hc->lock, flags);
1398	val2 = HFC_inb(hc, R_F0_CNTL);
1399	val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1400	if (debug & DEBUG_HFCMULTI_INIT)
1401	printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1402	"10 ms (2nd try)\n", val2);
1403	if (val2 >= val + 8) { /* 1 ms */
1404	test_and_set_bit(HFC_CHIP_PCM_MASTER,
1405	addr: &hc->chip);
1406	printk(KERN_INFO "controller is PCM bus MASTER "
1407	"(auto detected)\n");
1408	} else
1409	goto controller_fail;
1410	}
1411	}
1412
1413	/* Release the DSP Reset */
1414	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1415	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1416	plxsd_master = 1;
1417	spin_lock_irqsave(&plx_lock, plx_flags);
1418	plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1419	pv = readl(addr: plx_acc_32);
1420	pv |= PLX_DSP_RES_N;
1421	writel(val: pv, addr: plx_acc_32);
1422	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
1423	if (debug & DEBUG_HFCMULTI_INIT)
1424	printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1425	__func__, pv);
1426	}
1427
1428	/* pcm id */
1429	if (hc->pcm)
1430	printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1431	hc->pcm);
1432	else {
1433	if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1434	|| test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1435	PCM_cnt++; /* SD has proprietary bridging */
1436	}
1437	hc->pcm = PCM_cnt;
1438	printk(KERN_INFO "controller has PCM BUS ID %d "
1439	"(auto selected)\n", hc->pcm);
1440	}
1441
1442	/* set up timer */
1443	HFC_outb(hc, R_TI_WD, poll_timer);
1444	hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1445
1446	/* set E1 state machine IRQ */
1447	if (hc->ctype == HFC_TYPE_E1)
1448	hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1449
1450	/* set DTMF detection */
1451	if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1452	if (debug & DEBUG_HFCMULTI_INIT)
1453	printk(KERN_DEBUG "%s: enabling DTMF detection "
1454	"for all B-channel\n", __func__);
1455	hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1456	if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1457	hc->hw.r_dtmf |= V_ULAW_SEL;
1458	HFC_outb(hc, R_DTMF_N, 102 - 1);
1459	hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1460	}
1461
1462	/* conference engine */
1463	if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1464	r_conf_en = V_CONF_EN | V_ULAW;
1465	else
1466	r_conf_en = V_CONF_EN;
1467	if (hc->ctype != HFC_TYPE_XHFC)
1468	HFC_outb(hc, R_CONF_EN, r_conf_en);
1469
1470	/* setting leds */
1471	switch (hc->leds) {
1472	case 1: /* HFC-E1 OEM */
1473	if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1474	HFC_outb(hc, R_GPIO_SEL, 0x32);
1475	else
1476	HFC_outb(hc, R_GPIO_SEL, 0x30);
1477
1478	HFC_outb(hc, R_GPIO_EN1, 0x0f);
1479	HFC_outb(hc, R_GPIO_OUT1, 0x00);
1480
1481	HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1482	break;
1483
1484	case 2: /* HFC-4S OEM */
1485	case 3:
1486	HFC_outb(hc, R_GPIO_SEL, 0xf0);
1487	HFC_outb(hc, R_GPIO_EN1, 0xff);
1488	HFC_outb(hc, R_GPIO_OUT1, 0x00);
1489	break;
1490	}
1491
1492	if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1493	hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1494	HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1495	}
1496
1497	/* set master clock */
1498	if (hc->masterclk >= 0) {
1499	if (debug & DEBUG_HFCMULTI_INIT)
1500	printk(KERN_DEBUG "%s: setting ST master clock "
1501	"to port %d (0..%d)\n",
1502	__func__, hc->masterclk, hc->ports - 1);
1503	hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1504	HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1505	}
1506
1507
1508
1509	/* setting misc irq */
1510	HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1511	if (debug & DEBUG_HFCMULTI_INIT)
1512	printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1513	hc->hw.r_irqmsk_misc);
1514
1515	/* RAM access test */
1516	HFC_outb(hc, R_RAM_ADDR0, 0);
1517	HFC_outb(hc, R_RAM_ADDR1, 0);
1518	HFC_outb(hc, R_RAM_ADDR2, 0);
1519	for (i = 0; i < 256; i++) {
1520	HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1521	HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1522	}
1523	for (i = 0; i < 256; i++) {
1524	HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1525	HFC_inb_nodebug(hc, R_RAM_DATA);
1526	rval = HFC_inb_nodebug(hc, R_INT_DATA);
1527	if (rval != ((i * 3) & 0xff)) {
1528	printk(KERN_DEBUG
1529	"addr:%x val:%x should:%x\n", i, rval,
1530	(i * 3) & 0xff);
1531	err++;
1532	}
1533	}
1534	if (err) {
1535	printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1536	err = -EIO;
1537	goto out;
1538	}
1539
1540	if (debug & DEBUG_HFCMULTI_INIT)
1541	printk(KERN_DEBUG "%s: done\n", __func__);
1542	out:
1543	spin_unlock_irqrestore(lock: &hc->lock, flags);
1544	return err;
1545	}
1546
1547
1548	/*
1549	* control the watchdog
1550	*/
1551	static void
1552	hfcmulti_watchdog(struct hfc_multi *hc)
1553	{
1554	hc->wdcount++;
1555
1556	if (hc->wdcount > 10) {
1557	hc->wdcount = 0;
1558	hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1559	V_GPIO_OUT3 : V_GPIO_OUT2;
1560
1561	/* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1562	HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1563	HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1564	}
1565	}
1566
1567
1568
1569	/*
1570	* output leds
1571	*/
1572	static void
1573	hfcmulti_leds(struct hfc_multi *hc)
1574	{
1575	unsigned long lled;
1576	unsigned long leddw;
1577	int i, state, active, leds;
1578	struct dchannel *dch;
1579	int led[4];
1580
1581	switch (hc->leds) {
1582	case 1: /* HFC-E1 OEM */
1583	/* 2 red steady: LOS
1584	* 1 red steady: L1 not active
1585	* 2 green steady: L1 active
1586	* 1st green flashing: activity on TX
1587	* 2nd green flashing: activity on RX
1588	*/
1589	led[0] = 0;
1590	led[1] = 0;
1591	led[2] = 0;
1592	led[3] = 0;
1593	dch = hc->chan[hc->dnum[0]].dch;
1594	if (dch) {
1595	if (hc->chan[hc->dnum[0]].los)
1596	led[1] = 1;
1597	if (hc->e1_state != 1) {
1598	led[0] = 1;
1599	hc->flash[2] = 0;
1600	hc->flash[3] = 0;
1601	} else {
1602	led[2] = 1;
1603	led[3] = 1;
1604	if (!hc->flash[2] && hc->activity_tx)
1605	hc->flash[2] = poll;
1606	if (!hc->flash[3] && hc->activity_rx)
1607	hc->flash[3] = poll;
1608	if (hc->flash[2] && hc->flash[2] < 1024)
1609	led[2] = 0;
1610	if (hc->flash[3] && hc->flash[3] < 1024)
1611	led[3] = 0;
1612	if (hc->flash[2] >= 2048)
1613	hc->flash[2] = 0;
1614	if (hc->flash[3] >= 2048)
1615	hc->flash[3] = 0;
1616	if (hc->flash[2])
1617	hc->flash[2] += poll;
1618	if (hc->flash[3])
1619	hc->flash[3] += poll;
1620	}
1621	}
1622	leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1623	/* leds are inverted */
1624	if (leds != (int)hc->ledstate) {
1625	HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1626	hc->ledstate = leds;
1627	}
1628	break;
1629
1630	case 2: /* HFC-4S OEM */
1631	/* red steady: PH_DEACTIVATE
1632	* green steady: PH_ACTIVATE
1633	* green flashing: activity on TX
1634	*/
1635	for (i = 0; i < 4; i++) {
1636	state = 0;
1637	active = -1;
1638	dch = hc->chan[(i << 2) | 2].dch;
1639	if (dch) {
1640	state = dch->state;
1641	if (dch->dev.D.protocol == ISDN_P_NT_S0)
1642	active = 3;
1643	else
1644	active = 7;
1645	}
1646	if (state) {
1647	if (state == active) {
1648	led[i] = 1; /* led green */
1649	hc->activity_tx |= hc->activity_rx;
1650	if (!hc->flash[i] &&
1651	(hc->activity_tx & (1 << i)))
1652	hc->flash[i] = poll;
1653	if (hc->flash[i] && hc->flash[i] < 1024)
1654	led[i] = 0; /* led off */
1655	if (hc->flash[i] >= 2048)
1656	hc->flash[i] = 0;
1657	if (hc->flash[i])
1658	hc->flash[i] += poll;
1659	} else {
1660	led[i] = 2; /* led red */
1661	hc->flash[i] = 0;
1662	}
1663	} else
1664	led[i] = 0; /* led off */
1665	}
1666	if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1667	leds = 0;
1668	for (i = 0; i < 4; i++) {
1669	if (led[i] == 1) {
1670	/*green*/
1671	leds |= (0x2 << (i * 2));
1672	} else if (led[i] == 2) {
1673	/*red*/
1674	leds |= (0x1 << (i * 2));
1675	}
1676	}
1677	if (leds != (int)hc->ledstate) {
1678	vpm_out(c: hc, which: 0, addr: 0x1a8 + 3, data: leds);
1679	hc->ledstate = leds;
1680	}
1681	} else {
1682	leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1683	((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1684	((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1685	((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1686	if (leds != (int)hc->ledstate) {
1687	HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1688	HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1689	hc->ledstate = leds;
1690	}
1691	}
1692	break;
1693
1694	case 3: /* HFC 1S/2S Beronet */
1695	/* red steady: PH_DEACTIVATE
1696	* green steady: PH_ACTIVATE
1697	* green flashing: activity on TX
1698	*/
1699	for (i = 0; i < 2; i++) {
1700	state = 0;
1701	active = -1;
1702	dch = hc->chan[(i << 2) | 2].dch;
1703	if (dch) {
1704	state = dch->state;
1705	if (dch->dev.D.protocol == ISDN_P_NT_S0)
1706	active = 3;
1707	else
1708	active = 7;
1709	}
1710	if (state) {
1711	if (state == active) {
1712	led[i] = 1; /* led green */
1713	hc->activity_tx |= hc->activity_rx;
1714	if (!hc->flash[i] &&
1715	(hc->activity_tx & (1 << i)))
1716	hc->flash[i] = poll;
1717	if (hc->flash[i] < 1024)
1718	led[i] = 0; /* led off */
1719	if (hc->flash[i] >= 2048)
1720	hc->flash[i] = 0;
1721	if (hc->flash[i])
1722	hc->flash[i] += poll;
1723	} else {
1724	led[i] = 2; /* led red */
1725	hc->flash[i] = 0;
1726	}
1727	} else
1728	led[i] = 0; /* led off */
1729	}
1730	leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1731	| ((led[1]&1) << 3);
1732	if (leds != (int)hc->ledstate) {
1733	HFC_outb_nodebug(hc, R_GPIO_EN1,
1734	((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1735	HFC_outb_nodebug(hc, R_GPIO_OUT1,
1736	((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1737	hc->ledstate = leds;
1738	}
1739	break;
1740	case 8: /* HFC 8S+ Beronet */
1741	/* off: PH_DEACTIVATE
1742	* steady: PH_ACTIVATE
1743	* flashing: activity on TX
1744	*/
1745	lled = 0xff; /* leds off */
1746	for (i = 0; i < 8; i++) {
1747	state = 0;
1748	active = -1;
1749	dch = hc->chan[(i << 2) | 2].dch;
1750	if (dch) {
1751	state = dch->state;
1752	if (dch->dev.D.protocol == ISDN_P_NT_S0)
1753	active = 3;
1754	else
1755	active = 7;
1756	}
1757	if (state) {
1758	if (state == active) {
1759	lled &= ~(1 << i); /* led on */
1760	hc->activity_tx |= hc->activity_rx;
1761	if (!hc->flash[i] &&
1762	(hc->activity_tx & (1 << i)))
1763	hc->flash[i] = poll;
1764	if (hc->flash[i] < 1024)
1765	lled |= 1 << i; /* led off */
1766	if (hc->flash[i] >= 2048)
1767	hc->flash[i] = 0;
1768	if (hc->flash[i])
1769	hc->flash[i] += poll;
1770	} else
1771	hc->flash[i] = 0;
1772	}
1773	}
1774	leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1775	if (leddw != hc->ledstate) {
1776	/* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1777	HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1778	/* was _io before */
1779	HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1780	outw(value: 0x4000, port: hc->pci_iobase + 4);
1781	outl(value: leddw, port: hc->pci_iobase);
1782	HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1783	hc->ledstate = leddw;
1784	}
1785	break;
1786	}
1787	hc->activity_tx = 0;
1788	hc->activity_rx = 0;
1789	}
1790	/*
1791	* read dtmf coefficients
1792	*/
1793
1794	static void
1795	hfcmulti_dtmf(struct hfc_multi *hc)
1796	{
1797	s32 *coeff;
1798	u_int mantissa;
1799	int co, ch;
1800	struct bchannel *bch = NULL;
1801	u8 exponent;
1802	int dtmf = 0;
1803	int addr;
1804	u16 w_float;
1805	struct sk_buff *skb;
1806	struct mISDNhead *hh;
1807
1808	if (debug & DEBUG_HFCMULTI_DTMF)
1809	printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1810	for (ch = 0; ch <= 31; ch++) {
1811	/* only process enabled B-channels */
1812	bch = hc->chan[ch].bch;
1813	if (!bch)
1814	continue;
1815	if (!hc->created[hc->chan[ch].port])
1816	continue;
1817	if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1818	continue;
1819	if (debug & DEBUG_HFCMULTI_DTMF)
1820	printk(KERN_DEBUG "%s: dtmf channel %d:",
1821	__func__, ch);
1822	coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1823	dtmf = 1;
1824	for (co = 0; co < 8; co++) {
1825	/* read W(n-1) coefficient */
1826	addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1827	HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1828	HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1829	HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1830	| V_ADDR_INC);
1831	w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1832	w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1833	if (debug & DEBUG_HFCMULTI_DTMF)
1834	printk(" %04x", w_float);
1835
1836	/* decode float (see chip doc) */
1837	mantissa = w_float & 0x0fff;
1838	if (w_float & 0x8000)
1839	mantissa |= 0xfffff000;
1840	exponent = (w_float >> 12) & 0x7;
1841	if (exponent) {
1842	mantissa ^= 0x1000;
1843	mantissa <<= (exponent - 1);
1844	}
1845
1846	/* store coefficient */
1847	coeff[co << 1] = mantissa;
1848
1849	/* read W(n) coefficient */
1850	w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1851	w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1852	if (debug & DEBUG_HFCMULTI_DTMF)
1853	printk(" %04x", w_float);
1854
1855	/* decode float (see chip doc) */
1856	mantissa = w_float & 0x0fff;
1857	if (w_float & 0x8000)
1858	mantissa |= 0xfffff000;
1859	exponent = (w_float >> 12) & 0x7;
1860	if (exponent) {
1861	mantissa ^= 0x1000;
1862	mantissa <<= (exponent - 1);
1863	}
1864
1865	/* store coefficient */
1866	coeff[(co << 1) | 1] = mantissa;
1867	}
1868	if (debug & DEBUG_HFCMULTI_DTMF)
1869	printk(" DTMF ready %08x %08x %08x %08x "
1870	"%08x %08x %08x %08x\n",
1871	coeff[0], coeff[1], coeff[2], coeff[3],
1872	coeff[4], coeff[5], coeff[6], coeff[7]);
1873	hc->chan[ch].coeff_count++;
1874	if (hc->chan[ch].coeff_count == 8) {
1875	hc->chan[ch].coeff_count = 0;
1876	skb = mI_alloc_skb(len: 512, GFP_ATOMIC);
1877	if (!skb) {
1878	printk(KERN_DEBUG "%s: No memory for skb\n",
1879	__func__);
1880	continue;
1881	}
1882	hh = mISDN_HEAD_P(skb);
1883	hh->prim = PH_CONTROL_IND;
1884	hh->id = DTMF_HFC_COEF;
1885	skb_put_data(skb, data: hc->chan[ch].coeff, len: 512);
1886	recv_Bchannel_skb(bch, skb);
1887	}
1888	}
1889
1890	/* restart DTMF processing */
1891	hc->dtmf = dtmf;
1892	if (dtmf)
1893	HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1894	}
1895
1896
1897	/*
1898	* fill fifo as much as possible
1899	*/
1900
1901	static void
1902	hfcmulti_tx(struct hfc_multi *hc, int ch)
1903	{
1904	int i, ii, temp, tmp_len, len = 0;
1905	int Zspace, z1, z2; /* must be int for calculation */
1906	int Fspace, f1, f2;
1907	u_char *d;
1908	int *txpending, slot_tx;
1909	struct bchannel *bch;
1910	struct dchannel *dch;
1911	struct sk_buff **sp = NULL;
1912	int *idxp;
1913
1914	bch = hc->chan[ch].bch;
1915	dch = hc->chan[ch].dch;
1916	if ((!dch) && (!bch))
1917	return;
1918
1919	txpending = &hc->chan[ch].txpending;
1920	slot_tx = hc->chan[ch].slot_tx;
1921	if (dch) {
1922	if (!test_bit(FLG_ACTIVE, &dch->Flags))
1923	return;
1924	sp = &dch->tx_skb;
1925	idxp = &dch->tx_idx;
1926	} else {
1927	if (!test_bit(FLG_ACTIVE, &bch->Flags))
1928	return;
1929	sp = &bch->tx_skb;
1930	idxp = &bch->tx_idx;
1931	}
1932	if (*sp)
1933	len = (*sp)->len;
1934
1935	if ((!len) && *txpending != 1)
1936	return; /* no data */
1937
1938	if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1939	(hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1940	(hc->chan[ch].slot_rx < 0) &&
1941	(hc->chan[ch].slot_tx < 0))
1942	HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1943	else
1944	HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1945	HFC_wait_nodebug(hc);
1946
1947	if (*txpending == 2) {
1948	/* reset fifo */
1949	HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1950	HFC_wait_nodebug(hc);
1951	HFC_outb(hc, A_SUBCH_CFG, 0);
1952	*txpending = 1;
1953	}
1954	next_frame:
1955	if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1956	f1 = HFC_inb_nodebug(hc, A_F1);
1957	f2 = HFC_inb_nodebug(hc, A_F2);
1958	while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1959	if (debug & DEBUG_HFCMULTI_FIFO)
1960	printk(KERN_DEBUG
1961	"%s(card %d): reread f2 because %d!=%d\n",
1962	__func__, hc->id + 1, temp, f2);
1963	f2 = temp; /* repeat until F2 is equal */
1964	}
1965	Fspace = f2 - f1 - 1;
1966	if (Fspace < 0)
1967	Fspace += hc->Flen;
1968	/*
1969	* Old FIFO handling doesn't give us the current Z2 read
1970	* pointer, so we cannot send the next frame before the fifo
1971	* is empty. It makes no difference except for a slightly
1972	* lower performance.
1973	*/
1974	if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1975	if (f1 != f2)
1976	Fspace = 0;
1977	else
1978	Fspace = 1;
1979	}
1980	/* one frame only for ST D-channels, to allow resending */
1981	if (hc->ctype != HFC_TYPE_E1 && dch) {
1982	if (f1 != f2)
1983	Fspace = 0;
1984	}
1985	/* F-counter full condition */
1986	if (Fspace == 0)
1987	return;
1988	}
1989	z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1990	z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1991	while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1992	if (debug & DEBUG_HFCMULTI_FIFO)
1993	printk(KERN_DEBUG "%s(card %d): reread z2 because "
1994	"%d!=%d\n", __func__, hc->id + 1, temp, z2);
1995	z2 = temp; /* repeat unti Z2 is equal */
1996	}
1997	hc->chan[ch].Zfill = z1 - z2;
1998	if (hc->chan[ch].Zfill < 0)
1999	hc->chan[ch].Zfill += hc->Zlen;
2000	Zspace = z2 - z1;
2001	if (Zspace <= 0)
2002	Zspace += hc->Zlen;
2003	Zspace -= 4; /* keep not too full, so pointers will not overrun */
2004	/* fill transparent data only to maximum transparent load (minus 4) */
2005	if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2006	Zspace = Zspace - hc->Zlen + hc->max_trans;
2007	if (Zspace <= 0) /* no space of 4 bytes */
2008	return;
2009
2010	/* if no data */
2011	if (!len) {
2012	if (z1 == z2) { /* empty */
2013	/* if done with FIFO audio data during PCM connection */
2014	if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2015	*txpending && slot_tx >= 0) {
2016	if (debug & DEBUG_HFCMULTI_MODE)
2017	printk(KERN_DEBUG
2018	"%s: reconnecting PCM due to no "
2019	"more FIFO data: channel %d "
2020	"slot_tx %d\n",
2021	__func__, ch, slot_tx);
2022	/* connect slot */
2023	if (hc->ctype == HFC_TYPE_XHFC)
2024	HFC_outb(hc, A_CON_HDLC, 0xc0
2025	| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2026	/* Enable FIFO, no interrupt */
2027	else
2028	HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2029	V_HDLC_TRP | V_IFF);
2030	HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2031	HFC_wait_nodebug(hc);
2032	if (hc->ctype == HFC_TYPE_XHFC)
2033	HFC_outb(hc, A_CON_HDLC, 0xc0
2034	| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2035	/* Enable FIFO, no interrupt */
2036	else
2037	HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2038	V_HDLC_TRP | V_IFF);
2039	HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2040	HFC_wait_nodebug(hc);
2041	}
2042	*txpending = 0;
2043	}
2044	return; /* no data */
2045	}
2046
2047	/* "fill fifo if empty" feature */
2048	if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2049	&& !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2050	if (debug & DEBUG_HFCMULTI_FILL)
2051	printk(KERN_DEBUG "%s: buffer empty, so we have "
2052	"underrun\n", __func__);
2053	/* fill buffer, to prevent future underrun */
2054	hc->write_fifo(hc, hc->silence_data, poll >> 1);
2055	Zspace -= (poll >> 1);
2056	}
2057
2058	/* if audio data and connected slot */
2059	if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2060	&& slot_tx >= 0) {
2061	if (debug & DEBUG_HFCMULTI_MODE)
2062	printk(KERN_DEBUG "%s: disconnecting PCM due to "
2063	"FIFO data: channel %d slot_tx %d\n",
2064	__func__, ch, slot_tx);
2065	/* disconnect slot */
2066	if (hc->ctype == HFC_TYPE_XHFC)
2067	HFC_outb(hc, A_CON_HDLC, 0x80
2068	| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2069	/* Enable FIFO, no interrupt */
2070	else
2071	HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2072	V_HDLC_TRP | V_IFF);
2073	HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2074	HFC_wait_nodebug(hc);
2075	if (hc->ctype == HFC_TYPE_XHFC)
2076	HFC_outb(hc, A_CON_HDLC, 0x80
2077	| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2078	/* Enable FIFO, no interrupt */
2079	else
2080	HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2081	V_HDLC_TRP | V_IFF);
2082	HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2083	HFC_wait_nodebug(hc);
2084	}
2085	*txpending = 1;
2086
2087	/* show activity */
2088	if (dch)
2089	hc->activity_tx |= 1 << hc->chan[ch].port;
2090
2091	/* fill fifo to what we have left */
2092	ii = len;
2093	if (dch || test_bit(FLG_HDLC, &bch->Flags))
2094	temp = 1;
2095	else
2096	temp = 0;
2097	i = *idxp;
2098	d = (*sp)->data + i;
2099	if (ii - i > Zspace)
2100	ii = Zspace + i;
2101	if (debug & DEBUG_HFCMULTI_FIFO)
2102	printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2103	"left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2104	__func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2105	temp ? "HDLC" : "TRANS");
2106
2107	/* Have to prep the audio data */
2108	hc->write_fifo(hc, d, ii - i);
2109	hc->chan[ch].Zfill += ii - i;
2110	*idxp = ii;
2111
2112	/* if not all data has been written */
2113	if (ii != len) {
2114	/* NOTE: fifo is started by the calling function */
2115	return;
2116	}
2117
2118	/* if all data has been written, terminate frame */
2119	if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2120	/* increment f-counter */
2121	HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2122	HFC_wait_nodebug(hc);
2123	}
2124
2125	tmp_len = (*sp)->len;
2126	dev_kfree_skb(*sp);
2127	/* check for next frame */
2128	if (bch && get_next_bframe(bch)) {
2129	len = tmp_len;
2130	goto next_frame;
2131	}
2132	if (dch && get_next_dframe(dch)) {
2133	len = tmp_len;
2134	goto next_frame;
2135	}
2136
2137	/*
2138	* now we have no more data, so in case of transparent,
2139	* we set the last byte in fifo to 'silence' in case we will get
2140	* no more data at all. this prevents sending an undefined value.
2141	*/
2142	if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2143	HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2144	}
2145
2146
2147	/* NOTE: only called if E1 card is in active state */
2148	static void
2149	hfcmulti_rx(struct hfc_multi *hc, int ch)
2150	{
2151	int temp;
2152	int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2153	int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2154	int again = 0;
2155	struct bchannel *bch;
2156	struct dchannel *dch = NULL;
2157	struct sk_buff *skb, **sp = NULL;
2158	int maxlen;
2159
2160	bch = hc->chan[ch].bch;
2161	if (bch) {
2162	if (!test_bit(FLG_ACTIVE, &bch->Flags))
2163	return;
2164	} else if (hc->chan[ch].dch) {
2165	dch = hc->chan[ch].dch;
2166	if (!test_bit(FLG_ACTIVE, &dch->Flags))
2167	return;
2168	} else {
2169	return;
2170	}
2171	next_frame:
2172	/* on first AND before getting next valid frame, R_FIFO must be written
2173	to. */
2174	if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2175	(hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2176	(hc->chan[ch].slot_rx < 0) &&
2177	(hc->chan[ch].slot_tx < 0))
2178	HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2179	else
2180	HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2181	HFC_wait_nodebug(hc);
2182
2183	/* ignore if rx is off BUT change fifo (above) to start pending TX */
2184	if (hc->chan[ch].rx_off) {
2185	if (bch)
2186	bch->dropcnt += poll; /* not exact but fair enough */
2187	return;
2188	}
2189
2190	if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2191	f1 = HFC_inb_nodebug(hc, A_F1);
2192	while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2193	if (debug & DEBUG_HFCMULTI_FIFO)
2194	printk(KERN_DEBUG
2195	"%s(card %d): reread f1 because %d!=%d\n",
2196	__func__, hc->id + 1, temp, f1);
2197	f1 = temp; /* repeat until F1 is equal */
2198	}
2199	f2 = HFC_inb_nodebug(hc, A_F2);
2200	}
2201	z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2202	while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2203	if (debug & DEBUG_HFCMULTI_FIFO)
2204	printk(KERN_DEBUG "%s(card %d): reread z2 because "
2205	"%d!=%d\n", __func__, hc->id + 1, temp, z2);
2206	z1 = temp; /* repeat until Z1 is equal */
2207	}
2208	z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2209	Zsize = z1 - z2;
2210	if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2211	/* complete hdlc frame */
2212	Zsize++;
2213	if (Zsize < 0)
2214	Zsize += hc->Zlen;
2215	/* if buffer is empty */
2216	if (Zsize <= 0)
2217	return;
2218
2219	if (bch) {
2220	maxlen = bchannel_get_rxbuf(bch, Zsize);
2221	if (maxlen < 0) {
2222	pr_warn("card%d.B%d: No bufferspace for %d bytes\n",
2223	hc->id + 1, bch->nr, Zsize);
2224	return;
2225	}
2226	sp = &bch->rx_skb;
2227	maxlen = bch->maxlen;
2228	} else { /* Dchannel */
2229	sp = &dch->rx_skb;
2230	maxlen = dch->maxlen + 3;
2231	if (*sp == NULL) {
2232	*sp = mI_alloc_skb(len: maxlen, GFP_ATOMIC);
2233	if (*sp == NULL) {
2234	pr_warn("card%d: No mem for dch rx_skb\n",
2235	hc->id + 1);
2236	return;
2237	}
2238	}
2239	}
2240	/* show activity */
2241	if (dch)
2242	hc->activity_rx |= 1 << hc->chan[ch].port;
2243
2244	/* empty fifo with what we have */
2245	if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2246	if (debug & DEBUG_HFCMULTI_FIFO)
2247	printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2248	"bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2249	"got=%d (again %d)\n", __func__, hc->id + 1, ch,
2250	Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2251	f1, f2, Zsize + (*sp)->len, again);
2252	/* HDLC */
2253	if ((Zsize + (*sp)->len) > maxlen) {
2254	if (debug & DEBUG_HFCMULTI_FIFO)
2255	printk(KERN_DEBUG
2256	"%s(card %d): hdlc-frame too large.\n",
2257	__func__, hc->id + 1);
2258	skb_trim(skb: *sp, len: 0);
2259	HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2260	HFC_wait_nodebug(hc);
2261	return;
2262	}
2263
2264	hc->read_fifo(hc, skb_put(skb: *sp, len: Zsize), Zsize);
2265
2266	if (f1 != f2) {
2267	/* increment Z2,F2-counter */
2268	HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2269	HFC_wait_nodebug(hc);
2270	/* check size */
2271	if ((*sp)->len < 4) {
2272	if (debug & DEBUG_HFCMULTI_FIFO)
2273	printk(KERN_DEBUG
2274	"%s(card %d): Frame below minimum "
2275	"size\n", __func__, hc->id + 1);
2276	skb_trim(skb: *sp, len: 0);
2277	goto next_frame;
2278	}
2279	/* there is at least one complete frame, check crc */
2280	if ((*sp)->data[(*sp)->len - 1]) {
2281	if (debug & DEBUG_HFCMULTI_CRC)
2282	printk(KERN_DEBUG
2283	"%s: CRC-error\n", __func__);
2284	skb_trim(skb: *sp, len: 0);
2285	goto next_frame;
2286	}
2287	skb_trim(skb: *sp, len: (*sp)->len - 3);
2288	if ((*sp)->len < MISDN_COPY_SIZE) {
2289	skb = *sp;
2290	*sp = mI_alloc_skb(len: skb->len, GFP_ATOMIC);
2291	if (*sp) {
2292	skb_put_data(skb: *sp, data: skb->data, len: skb->len);
2293	skb_trim(skb, len: 0);
2294	} else {
2295	printk(KERN_DEBUG "%s: No mem\n",
2296	__func__);
2297	*sp = skb;
2298	skb = NULL;
2299	}
2300	} else {
2301	skb = NULL;
2302	}
2303	if (debug & DEBUG_HFCMULTI_FIFO) {
2304	printk(KERN_DEBUG "%s(card %d):",
2305	__func__, hc->id + 1);
2306	temp = 0;
2307	while (temp < (*sp)->len)
2308	printk(" %02x", (*sp)->data[temp++]);
2309	printk("\n");
2310	}
2311	if (dch)
2312	recv_Dchannel(dch);
2313	else
2314	recv_Bchannel(bch, MISDN_ID_ANY, false);
2315	*sp = skb;
2316	again++;
2317	goto next_frame;
2318	}
2319	/* there is an incomplete frame */
2320	} else {
2321	/* transparent */
2322	hc->read_fifo(hc, skb_put(skb: *sp, len: Zsize), Zsize);
2323	if (debug & DEBUG_HFCMULTI_FIFO)
2324	printk(KERN_DEBUG
2325	"%s(card %d): fifo(%d) reading %d bytes "
2326	"(z1=%04x, z2=%04x) TRANS\n",
2327	__func__, hc->id + 1, ch, Zsize, z1, z2);
2328	/* only bch is transparent */
2329	recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2330	}
2331	}
2332
2333
2334	/*
2335	* Interrupt handler
2336	*/
2337	static void
2338	signal_state_up(struct dchannel *dch, int info, char *msg)
2339	{
2340	struct sk_buff *skb;
2341	int id, data = info;
2342
2343	if (debug & DEBUG_HFCMULTI_STATE)
2344	printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2345
2346	id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2347
2348	skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, len: sizeof(data), dp: &data,
2349	GFP_ATOMIC);
2350	if (!skb)
2351	return;
2352	recv_Dchannel_skb(dch, skb);
2353	}
2354
2355	static inline void
2356	handle_timer_irq(struct hfc_multi *hc)
2357	{
2358	int ch, temp;
2359	struct dchannel *dch;
2360	u_long flags;
2361
2362	/* process queued resync jobs */
2363	if (hc->e1_resync) {
2364	/* lock, so e1_resync gets not changed */
2365	spin_lock_irqsave(&HFClock, flags);
2366	if (hc->e1_resync & 1) {
2367	if (debug & DEBUG_HFCMULTI_PLXSD)
2368	printk(KERN_DEBUG "Enable SYNC_I\n");
2369	HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2370	/* disable JATT, if RX_SYNC is set */
2371	if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2372	HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2373	}
2374	if (hc->e1_resync & 2) {
2375	if (debug & DEBUG_HFCMULTI_PLXSD)
2376	printk(KERN_DEBUG "Enable jatt PLL\n");
2377	HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2378	}
2379	if (hc->e1_resync & 4) {
2380	if (debug & DEBUG_HFCMULTI_PLXSD)
2381	printk(KERN_DEBUG
2382	"Enable QUARTZ for HFC-E1\n");
2383	/* set jatt to quartz */
2384	HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2385	| V_JATT_OFF);
2386	/* switch to JATT, in case it is not already */
2387	HFC_outb(hc, R_SYNC_OUT, 0);
2388	}
2389	hc->e1_resync = 0;
2390	spin_unlock_irqrestore(lock: &HFClock, flags);
2391	}
2392
2393	if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2394	for (ch = 0; ch <= 31; ch++) {
2395	if (hc->created[hc->chan[ch].port]) {
2396	hfcmulti_tx(hc, ch);
2397	/* fifo is started when switching to rx-fifo */
2398	hfcmulti_rx(hc, ch);
2399	if (hc->chan[ch].dch &&
2400	hc->chan[ch].nt_timer > -1) {
2401	dch = hc->chan[ch].dch;
2402	if (!(--hc->chan[ch].nt_timer)) {
2403	schedule_event(dch,
2404	FLG_PHCHANGE);
2405	if (debug &
2406	DEBUG_HFCMULTI_STATE)
2407	printk(KERN_DEBUG
2408	"%s: nt_timer at "
2409	"state %x\n",
2410	__func__,
2411	dch->state);
2412	}
2413	}
2414	}
2415	}
2416	if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2417	dch = hc->chan[hc->dnum[0]].dch;
2418	/* LOS */
2419	temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2420	hc->chan[hc->dnum[0]].los = temp;
2421	if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2422	if (!temp && hc->chan[hc->dnum[0]].los)
2423	signal_state_up(dch, L1_SIGNAL_LOS_ON,
2424	msg: "LOS detected");
2425	if (temp && !hc->chan[hc->dnum[0]].los)
2426	signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2427	msg: "LOS gone");
2428	}
2429	if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2430	/* AIS */
2431	temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2432	if (!temp && hc->chan[hc->dnum[0]].ais)
2433	signal_state_up(dch, L1_SIGNAL_AIS_ON,
2434	msg: "AIS detected");
2435	if (temp && !hc->chan[hc->dnum[0]].ais)
2436	signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2437	msg: "AIS gone");
2438	hc->chan[hc->dnum[0]].ais = temp;
2439	}
2440	if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2441	/* SLIP */
2442	temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2443	if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2444	signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2445	msg: " bit SLIP detected RX");
2446	hc->chan[hc->dnum[0]].slip_rx = temp;
2447	temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2448	if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2449	signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2450	msg: " bit SLIP detected TX");
2451	hc->chan[hc->dnum[0]].slip_tx = temp;
2452	}
2453	if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2454	/* RDI */
2455	temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2456	if (!temp && hc->chan[hc->dnum[0]].rdi)
2457	signal_state_up(dch, L1_SIGNAL_RDI_ON,
2458	msg: "RDI detected");
2459	if (temp && !hc->chan[hc->dnum[0]].rdi)
2460	signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2461	msg: "RDI gone");
2462	hc->chan[hc->dnum[0]].rdi = temp;
2463	}
2464	temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2465	switch (hc->chan[hc->dnum[0]].sync) {
2466	case 0:
2467	if ((temp & 0x60) == 0x60) {
2468	if (debug & DEBUG_HFCMULTI_SYNC)
2469	printk(KERN_DEBUG
2470	"%s: (id=%d) E1 now "
2471	"in clock sync\n",
2472	__func__, hc->id);
2473	HFC_outb(hc, R_RX_OFF,
2474	hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2475	HFC_outb(hc, R_TX_OFF,
2476	hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2477	hc->chan[hc->dnum[0]].sync = 1;
2478	goto check_framesync;
2479	}
2480	break;
2481	case 1:
2482	if ((temp & 0x60) != 0x60) {
2483	if (debug & DEBUG_HFCMULTI_SYNC)
2484	printk(KERN_DEBUG
2485	"%s: (id=%d) E1 "
2486	"lost clock sync\n",
2487	__func__, hc->id);
2488	hc->chan[hc->dnum[0]].sync = 0;
2489	break;
2490	}
2491	check_framesync:
2492	temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2493	if (temp == 0x27) {
2494	if (debug & DEBUG_HFCMULTI_SYNC)
2495	printk(KERN_DEBUG
2496	"%s: (id=%d) E1 "
2497	"now in frame sync\n",
2498	__func__, hc->id);
2499	hc->chan[hc->dnum[0]].sync = 2;
2500	}
2501	break;
2502	case 2:
2503	if ((temp & 0x60) != 0x60) {
2504	if (debug & DEBUG_HFCMULTI_SYNC)
2505	printk(KERN_DEBUG
2506	"%s: (id=%d) E1 lost "
2507	"clock & frame sync\n",
2508	__func__, hc->id);
2509	hc->chan[hc->dnum[0]].sync = 0;
2510	break;
2511	}
2512	temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2513	if (temp != 0x27) {
2514	if (debug & DEBUG_HFCMULTI_SYNC)
2515	printk(KERN_DEBUG
2516	"%s: (id=%d) E1 "
2517	"lost frame sync\n",
2518	__func__, hc->id);
2519	hc->chan[hc->dnum[0]].sync = 1;
2520	}
2521	break;
2522	}
2523	}
2524
2525	if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2526	hfcmulti_watchdog(hc);
2527
2528	if (hc->leds)
2529	hfcmulti_leds(hc);
2530	}
2531
2532	static void
2533	ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2534	{
2535	struct dchannel *dch;
2536	int ch;
2537	int active;
2538	u_char st_status, temp;
2539
2540	/* state machine */
2541	for (ch = 0; ch <= 31; ch++) {
2542	if (hc->chan[ch].dch) {
2543	dch = hc->chan[ch].dch;
2544	if (r_irq_statech & 1) {
2545	HFC_outb_nodebug(hc, R_ST_SEL,
2546	hc->chan[ch].port);
2547	/* undocumented: delay after R_ST_SEL */
2548	udelay(usec: 1);
2549	/* undocumented: status changes during read */
2550	st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2551	while (st_status != (temp =
2552	HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2553	if (debug & DEBUG_HFCMULTI_STATE)
2554	printk(KERN_DEBUG "%s: reread "
2555	"STATE because %d!=%d\n",
2556	__func__, temp,
2557	st_status);
2558	st_status = temp; /* repeat */
2559	}
2560
2561	/* Speech Design TE-sync indication */
2562	if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2563	dch->dev.D.protocol == ISDN_P_TE_S0) {
2564	if (st_status & V_FR_SYNC_ST)
2565	hc->syncronized |=
2566	(1 << hc->chan[ch].port);
2567	else
2568	hc->syncronized &=
2569	~(1 << hc->chan[ch].port);
2570	}
2571	dch->state = st_status & 0x0f;
2572	if (dch->dev.D.protocol == ISDN_P_NT_S0)
2573	active = 3;
2574	else
2575	active = 7;
2576	if (dch->state == active) {
2577	HFC_outb_nodebug(hc, R_FIFO,
2578	(ch << 1) | 1);
2579	HFC_wait_nodebug(hc);
2580	HFC_outb_nodebug(hc,
2581	R_INC_RES_FIFO, V_RES_F);
2582	HFC_wait_nodebug(hc);
2583	dch->tx_idx = 0;
2584	}
2585	schedule_event(dch, FLG_PHCHANGE);
2586	if (debug & DEBUG_HFCMULTI_STATE)
2587	printk(KERN_DEBUG
2588	"%s: S/T newstate %x port %d\n",
2589	__func__, dch->state,
2590	hc->chan[ch].port);
2591	}
2592	r_irq_statech >>= 1;
2593	}
2594	}
2595	if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2596	plxsd_checksync(hc, rm: 0);
2597	}
2598
2599	static void
2600	fifo_irq(struct hfc_multi *hc, int block)
2601	{
2602	int ch, j;
2603	struct dchannel *dch;
2604	struct bchannel *bch;
2605	u_char r_irq_fifo_bl;
2606
2607	r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2608	j = 0;
2609	while (j < 8) {
2610	ch = (block << 2) + (j >> 1);
2611	dch = hc->chan[ch].dch;
2612	bch = hc->chan[ch].bch;
2613	if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2614	j += 2;
2615	continue;
2616	}
2617	if (dch && (r_irq_fifo_bl & (1 << j)) &&
2618	test_bit(FLG_ACTIVE, &dch->Flags)) {
2619	hfcmulti_tx(hc, ch);
2620	/* start fifo */
2621	HFC_outb_nodebug(hc, R_FIFO, 0);
2622	HFC_wait_nodebug(hc);
2623	}
2624	if (bch && (r_irq_fifo_bl & (1 << j)) &&
2625	test_bit(FLG_ACTIVE, &bch->Flags)) {
2626	hfcmulti_tx(hc, ch);
2627	/* start fifo */
2628	HFC_outb_nodebug(hc, R_FIFO, 0);
2629	HFC_wait_nodebug(hc);
2630	}
2631	j++;
2632	if (dch && (r_irq_fifo_bl & (1 << j)) &&
2633	test_bit(FLG_ACTIVE, &dch->Flags)) {
2634	hfcmulti_rx(hc, ch);
2635	}
2636	if (bch && (r_irq_fifo_bl & (1 << j)) &&
2637	test_bit(FLG_ACTIVE, &bch->Flags)) {
2638	hfcmulti_rx(hc, ch);
2639	}
2640	j++;
2641	}
2642	}
2643
2644	#ifdef IRQ_DEBUG
2645	int irqsem;
2646	#endif
2647	static irqreturn_t
2648	hfcmulti_interrupt(int intno, void *dev_id)
2649	{
2650	#ifdef IRQCOUNT_DEBUG
2651	static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2652	iq5 = 0, iq6 = 0, iqcnt = 0;
2653	#endif
2654	struct hfc_multi *hc = dev_id;
2655	struct dchannel *dch;
2656	u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2657	int i;
2658	void __iomem *plx_acc;
2659	u_short wval;
2660	u_char e1_syncsta, temp, temp2;
2661	u_long flags;
2662
2663	if (!hc) {
2664	printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2665	return IRQ_NONE;
2666	}
2667
2668	spin_lock(lock: &hc->lock);
2669
2670	#ifdef IRQ_DEBUG
2671	if (irqsem)
2672	printk(KERN_ERR "irq for card %d during irq from "
2673	"card %d, this is no bug.\n", hc->id + 1, irqsem);
2674	irqsem = hc->id + 1;
2675	#endif
2676	#ifdef CONFIG_MISDN_HFCMULTI_8xx
2677	if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2678	goto irq_notforus;
2679	#endif
2680	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2681	spin_lock_irqsave(&plx_lock, flags);
2682	plx_acc = hc->plx_membase + PLX_INTCSR;
2683	wval = readw(addr: plx_acc);
2684	spin_unlock_irqrestore(lock: &plx_lock, flags);
2685	if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2686	goto irq_notforus;
2687	}
2688
2689	status = HFC_inb_nodebug(hc, R_STATUS);
2690	r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2691	#ifdef IRQCOUNT_DEBUG
2692	if (r_irq_statech)
2693	iq1++;
2694	if (status & V_DTMF_STA)
2695	iq2++;
2696	if (status & V_LOST_STA)
2697	iq3++;
2698	if (status & V_EXT_IRQSTA)
2699	iq4++;
2700	if (status & V_MISC_IRQSTA)
2701	iq5++;
2702	if (status & V_FR_IRQSTA)
2703	iq6++;
2704	if (iqcnt++ > 5000) {
2705	printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2706	iq1, iq2, iq3, iq4, iq5, iq6);
2707	iqcnt = 0;
2708	}
2709	#endif
2710
2711	if (!r_irq_statech &&
2712	!(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2713	V_MISC_IRQSTA | V_FR_IRQSTA))) {
2714	/* irq is not for us */
2715	goto irq_notforus;
2716	}
2717	hc->irqcnt++;
2718	if (r_irq_statech) {
2719	if (hc->ctype != HFC_TYPE_E1)
2720	ph_state_irq(hc, r_irq_statech);
2721	}
2722	if (status & V_LOST_STA) {
2723	/* LOST IRQ */
2724	HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2725	}
2726	if (status & V_MISC_IRQSTA) {
2727	/* misc IRQ */
2728	r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2729	r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2730	if (r_irq_misc & V_STA_IRQ) {
2731	if (hc->ctype == HFC_TYPE_E1) {
2732	/* state machine */
2733	dch = hc->chan[hc->dnum[0]].dch;
2734	e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2735	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2736	&& hc->e1_getclock) {
2737	if (e1_syncsta & V_FR_SYNC_E1)
2738	hc->syncronized = 1;
2739	else
2740	hc->syncronized = 0;
2741	}
2742	/* undocumented: status changes during read */
2743	temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2744	while (temp != (temp2 =
2745	HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2746	if (debug & DEBUG_HFCMULTI_STATE)
2747	printk(KERN_DEBUG "%s: reread "
2748	"STATE because %d!=%d\n",
2749	__func__, temp, temp2);
2750	temp = temp2; /* repeat */
2751	}
2752	/* broadcast state change to all fragments */
2753	if (debug & DEBUG_HFCMULTI_STATE)
2754	printk(KERN_DEBUG
2755	"%s: E1 (id=%d) newstate %x\n",
2756	__func__, hc->id, temp & 0x7);
2757	for (i = 0; i < hc->ports; i++) {
2758	dch = hc->chan[hc->dnum[i]].dch;
2759	dch->state = temp & 0x7;
2760	schedule_event(dch, FLG_PHCHANGE);
2761	}
2762
2763	if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2764	plxsd_checksync(hc, rm: 0);
2765	}
2766	}
2767	if (r_irq_misc & V_TI_IRQ) {
2768	if (hc->iclock_on)
2769	mISDN_clock_update(hc->iclock, poll, NULL);
2770	handle_timer_irq(hc);
2771	}
2772
2773	if (r_irq_misc & V_DTMF_IRQ)
2774	hfcmulti_dtmf(hc);
2775
2776	if (r_irq_misc & V_IRQ_PROC) {
2777	static int irq_proc_cnt;
2778	if (!irq_proc_cnt++)
2779	printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2780	" this should not happen\n", __func__);
2781	}
2782
2783	}
2784	if (status & V_FR_IRQSTA) {
2785	/* FIFO IRQ */
2786	r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2787	for (i = 0; i < 8; i++) {
2788	if (r_irq_oview & (1 << i))
2789	fifo_irq(hc, block: i);
2790	}
2791	}
2792
2793	#ifdef IRQ_DEBUG
2794	irqsem = 0;
2795	#endif
2796	spin_unlock(lock: &hc->lock);
2797	return IRQ_HANDLED;
2798
2799	irq_notforus:
2800	#ifdef IRQ_DEBUG
2801	irqsem = 0;
2802	#endif
2803	spin_unlock(lock: &hc->lock);
2804	return IRQ_NONE;
2805	}
2806
2807
2808	/*
2809	* timer callback for D-chan busy resolution. Currently no function
2810	*/
2811
2812	static void
2813	hfcmulti_dbusy_timer(struct timer_list *t)
2814	{
2815	}
2816
2817
2818	/*
2819	* activate/deactivate hardware for selected channels and mode
2820	*
2821	* configure B-channel with the given protocol
2822	* ch eqals to the HFC-channel (0-31)
2823	* ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2824	* for S/T, 1-31 for E1)
2825	* the hdlc interrupts will be set/unset
2826	*/
2827	static int
2828	mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2829	int bank_tx, int slot_rx, int bank_rx)
2830	{
2831	int flow_tx = 0, flow_rx = 0, routing = 0;
2832	int oslot_tx, oslot_rx;
2833	int conf;
2834
2835	if (ch < 0 || ch > 31)
2836	return -EINVAL;
2837	oslot_tx = hc->chan[ch].slot_tx;
2838	oslot_rx = hc->chan[ch].slot_rx;
2839	conf = hc->chan[ch].conf;
2840
2841	if (debug & DEBUG_HFCMULTI_MODE)
2842	printk(KERN_DEBUG
2843	"%s: card %d channel %d protocol %x slot old=%d new=%d "
2844	"bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2845	__func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2846	bank_tx, oslot_rx, slot_rx, bank_rx);
2847
2848	if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2849	/* remove from slot */
2850	if (debug & DEBUG_HFCMULTI_MODE)
2851	printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2852	__func__, oslot_tx);
2853	if (hc->slot_owner[oslot_tx << 1] == ch) {
2854	HFC_outb(hc, R_SLOT, oslot_tx << 1);
2855	HFC_outb(hc, A_SL_CFG, 0);
2856	if (hc->ctype != HFC_TYPE_XHFC)
2857	HFC_outb(hc, A_CONF, 0);
2858	hc->slot_owner[oslot_tx << 1] = -1;
2859	} else {
2860	if (debug & DEBUG_HFCMULTI_MODE)
2861	printk(KERN_DEBUG
2862	"%s: we are not owner of this tx slot "
2863	"anymore, channel %d is.\n",
2864	__func__, hc->slot_owner[oslot_tx << 1]);
2865	}
2866	}
2867
2868	if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2869	/* remove from slot */
2870	if (debug & DEBUG_HFCMULTI_MODE)
2871	printk(KERN_DEBUG
2872	"%s: remove from slot %d (RX)\n",
2873	__func__, oslot_rx);
2874	if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2875	HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2876	HFC_outb(hc, A_SL_CFG, 0);
2877	hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2878	} else {
2879	if (debug & DEBUG_HFCMULTI_MODE)
2880	printk(KERN_DEBUG
2881	"%s: we are not owner of this rx slot "
2882	"anymore, channel %d is.\n",
2883	__func__,
2884	hc->slot_owner[(oslot_rx << 1) | 1]);
2885	}
2886	}
2887
2888	if (slot_tx < 0) {
2889	flow_tx = 0x80; /* FIFO->ST */
2890	/* disable pcm slot */
2891	hc->chan[ch].slot_tx = -1;
2892	hc->chan[ch].bank_tx = 0;
2893	} else {
2894	/* set pcm slot */
2895	if (hc->chan[ch].txpending)
2896	flow_tx = 0x80; /* FIFO->ST */
2897	else
2898	flow_tx = 0xc0; /* PCM->ST */
2899	/* put on slot */
2900	routing = bank_tx ? 0xc0 : 0x80;
2901	if (conf >= 0 || bank_tx > 1)
2902	routing = 0x40; /* loop */
2903	if (debug & DEBUG_HFCMULTI_MODE)
2904	printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2905	" %d flow %02x routing %02x conf %d (TX)\n",
2906	__func__, ch, slot_tx, bank_tx,
2907	flow_tx, routing, conf);
2908	HFC_outb(hc, R_SLOT, slot_tx << 1);
2909	HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2910	if (hc->ctype != HFC_TYPE_XHFC)
2911	HFC_outb(hc, A_CONF,
2912	(conf < 0) ? 0 : (conf | V_CONF_SL));
2913	hc->slot_owner[slot_tx << 1] = ch;
2914	hc->chan[ch].slot_tx = slot_tx;
2915	hc->chan[ch].bank_tx = bank_tx;
2916	}
2917	if (slot_rx < 0) {
2918	/* disable pcm slot */
2919	flow_rx = 0x80; /* ST->FIFO */
2920	hc->chan[ch].slot_rx = -1;
2921	hc->chan[ch].bank_rx = 0;
2922	} else {
2923	/* set pcm slot */
2924	if (hc->chan[ch].txpending)
2925	flow_rx = 0x80; /* ST->FIFO */
2926	else
2927	flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2928	/* put on slot */
2929	routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2930	if (conf >= 0 || bank_rx > 1)
2931	routing = 0x40; /* loop */
2932	if (debug & DEBUG_HFCMULTI_MODE)
2933	printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2934	" %d flow %02x routing %02x conf %d (RX)\n",
2935	__func__, ch, slot_rx, bank_rx,
2936	flow_rx, routing, conf);
2937	HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2938	HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2939	hc->slot_owner[(slot_rx << 1) | 1] = ch;
2940	hc->chan[ch].slot_rx = slot_rx;
2941	hc->chan[ch].bank_rx = bank_rx;
2942	}
2943
2944	switch (protocol) {
2945	case (ISDN_P_NONE):
2946	/* disable TX fifo */
2947	HFC_outb(hc, R_FIFO, ch << 1);
2948	HFC_wait(hc);
2949	HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2950	HFC_outb(hc, A_SUBCH_CFG, 0);
2951	HFC_outb(hc, A_IRQ_MSK, 0);
2952	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2953	HFC_wait(hc);
2954	/* disable RX fifo */
2955	HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2956	HFC_wait(hc);
2957	HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2958	HFC_outb(hc, A_SUBCH_CFG, 0);
2959	HFC_outb(hc, A_IRQ_MSK, 0);
2960	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2961	HFC_wait(hc);
2962	if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2963	hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2964	((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2965	HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2966	/* undocumented: delay after R_ST_SEL */
2967	udelay(usec: 1);
2968	HFC_outb(hc, A_ST_CTRL0,
2969	hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2970	}
2971	if (hc->chan[ch].bch) {
2972	test_and_clear_bit(FLG_HDLC, addr: &hc->chan[ch].bch->Flags);
2973	test_and_clear_bit(FLG_TRANSPARENT,
2974	addr: &hc->chan[ch].bch->Flags);
2975	}
2976	break;
2977	case (ISDN_P_B_RAW): /* B-channel */
2978
2979	if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2980	(hc->chan[ch].slot_rx < 0) &&
2981	(hc->chan[ch].slot_tx < 0)) {
2982
2983	printk(KERN_DEBUG
2984	"Setting B-channel %d to echo cancelable "
2985	"state on PCM slot %d\n", ch,
2986	((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2987	printk(KERN_DEBUG
2988	"Enabling pass through for channel\n");
2989	vpm_out(c: hc, which: ch, addr: ((ch / 4) * 8) +
2990	((ch % 4) * 4) + 1, data: 0x01);
2991	/* rx path */
2992	/* S/T -> PCM */
2993	HFC_outb(hc, R_FIFO, (ch << 1));
2994	HFC_wait(hc);
2995	HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2996	HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2997	((ch % 4) * 4) + 1) << 1);
2998	HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2999
3000	/* PCM -> FIFO */
3001	HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3002	HFC_wait(hc);
3003	HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3004	HFC_outb(hc, A_SUBCH_CFG, 0);
3005	HFC_outb(hc, A_IRQ_MSK, 0);
3006	if (hc->chan[ch].protocol != protocol) {
3007	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3008	HFC_wait(hc);
3009	}
3010	HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3011	((ch % 4) * 4) + 1) << 1) | 1);
3012	HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3013
3014	/* tx path */
3015	/* PCM -> S/T */
3016	HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3017	HFC_wait(hc);
3018	HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3019	HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3020	((ch % 4) * 4)) << 1) | 1);
3021	HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3022
3023	/* FIFO -> PCM */
3024	HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3025	HFC_wait(hc);
3026	HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3027	HFC_outb(hc, A_SUBCH_CFG, 0);
3028	HFC_outb(hc, A_IRQ_MSK, 0);
3029	if (hc->chan[ch].protocol != protocol) {
3030	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3031	HFC_wait(hc);
3032	}
3033	/* tx silence */
3034	HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3035	HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3036	((ch % 4) * 4)) << 1);
3037	HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3038	} else {
3039	/* enable TX fifo */
3040	HFC_outb(hc, R_FIFO, ch << 1);
3041	HFC_wait(hc);
3042	if (hc->ctype == HFC_TYPE_XHFC)
3043	HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3044	V_HDLC_TRP | V_IFF);
3045	/* Enable FIFO, no interrupt */
3046	else
3047	HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3048	V_HDLC_TRP | V_IFF);
3049	HFC_outb(hc, A_SUBCH_CFG, 0);
3050	HFC_outb(hc, A_IRQ_MSK, 0);
3051	if (hc->chan[ch].protocol != protocol) {
3052	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3053	HFC_wait(hc);
3054	}
3055	/* tx silence */
3056	HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3057	/* enable RX fifo */
3058	HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3059	HFC_wait(hc);
3060	if (hc->ctype == HFC_TYPE_XHFC)
3061	HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3062	V_HDLC_TRP);
3063	/* Enable FIFO, no interrupt*/
3064	else
3065	HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3066	V_HDLC_TRP);
3067	HFC_outb(hc, A_SUBCH_CFG, 0);
3068	HFC_outb(hc, A_IRQ_MSK, 0);
3069	if (hc->chan[ch].protocol != protocol) {
3070	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3071	HFC_wait(hc);
3072	}
3073	}
3074	if (hc->ctype != HFC_TYPE_E1) {
3075	hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3076	((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3077	HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3078	/* undocumented: delay after R_ST_SEL */
3079	udelay(usec: 1);
3080	HFC_outb(hc, A_ST_CTRL0,
3081	hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3082	}
3083	if (hc->chan[ch].bch)
3084	test_and_set_bit(FLG_TRANSPARENT,
3085	addr: &hc->chan[ch].bch->Flags);
3086	break;
3087	case (ISDN_P_B_HDLC): /* B-channel */
3088	case (ISDN_P_TE_S0): /* D-channel */
3089	case (ISDN_P_NT_S0):
3090	case (ISDN_P_TE_E1):
3091	case (ISDN_P_NT_E1):
3092	/* enable TX fifo */
3093	HFC_outb(hc, R_FIFO, ch << 1);
3094	HFC_wait(hc);
3095	if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3096	/* E1 or B-channel */
3097	HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3098	HFC_outb(hc, A_SUBCH_CFG, 0);
3099	} else {
3100	/* D-Channel without HDLC fill flags */
3101	HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3102	HFC_outb(hc, A_SUBCH_CFG, 2);
3103	}
3104	HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3105	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3106	HFC_wait(hc);
3107	/* enable RX fifo */
3108	HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3109	HFC_wait(hc);
3110	HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3111	if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3112	HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3113	else
3114	HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3115	HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3116	HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3117	HFC_wait(hc);
3118	if (hc->chan[ch].bch) {
3119	test_and_set_bit(FLG_HDLC, addr: &hc->chan[ch].bch->Flags);
3120	if (hc->ctype != HFC_TYPE_E1) {
3121	hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3122	((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3123	HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3124	/* undocumented: delay after R_ST_SEL */
3125	udelay(usec: 1);
3126	HFC_outb(hc, A_ST_CTRL0,
3127	hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3128	}
3129	}
3130	break;
3131	default:
3132	printk(KERN_DEBUG "%s: protocol not known %x\n",
3133	__func__, protocol);
3134	hc->chan[ch].protocol = ISDN_P_NONE;
3135	return -ENOPROTOOPT;
3136	}
3137	hc->chan[ch].protocol = protocol;
3138	return 0;
3139	}
3140
3141
3142	/*
3143	* connect/disconnect PCM
3144	*/
3145
3146	static void
3147	hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3148	int slot_rx, int bank_rx)
3149	{
3150	if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3151	/* disable PCM */
3152	mode_hfcmulti(hc, ch, protocol: hc->chan[ch].protocol, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3153	return;
3154	}
3155
3156	/* enable pcm */
3157	mode_hfcmulti(hc, ch, protocol: hc->chan[ch].protocol, slot_tx, bank_tx,
3158	slot_rx, bank_rx);
3159	}
3160
3161	/*
3162	* set/disable conference
3163	*/
3164
3165	static void
3166	hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3167	{
3168	if (num >= 0 && num <= 7)
3169	hc->chan[ch].conf = num;
3170	else
3171	hc->chan[ch].conf = -1;
3172	mode_hfcmulti(hc, ch, protocol: hc->chan[ch].protocol, slot_tx: hc->chan[ch].slot_tx,
3173	bank_tx: hc->chan[ch].bank_tx, slot_rx: hc->chan[ch].slot_rx,
3174	bank_rx: hc->chan[ch].bank_rx);
3175	}
3176
3177
3178	/*
3179	* set/disable sample loop
3180	*/
3181
3182	/* NOTE: this function is experimental and therefore disabled */
3183
3184	/*
3185	* Layer 1 callback function
3186	*/
3187	static int
3188	hfcm_l1callback(struct dchannel *dch, u_int cmd)
3189	{
3190	struct hfc_multi *hc = dch->hw;
3191	struct sk_buff_head free_queue;
3192	u_long flags;
3193
3194	switch (cmd) {
3195	case INFO3_P8:
3196	case INFO3_P10:
3197	break;
3198	case HW_RESET_REQ:
3199	/* start activation */
3200	spin_lock_irqsave(&hc->lock, flags);
3201	if (hc->ctype == HFC_TYPE_E1) {
3202	if (debug & DEBUG_HFCMULTI_MSG)
3203	printk(KERN_DEBUG
3204	"%s: HW_RESET_REQ no BRI\n",
3205	__func__);
3206	} else {
3207	HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3208	/* undocumented: delay after R_ST_SEL */
3209	udelay(usec: 1);
3210	HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3211	udelay(usec: 6); /* wait at least 5,21us */
3212	HFC_outb(hc, A_ST_WR_STATE, 3);
3213	HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3214	/* activate */
3215	}
3216	spin_unlock_irqrestore(lock: &hc->lock, flags);
3217	l1_event(dch->l1, HW_POWERUP_IND);
3218	break;
3219	case HW_DEACT_REQ:
3220	__skb_queue_head_init(list: &free_queue);
3221	/* start deactivation */
3222	spin_lock_irqsave(&hc->lock, flags);
3223	if (hc->ctype == HFC_TYPE_E1) {
3224	if (debug & DEBUG_HFCMULTI_MSG)
3225	printk(KERN_DEBUG
3226	"%s: HW_DEACT_REQ no BRI\n",
3227	__func__);
3228	} else {
3229	HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3230	/* undocumented: delay after R_ST_SEL */
3231	udelay(usec: 1);
3232	HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3233	/* deactivate */
3234	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3235	hc->syncronized &=
3236	~(1 << hc->chan[dch->slot].port);
3237	plxsd_checksync(hc, rm: 0);
3238	}
3239	}
3240	skb_queue_splice_init(list: &dch->squeue, head: &free_queue);
3241	if (dch->tx_skb) {
3242	__skb_queue_tail(list: &free_queue, newsk: dch->tx_skb);
3243	dch->tx_skb = NULL;
3244	}
3245	dch->tx_idx = 0;
3246	if (dch->rx_skb) {
3247	__skb_queue_tail(list: &free_queue, newsk: dch->rx_skb);
3248	dch->rx_skb = NULL;
3249	}
3250	test_and_clear_bit(FLG_TX_BUSY, addr: &dch->Flags);
3251	if (test_and_clear_bit(FLG_BUSY_TIMER, addr: &dch->Flags))
3252	timer_delete(timer: &dch->timer);
3253	spin_unlock_irqrestore(lock: &hc->lock, flags);
3254	__skb_queue_purge(list: &free_queue);
3255	break;
3256	case HW_POWERUP_REQ:
3257	spin_lock_irqsave(&hc->lock, flags);
3258	if (hc->ctype == HFC_TYPE_E1) {
3259	if (debug & DEBUG_HFCMULTI_MSG)
3260	printk(KERN_DEBUG
3261	"%s: HW_POWERUP_REQ no BRI\n",
3262	__func__);
3263	} else {
3264	HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3265	/* undocumented: delay after R_ST_SEL */
3266	udelay(usec: 1);
3267	HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3268	udelay(usec: 6); /* wait at least 5,21us */
3269	HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3270	}
3271	spin_unlock_irqrestore(lock: &hc->lock, flags);
3272	break;
3273	case PH_ACTIVATE_IND:
3274	test_and_set_bit(FLG_ACTIVE, addr: &dch->Flags);
3275	_queue_data(ch: &dch->dev.D, prim: cmd, MISDN_ID_ANY, len: 0, NULL,
3276	GFP_ATOMIC);
3277	break;
3278	case PH_DEACTIVATE_IND:
3279	test_and_clear_bit(FLG_ACTIVE, addr: &dch->Flags);
3280	_queue_data(ch: &dch->dev.D, prim: cmd, MISDN_ID_ANY, len: 0, NULL,
3281	GFP_ATOMIC);
3282	break;
3283	default:
3284	if (dch->debug & DEBUG_HW)
3285	printk(KERN_DEBUG "%s: unknown command %x\n",
3286	__func__, cmd);
3287	return -1;
3288	}
3289	return 0;
3290	}
3291
3292	/*
3293	* Layer2 -> Layer 1 Transfer
3294	*/
3295
3296	static int
3297	handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3298	{
3299	struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3300	struct dchannel *dch = container_of(dev, struct dchannel, dev);
3301	struct hfc_multi *hc = dch->hw;
3302	struct mISDNhead *hh = mISDN_HEAD_P(skb);
3303	int ret = -EINVAL;
3304	unsigned int id;
3305	u_long flags;
3306
3307	switch (hh->prim) {
3308	case PH_DATA_REQ:
3309	if (skb->len < 1)
3310	break;
3311	spin_lock_irqsave(&hc->lock, flags);
3312	ret = dchannel_senddata(dch, skb);
3313	if (ret > 0) { /* direct TX */
3314	id = hh->id; /* skb can be freed */
3315	hfcmulti_tx(hc, ch: dch->slot);
3316	ret = 0;
3317	/* start fifo */
3318	HFC_outb(hc, R_FIFO, 0);
3319	HFC_wait(hc);
3320	spin_unlock_irqrestore(lock: &hc->lock, flags);
3321	queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3322	} else
3323	spin_unlock_irqrestore(lock: &hc->lock, flags);
3324	return ret;
3325	case PH_ACTIVATE_REQ:
3326	if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3327	spin_lock_irqsave(&hc->lock, flags);
3328	ret = 0;
3329	if (debug & DEBUG_HFCMULTI_MSG)
3330	printk(KERN_DEBUG
3331	"%s: PH_ACTIVATE port %d (0..%d)\n",
3332	__func__, hc->chan[dch->slot].port,
3333	hc->ports - 1);
3334	/* start activation */
3335	if (hc->ctype == HFC_TYPE_E1) {
3336	ph_state_change(dch);
3337	if (debug & DEBUG_HFCMULTI_STATE)
3338	printk(KERN_DEBUG
3339	"%s: E1 report state %x \n",
3340	__func__, dch->state);
3341	} else {
3342	HFC_outb(hc, R_ST_SEL,
3343	hc->chan[dch->slot].port);
3344	/* undocumented: delay after R_ST_SEL */
3345	udelay(usec: 1);
3346	HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3347	/* G1 */
3348	udelay(usec: 6); /* wait at least 5,21us */
3349	HFC_outb(hc, A_ST_WR_STATE, 1);
3350	HFC_outb(hc, A_ST_WR_STATE, 1 |
3351	(V_ST_ACT * 3)); /* activate */
3352	dch->state = 1;
3353	}
3354	spin_unlock_irqrestore(lock: &hc->lock, flags);
3355	} else
3356	ret = l1_event(dch->l1, hh->prim);
3357	break;
3358	case PH_DEACTIVATE_REQ:
3359	test_and_clear_bit(FLG_L2_ACTIVATED, addr: &dch->Flags);
3360	if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3361	struct sk_buff_head free_queue;
3362
3363	__skb_queue_head_init(list: &free_queue);
3364	spin_lock_irqsave(&hc->lock, flags);
3365	if (debug & DEBUG_HFCMULTI_MSG)
3366	printk(KERN_DEBUG
3367	"%s: PH_DEACTIVATE port %d (0..%d)\n",
3368	__func__, hc->chan[dch->slot].port,
3369	hc->ports - 1);
3370	/* start deactivation */
3371	if (hc->ctype == HFC_TYPE_E1) {
3372	if (debug & DEBUG_HFCMULTI_MSG)
3373	printk(KERN_DEBUG
3374	"%s: PH_DEACTIVATE no BRI\n",
3375	__func__);
3376	} else {
3377	HFC_outb(hc, R_ST_SEL,
3378	hc->chan[dch->slot].port);
3379	/* undocumented: delay after R_ST_SEL */
3380	udelay(usec: 1);
3381	HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3382	/* deactivate */
3383	dch->state = 1;
3384	}
3385	skb_queue_splice_init(list: &dch->squeue, head: &free_queue);
3386	if (dch->tx_skb) {
3387	__skb_queue_tail(list: &free_queue, newsk: dch->tx_skb);
3388	dch->tx_skb = NULL;
3389	}
3390	dch->tx_idx = 0;
3391	if (dch->rx_skb) {
3392	__skb_queue_tail(list: &free_queue, newsk: dch->rx_skb);
3393	dch->rx_skb = NULL;
3394	}
3395	test_and_clear_bit(FLG_TX_BUSY, addr: &dch->Flags);
3396	if (test_and_clear_bit(FLG_BUSY_TIMER, addr: &dch->Flags))
3397	timer_delete(timer: &dch->timer);
3398	#ifdef FIXME
3399	if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3400	dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3401	#endif
3402	ret = 0;
3403	spin_unlock_irqrestore(lock: &hc->lock, flags);
3404	__skb_queue_purge(list: &free_queue);
3405	} else
3406	ret = l1_event(dch->l1, hh->prim);
3407	break;
3408	}
3409	if (!ret)
3410	dev_kfree_skb(skb);
3411	return ret;
3412	}
3413
3414	static void
3415	deactivate_bchannel(struct bchannel *bch)
3416	{
3417	struct hfc_multi *hc = bch->hw;
3418	u_long flags;
3419
3420	spin_lock_irqsave(&hc->lock, flags);
3421	mISDN_clear_bchannel(bch);
3422	hc->chan[bch->slot].coeff_count = 0;
3423	hc->chan[bch->slot].rx_off = 0;
3424	hc->chan[bch->slot].conf = -1;
3425	mode_hfcmulti(hc, ch: bch->slot, ISDN_P_NONE, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3426	spin_unlock_irqrestore(lock: &hc->lock, flags);
3427	}
3428
3429	static int
3430	handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3431	{
3432	struct bchannel *bch = container_of(ch, struct bchannel, ch);
3433	struct hfc_multi *hc = bch->hw;
3434	int ret = -EINVAL;
3435	struct mISDNhead *hh = mISDN_HEAD_P(skb);
3436	unsigned long flags;
3437
3438	switch (hh->prim) {
3439	case PH_DATA_REQ:
3440	if (!skb->len)
3441	break;
3442	spin_lock_irqsave(&hc->lock, flags);
3443	ret = bchannel_senddata(bch, skb);
3444	if (ret > 0) { /* direct TX */
3445	hfcmulti_tx(hc, ch: bch->slot);
3446	ret = 0;
3447	/* start fifo */
3448	HFC_outb_nodebug(hc, R_FIFO, 0);
3449	HFC_wait_nodebug(hc);
3450	}
3451	spin_unlock_irqrestore(lock: &hc->lock, flags);
3452	return ret;
3453	case PH_ACTIVATE_REQ:
3454	if (debug & DEBUG_HFCMULTI_MSG)
3455	printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3456	__func__, bch->slot);
3457	spin_lock_irqsave(&hc->lock, flags);
3458	/* activate B-channel if not already activated */
3459	if (!test_and_set_bit(FLG_ACTIVE, addr: &bch->Flags)) {
3460	hc->chan[bch->slot].txpending = 0;
3461	ret = mode_hfcmulti(hc, ch: bch->slot,
3462	protocol: ch->protocol,
3463	slot_tx: hc->chan[bch->slot].slot_tx,
3464	bank_tx: hc->chan[bch->slot].bank_tx,
3465	slot_rx: hc->chan[bch->slot].slot_rx,
3466	bank_rx: hc->chan[bch->slot].bank_rx);
3467	if (!ret) {
3468	if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3469	&& test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3470	/* start decoder */
3471	hc->dtmf = 1;
3472	if (debug & DEBUG_HFCMULTI_DTMF)
3473	printk(KERN_DEBUG
3474	"%s: start dtmf decoder\n",
3475	__func__);
3476	HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3477	V_RST_DTMF);
3478	}
3479	}
3480	} else
3481	ret = 0;
3482	spin_unlock_irqrestore(lock: &hc->lock, flags);
3483	if (!ret)
3484	_queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, len: 0, NULL,
3485	GFP_KERNEL);
3486	break;
3487	case PH_CONTROL_REQ:
3488	spin_lock_irqsave(&hc->lock, flags);
3489	switch (hh->id) {
3490	case HFC_SPL_LOOP_ON: /* set sample loop */
3491	if (debug & DEBUG_HFCMULTI_MSG)
3492	printk(KERN_DEBUG
3493	"%s: HFC_SPL_LOOP_ON (len = %d)\n",
3494	__func__, skb->len);
3495	ret = 0;
3496	break;
3497	case HFC_SPL_LOOP_OFF: /* set silence */
3498	if (debug & DEBUG_HFCMULTI_MSG)
3499	printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3500	__func__);
3501	ret = 0;
3502	break;
3503	default:
3504	printk(KERN_ERR
3505	"%s: unknown PH_CONTROL_REQ info %x\n",
3506	__func__, hh->id);
3507	ret = -EINVAL;
3508	}
3509	spin_unlock_irqrestore(lock: &hc->lock, flags);
3510	break;
3511	case PH_DEACTIVATE_REQ:
3512	deactivate_bchannel(bch); /* locked there */
3513	_queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, len: 0, NULL,
3514	GFP_KERNEL);
3515	ret = 0;
3516	break;
3517	}
3518	if (!ret)
3519	dev_kfree_skb(skb);
3520	return ret;
3521	}
3522
3523	/*
3524	* bchannel control function
3525	*/
3526	static int
3527	channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3528	{
3529	int ret = 0;
3530	struct dsp_features *features =
3531	(struct dsp_features *)(*((u_long *)&cq->p1));
3532	struct hfc_multi *hc = bch->hw;
3533	int slot_tx;
3534	int bank_tx;
3535	int slot_rx;
3536	int bank_rx;
3537	int num;
3538
3539	switch (cq->op) {
3540	case MISDN_CTRL_GETOP:
3541	ret = mISDN_ctrl_bchannel(bch, cq);
3542	cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3543	break;
3544	case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3545	ret = mISDN_ctrl_bchannel(bch, cq);
3546	hc->chan[bch->slot].rx_off = !!cq->p1;
3547	if (!hc->chan[bch->slot].rx_off) {
3548	/* reset fifo on rx on */
3549	HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3550	HFC_wait_nodebug(hc);
3551	HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3552	HFC_wait_nodebug(hc);
3553	}
3554	if (debug & DEBUG_HFCMULTI_MSG)
3555	printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3556	__func__, bch->nr, hc->chan[bch->slot].rx_off);
3557	break;
3558	case MISDN_CTRL_FILL_EMPTY:
3559	ret = mISDN_ctrl_bchannel(bch, cq);
3560	hc->silence = bch->fill[0];
3561	memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3562	break;
3563	case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3564	if (debug & DEBUG_HFCMULTI_MSG)
3565	printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3566	__func__);
3567	/* create confirm */
3568	features->hfc_id = hc->id;
3569	if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3570	features->hfc_dtmf = 1;
3571	if (test_bit(HFC_CHIP_CONF, &hc->chip))
3572	features->hfc_conf = 1;
3573	features->hfc_loops = 0;
3574	if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3575	features->hfc_echocanhw = 1;
3576	} else {
3577	features->pcm_id = hc->pcm;
3578	features->pcm_slots = hc->slots;
3579	features->pcm_banks = 2;
3580	}
3581	break;
3582	case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3583	slot_tx = cq->p1 & 0xff;
3584	bank_tx = cq->p1 >> 8;
3585	slot_rx = cq->p2 & 0xff;
3586	bank_rx = cq->p2 >> 8;
3587	if (debug & DEBUG_HFCMULTI_MSG)
3588	printk(KERN_DEBUG
3589	"%s: HFC_PCM_CONN slot %d bank %d (TX) "
3590	"slot %d bank %d (RX)\n",
3591	__func__, slot_tx, bank_tx,
3592	slot_rx, bank_rx);
3593	if (slot_tx < hc->slots && bank_tx <= 2 &&
3594	slot_rx < hc->slots && bank_rx <= 2)
3595	hfcmulti_pcm(hc, ch: bch->slot,
3596	slot_tx, bank_tx, slot_rx, bank_rx);
3597	else {
3598	printk(KERN_WARNING
3599	"%s: HFC_PCM_CONN slot %d bank %d (TX) "
3600	"slot %d bank %d (RX) out of range\n",
3601	__func__, slot_tx, bank_tx,
3602	slot_rx, bank_rx);
3603	ret = -EINVAL;
3604	}
3605	break;
3606	case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3607	if (debug & DEBUG_HFCMULTI_MSG)
3608	printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3609	__func__);
3610	hfcmulti_pcm(hc, ch: bch->slot, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3611	break;
3612	case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3613	num = cq->p1 & 0xff;
3614	if (debug & DEBUG_HFCMULTI_MSG)
3615	printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3616	__func__, num);
3617	if (num <= 7)
3618	hfcmulti_conf(hc, ch: bch->slot, num);
3619	else {
3620	printk(KERN_WARNING
3621	"%s: HW_CONF_JOIN conf %d out of range\n",
3622	__func__, num);
3623	ret = -EINVAL;
3624	}
3625	break;
3626	case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3627	if (debug & DEBUG_HFCMULTI_MSG)
3628	printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3629	hfcmulti_conf(hc, ch: bch->slot, num: -1);
3630	break;
3631	case MISDN_CTRL_HFC_ECHOCAN_ON:
3632	if (debug & DEBUG_HFCMULTI_MSG)
3633	printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3634	if (test_bit(HFC_CHIP_B410P, &hc->chip))
3635	vpm_echocan_on(hc, ch: bch->slot, taps: cq->p1);
3636	else
3637	ret = -EINVAL;
3638	break;
3639
3640	case MISDN_CTRL_HFC_ECHOCAN_OFF:
3641	if (debug & DEBUG_HFCMULTI_MSG)
3642	printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3643	__func__);
3644	if (test_bit(HFC_CHIP_B410P, &hc->chip))
3645	vpm_echocan_off(hc, ch: bch->slot);
3646	else
3647	ret = -EINVAL;
3648	break;
3649	default:
3650	ret = mISDN_ctrl_bchannel(bch, cq);
3651	break;
3652	}
3653	return ret;
3654	}
3655
3656	static int
3657	hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3658	{
3659	struct bchannel *bch = container_of(ch, struct bchannel, ch);
3660	struct hfc_multi *hc = bch->hw;
3661	int err = -EINVAL;
3662	u_long flags;
3663
3664	if (bch->debug & DEBUG_HW)
3665	printk(KERN_DEBUG "%s: cmd:%x %p\n",
3666	__func__, cmd, arg);
3667	switch (cmd) {
3668	case CLOSE_CHANNEL:
3669	test_and_clear_bit(FLG_OPEN, addr: &bch->Flags);
3670	deactivate_bchannel(bch); /* locked there */
3671	ch->protocol = ISDN_P_NONE;
3672	ch->peer = NULL;
3673	module_put(THIS_MODULE);
3674	err = 0;
3675	break;
3676	case CONTROL_CHANNEL:
3677	spin_lock_irqsave(&hc->lock, flags);
3678	err = channel_bctrl(bch, cq: arg);
3679	spin_unlock_irqrestore(lock: &hc->lock, flags);
3680	break;
3681	default:
3682	printk(KERN_WARNING "%s: unknown prim(%x)\n",
3683	__func__, cmd);
3684	}
3685	return err;
3686	}
3687
3688	/*
3689	* handle D-channel events
3690	*
3691	* handle state change event
3692	*/
3693	static void
3694	ph_state_change(struct dchannel *dch)
3695	{
3696	struct hfc_multi *hc;
3697	int ch, i;
3698
3699	if (!dch) {
3700	printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3701	return;
3702	}
3703	hc = dch->hw;
3704	ch = dch->slot;
3705
3706	if (hc->ctype == HFC_TYPE_E1) {
3707	if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3708	if (debug & DEBUG_HFCMULTI_STATE)
3709	printk(KERN_DEBUG
3710	"%s: E1 TE (id=%d) newstate %x\n",
3711	__func__, hc->id, dch->state);
3712	} else {
3713	if (debug & DEBUG_HFCMULTI_STATE)
3714	printk(KERN_DEBUG
3715	"%s: E1 NT (id=%d) newstate %x\n",
3716	__func__, hc->id, dch->state);
3717	}
3718	switch (dch->state) {
3719	case (1):
3720	if (hc->e1_state != 1) {
3721	for (i = 1; i <= 31; i++) {
3722	/* reset fifos on e1 activation */
3723	HFC_outb_nodebug(hc, R_FIFO,
3724	(i << 1) | 1);
3725	HFC_wait_nodebug(hc);
3726	HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3727	V_RES_F);
3728	HFC_wait_nodebug(hc);
3729	}
3730	}
3731	test_and_set_bit(FLG_ACTIVE, addr: &dch->Flags);
3732	_queue_data(ch: &dch->dev.D, PH_ACTIVATE_IND,
3733	MISDN_ID_ANY, len: 0, NULL, GFP_ATOMIC);
3734	break;
3735
3736	default:
3737	if (hc->e1_state != 1)
3738	return;
3739	test_and_clear_bit(FLG_ACTIVE, addr: &dch->Flags);
3740	_queue_data(ch: &dch->dev.D, PH_DEACTIVATE_IND,
3741	MISDN_ID_ANY, len: 0, NULL, GFP_ATOMIC);
3742	}
3743	hc->e1_state = dch->state;
3744	} else {
3745	if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3746	if (debug & DEBUG_HFCMULTI_STATE)
3747	printk(KERN_DEBUG
3748	"%s: S/T TE newstate %x\n",
3749	__func__, dch->state);
3750	switch (dch->state) {
3751	case (0):
3752	l1_event(dch->l1, HW_RESET_IND);
3753	break;
3754	case (3):
3755	l1_event(dch->l1, HW_DEACT_IND);
3756	break;
3757	case (5):
3758	case (8):
3759	l1_event(dch->l1, ANYSIGNAL);
3760	break;
3761	case (6):
3762	l1_event(dch->l1, INFO2);
3763	break;
3764	case (7):
3765	l1_event(dch->l1, INFO4_P8);
3766	break;
3767	}
3768	} else {
3769	if (debug & DEBUG_HFCMULTI_STATE)
3770	printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3771	__func__, dch->state);
3772	switch (dch->state) {
3773	case (2):
3774	if (hc->chan[ch].nt_timer == 0) {
3775	hc->chan[ch].nt_timer = -1;
3776	HFC_outb(hc, R_ST_SEL,
3777	hc->chan[ch].port);
3778	/* undocumented: delay after R_ST_SEL */
3779	udelay(usec: 1);
3780	HFC_outb(hc, A_ST_WR_STATE, 4 |
3781	V_ST_LD_STA); /* G4 */
3782	udelay(usec: 6); /* wait at least 5,21us */
3783	HFC_outb(hc, A_ST_WR_STATE, 4);
3784	dch->state = 4;
3785	} else {
3786	/* one extra count for the next event */
3787	hc->chan[ch].nt_timer =
3788	nt_t1_count[poll_timer] + 1;
3789	HFC_outb(hc, R_ST_SEL,
3790	hc->chan[ch].port);
3791	/* undocumented: delay after R_ST_SEL */
3792	udelay(usec: 1);
3793	/* allow G2 -> G3 transition */
3794	HFC_outb(hc, A_ST_WR_STATE, 2 |
3795	V_SET_G2_G3);
3796	}
3797	break;
3798	case (1):
3799	hc->chan[ch].nt_timer = -1;
3800	test_and_clear_bit(FLG_ACTIVE, addr: &dch->Flags);
3801	_queue_data(ch: &dch->dev.D, PH_DEACTIVATE_IND,
3802	MISDN_ID_ANY, len: 0, NULL, GFP_ATOMIC);
3803	break;
3804	case (4):
3805	hc->chan[ch].nt_timer = -1;
3806	break;
3807	case (3):
3808	hc->chan[ch].nt_timer = -1;
3809	test_and_set_bit(FLG_ACTIVE, addr: &dch->Flags);
3810	_queue_data(ch: &dch->dev.D, PH_ACTIVATE_IND,
3811	MISDN_ID_ANY, len: 0, NULL, GFP_ATOMIC);
3812	break;
3813	}
3814	}
3815	}
3816	}
3817
3818	/*
3819	* called for card mode init message
3820	*/
3821
3822	static void
3823	hfcmulti_initmode(struct dchannel *dch)
3824	{
3825	struct hfc_multi *hc = dch->hw;
3826	u_char a_st_wr_state, r_e1_wr_sta;
3827	int i, pt;
3828
3829	if (debug & DEBUG_HFCMULTI_INIT)
3830	printk(KERN_DEBUG "%s: entered\n", __func__);
3831
3832	i = dch->slot;
3833	pt = hc->chan[i].port;
3834	if (hc->ctype == HFC_TYPE_E1) {
3835	/* E1 */
3836	hc->chan[hc->dnum[pt]].slot_tx = -1;
3837	hc->chan[hc->dnum[pt]].slot_rx = -1;
3838	hc->chan[hc->dnum[pt]].conf = -1;
3839	if (hc->dnum[pt]) {
3840	mode_hfcmulti(hc, ch: dch->slot, protocol: dch->dev.D.protocol,
3841	slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3842	timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3843	}
3844	for (i = 1; i <= 31; i++) {
3845	if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3846	continue;
3847	hc->chan[i].slot_tx = -1;
3848	hc->chan[i].slot_rx = -1;
3849	hc->chan[i].conf = -1;
3850	mode_hfcmulti(hc, ch: i, ISDN_P_NONE, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3851	}
3852	}
3853	if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3854	/* E1, port 0 */
3855	dch = hc->chan[hc->dnum[0]].dch;
3856	if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3857	HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3858	HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3859	}
3860	if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3861	HFC_outb(hc, R_RX0, 0);
3862	hc->hw.r_tx0 = 0 | V_OUT_EN;
3863	} else {
3864	HFC_outb(hc, R_RX0, 1);
3865	hc->hw.r_tx0 = 1 | V_OUT_EN;
3866	}
3867	hc->hw.r_tx1 = V_ATX | V_NTRI;
3868	HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3869	HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3870	HFC_outb(hc, R_TX_FR0, 0x00);
3871	HFC_outb(hc, R_TX_FR1, 0xf8);
3872
3873	if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3874	HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3875
3876	HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3877
3878	if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3879	HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3880
3881	if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3882	if (debug & DEBUG_HFCMULTI_INIT)
3883	printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3884	__func__);
3885	r_e1_wr_sta = 0; /* G0 */
3886	hc->e1_getclock = 0;
3887	} else {
3888	if (debug & DEBUG_HFCMULTI_INIT)
3889	printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3890	__func__);
3891	r_e1_wr_sta = 0; /* F0 */
3892	hc->e1_getclock = 1;
3893	}
3894	if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3895	HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3896	else
3897	HFC_outb(hc, R_SYNC_OUT, 0);
3898	if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3899	hc->e1_getclock = 1;
3900	if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3901	hc->e1_getclock = 0;
3902	if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3903	/* SLAVE (clock master) */
3904	if (debug & DEBUG_HFCMULTI_INIT)
3905	printk(KERN_DEBUG
3906	"%s: E1 port is clock master "
3907	"(clock from PCM)\n", __func__);
3908	HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3909	} else {
3910	if (hc->e1_getclock) {
3911	/* MASTER (clock slave) */
3912	if (debug & DEBUG_HFCMULTI_INIT)
3913	printk(KERN_DEBUG
3914	"%s: E1 port is clock slave "
3915	"(clock to PCM)\n", __func__);
3916	HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3917	} else {
3918	/* MASTER (clock master) */
3919	if (debug & DEBUG_HFCMULTI_INIT)
3920	printk(KERN_DEBUG "%s: E1 port is "
3921	"clock master "
3922	"(clock from QUARTZ)\n",
3923	__func__);
3924	HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3925	V_PCM_SYNC | V_JATT_OFF);
3926	HFC_outb(hc, R_SYNC_OUT, 0);
3927	}
3928	}
3929	HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3930	HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3931	HFC_outb(hc, R_PWM0, 0x50);
3932	HFC_outb(hc, R_PWM1, 0xff);
3933	/* state machine setup */
3934	HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3935	udelay(usec: 6); /* wait at least 5,21us */
3936	HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3937	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3938	hc->syncronized = 0;
3939	plxsd_checksync(hc, rm: 0);
3940	}
3941	}
3942	if (hc->ctype != HFC_TYPE_E1) {
3943	/* ST */
3944	hc->chan[i].slot_tx = -1;
3945	hc->chan[i].slot_rx = -1;
3946	hc->chan[i].conf = -1;
3947	mode_hfcmulti(hc, ch: i, protocol: dch->dev.D.protocol, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3948	timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3949	hc->chan[i - 2].slot_tx = -1;
3950	hc->chan[i - 2].slot_rx = -1;
3951	hc->chan[i - 2].conf = -1;
3952	mode_hfcmulti(hc, ch: i - 2, ISDN_P_NONE, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3953	hc->chan[i - 1].slot_tx = -1;
3954	hc->chan[i - 1].slot_rx = -1;
3955	hc->chan[i - 1].conf = -1;
3956	mode_hfcmulti(hc, ch: i - 1, ISDN_P_NONE, slot_tx: -1, bank_tx: 0, slot_rx: -1, bank_rx: 0);
3957	/* select interface */
3958	HFC_outb(hc, R_ST_SEL, pt);
3959	/* undocumented: delay after R_ST_SEL */
3960	udelay(usec: 1);
3961	if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3962	if (debug & DEBUG_HFCMULTI_INIT)
3963	printk(KERN_DEBUG
3964	"%s: ST port %d is NT-mode\n",
3965	__func__, pt);
3966	/* clock delay */
3967	HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3968	a_st_wr_state = 1; /* G1 */
3969	hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3970	} else {
3971	if (debug & DEBUG_HFCMULTI_INIT)
3972	printk(KERN_DEBUG
3973	"%s: ST port %d is TE-mode\n",
3974	__func__, pt);
3975	/* clock delay */
3976	HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3977	a_st_wr_state = 2; /* F2 */
3978	hc->hw.a_st_ctrl0[pt] = 0;
3979	}
3980	if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3981	hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3982	if (hc->ctype == HFC_TYPE_XHFC) {
3983	hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
3984	HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
3985	0x7c << 1 /* V_ST_PULSE */);
3986	}
3987	/* line setup */
3988	HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3989	/* disable E-channel */
3990	if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3991	test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3992	HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3993	else
3994	HFC_outb(hc, A_ST_CTRL1, 0);
3995	/* enable B-channel receive */
3996	HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
3997	/* state machine setup */
3998	HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3999	udelay(usec: 6); /* wait at least 5,21us */
4000	HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4001	hc->hw.r_sci_msk |= 1 << pt;
4002	/* state machine interrupts */
4003	HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4004	/* unset sync on port */
4005	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4006	hc->syncronized &=
4007	~(1 << hc->chan[dch->slot].port);
4008	plxsd_checksync(hc, rm: 0);
4009	}
4010	}
4011	if (debug & DEBUG_HFCMULTI_INIT)
4012	printk("%s: done\n", __func__);
4013	}
4014
4015
4016	static int
4017	open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4018	struct channel_req *rq)
4019	{
4020	int err = 0;
4021	u_long flags;
4022
4023	if (debug & DEBUG_HW_OPEN)
4024	printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4025	dch->dev.id, __builtin_return_address(0));
4026	if (rq->protocol == ISDN_P_NONE)
4027	return -EINVAL;
4028	if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4029	(dch->dev.D.protocol != rq->protocol)) {
4030	if (debug & DEBUG_HFCMULTI_MODE)
4031	printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4032	__func__, dch->dev.D.protocol, rq->protocol);
4033	}
4034	if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4035	(rq->protocol != ISDN_P_TE_S0))
4036	l1_event(dch->l1, CLOSE_CHANNEL);
4037	if (dch->dev.D.protocol != rq->protocol) {
4038	if (rq->protocol == ISDN_P_TE_S0) {
4039	err = create_l1(dch, hfcm_l1callback);
4040	if (err)
4041	return err;
4042	}
4043	dch->dev.D.protocol = rq->protocol;
4044	spin_lock_irqsave(&hc->lock, flags);
4045	hfcmulti_initmode(dch);
4046	spin_unlock_irqrestore(lock: &hc->lock, flags);
4047	}
4048	if (test_bit(FLG_ACTIVE, &dch->Flags))
4049	_queue_data(ch: &dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4050	len: 0, NULL, GFP_KERNEL);
4051	rq->ch = &dch->dev.D;
4052	if (!try_module_get(THIS_MODULE))
4053	printk(KERN_WARNING "%s:cannot get module\n", __func__);
4054	return 0;
4055	}
4056
4057	static int
4058	open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4059	struct channel_req *rq)
4060	{
4061	struct bchannel *bch;
4062	int ch;
4063
4064	if (!test_channelmap(nr: rq->adr.channel, map: dch->dev.channelmap))
4065	return -EINVAL;
4066	if (rq->protocol == ISDN_P_NONE)
4067	return -EINVAL;
4068	if (hc->ctype == HFC_TYPE_E1)
4069	ch = rq->adr.channel;
4070	else
4071	ch = (rq->adr.channel - 1) + (dch->slot - 2);
4072	bch = hc->chan[ch].bch;
4073	if (!bch) {
4074	printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4075	__func__, ch);
4076	return -EINVAL;
4077	}
4078	if (test_and_set_bit(FLG_OPEN, addr: &bch->Flags))
4079	return -EBUSY; /* b-channel can be only open once */
4080	bch->ch.protocol = rq->protocol;
4081	hc->chan[ch].rx_off = 0;
4082	rq->ch = &bch->ch;
4083	if (!try_module_get(THIS_MODULE))
4084	printk(KERN_WARNING "%s:cannot get module\n", __func__);
4085	return 0;
4086	}
4087
4088	/*
4089	* device control function
4090	*/
4091	static int
4092	channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4093	{
4094	struct hfc_multi *hc = dch->hw;
4095	int ret = 0;
4096	int wd_mode, wd_cnt;
4097
4098	switch (cq->op) {
4099	case MISDN_CTRL_GETOP:
4100	cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4101	break;
4102	case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4103	wd_cnt = cq->p1 & 0xf;
4104	wd_mode = !!(cq->p1 >> 4);
4105	if (debug & DEBUG_HFCMULTI_MSG)
4106	printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4107	", counter 0x%x\n", __func__,
4108	wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4109	/* set the watchdog timer */
4110	HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4111	hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4112	if (hc->ctype == HFC_TYPE_XHFC)
4113	hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4114	/* init the watchdog register and reset the counter */
4115	HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4116	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4117	/* enable the watchdog output for Speech-Design */
4118	HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4119	HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4120	HFC_outb(hc, R_GPIO_OUT1, 0);
4121	HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4122	}
4123	break;
4124	case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4125	if (debug & DEBUG_HFCMULTI_MSG)
4126	printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4127	__func__);
4128	HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4129	break;
4130	case MISDN_CTRL_L1_TIMER3:
4131	ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4132	break;
4133	default:
4134	printk(KERN_WARNING "%s: unknown Op %x\n",
4135	__func__, cq->op);
4136	ret = -EINVAL;
4137	break;
4138	}
4139	return ret;
4140	}
4141
4142	static int
4143	hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4144	{
4145	struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4146	struct dchannel *dch = container_of(dev, struct dchannel, dev);
4147	struct hfc_multi *hc = dch->hw;
4148	struct channel_req *rq;
4149	int err = 0;
4150	u_long flags;
4151
4152	if (dch->debug & DEBUG_HW)
4153	printk(KERN_DEBUG "%s: cmd:%x %p\n",
4154	__func__, cmd, arg);
4155	switch (cmd) {
4156	case OPEN_CHANNEL:
4157	rq = arg;
4158	switch (rq->protocol) {
4159	case ISDN_P_TE_S0:
4160	case ISDN_P_NT_S0:
4161	if (hc->ctype == HFC_TYPE_E1) {
4162	err = -EINVAL;
4163	break;
4164	}
4165	err = open_dchannel(hc, dch, rq); /* locked there */
4166	break;
4167	case ISDN_P_TE_E1:
4168	case ISDN_P_NT_E1:
4169	if (hc->ctype != HFC_TYPE_E1) {
4170	err = -EINVAL;
4171	break;
4172	}
4173	err = open_dchannel(hc, dch, rq); /* locked there */
4174	break;
4175	default:
4176	spin_lock_irqsave(&hc->lock, flags);
4177	err = open_bchannel(hc, dch, rq);
4178	spin_unlock_irqrestore(lock: &hc->lock, flags);
4179	}
4180	break;
4181	case CLOSE_CHANNEL:
4182	if (debug & DEBUG_HW_OPEN)
4183	printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4184	__func__, dch->dev.id,
4185	__builtin_return_address(0));
4186	module_put(THIS_MODULE);
4187	break;
4188	case CONTROL_CHANNEL:
4189	spin_lock_irqsave(&hc->lock, flags);
4190	err = channel_dctrl(dch, cq: arg);
4191	spin_unlock_irqrestore(lock: &hc->lock, flags);
4192	break;
4193	default:
4194	if (dch->debug & DEBUG_HW)
4195	printk(KERN_DEBUG "%s: unknown command %x\n",
4196	__func__, cmd);
4197	err = -EINVAL;
4198	}
4199	return err;
4200	}
4201
4202	static int
4203	clockctl(void *priv, int enable)
4204	{
4205	struct hfc_multi *hc = priv;
4206
4207	hc->iclock_on = enable;
4208	return 0;
4209	}
4210
4211	/*
4212	* initialize the card
4213	*/
4214
4215	/*
4216	* start timer irq, wait some time and check if we have interrupts.
4217	* if not, reset chip and try again.
4218	*/
4219	static int
4220	init_card(struct hfc_multi *hc)
4221	{
4222	int err = -EIO;
4223	u_long flags;
4224	void __iomem *plx_acc;
4225	u_long plx_flags;
4226
4227	if (debug & DEBUG_HFCMULTI_INIT)
4228	printk(KERN_DEBUG "%s: entered\n", __func__);
4229
4230	spin_lock_irqsave(&hc->lock, flags);
4231	/* set interrupts but leave global interrupt disabled */
4232	hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4233	disable_hwirq(hc);
4234	spin_unlock_irqrestore(lock: &hc->lock, flags);
4235
4236	if (request_irq(irq: hc->irq, handler: hfcmulti_interrupt, IRQF_SHARED,
4237	name: "HFC-multi", dev: hc)) {
4238	printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4239	hc->irq);
4240	hc->irq = 0;
4241	return -EIO;
4242	}
4243
4244	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4245	spin_lock_irqsave(&plx_lock, plx_flags);
4246	plx_acc = hc->plx_membase + PLX_INTCSR;
4247	writew(val: (PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4248	addr: plx_acc); /* enable PCI & LINT1 irq */
4249	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
4250	}
4251
4252	if (debug & DEBUG_HFCMULTI_INIT)
4253	printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4254	__func__, hc->irq, hc->irqcnt);
4255	err = init_chip(hc);
4256	if (err)
4257	goto error;
4258	/*
4259	* Finally enable IRQ output
4260	* this is only allowed, if an IRQ routine is already
4261	* established for this HFC, so don't do that earlier
4262	*/
4263	spin_lock_irqsave(&hc->lock, flags);
4264	enable_hwirq(hc);
4265	spin_unlock_irqrestore(lock: &hc->lock, flags);
4266	/* printk(KERN_DEBUG "no master irq set!!!\n"); */
4267	set_current_state(TASK_UNINTERRUPTIBLE);
4268	schedule_timeout(timeout: (100 * HZ) / 1000); /* Timeout 100ms */
4269	/* turn IRQ off until chip is completely initialized */
4270	spin_lock_irqsave(&hc->lock, flags);
4271	disable_hwirq(hc);
4272	spin_unlock_irqrestore(lock: &hc->lock, flags);
4273	if (debug & DEBUG_HFCMULTI_INIT)
4274	printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4275	__func__, hc->irq, hc->irqcnt);
4276	if (hc->irqcnt) {
4277	if (debug & DEBUG_HFCMULTI_INIT)
4278	printk(KERN_DEBUG "%s: done\n", __func__);
4279
4280	return 0;
4281	}
4282	if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4283	printk(KERN_INFO "ignoring missing interrupts\n");
4284	return 0;
4285	}
4286
4287	printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4288	hc->irq);
4289
4290	err = -EIO;
4291
4292	error:
4293	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4294	spin_lock_irqsave(&plx_lock, plx_flags);
4295	plx_acc = hc->plx_membase + PLX_INTCSR;
4296	writew(val: 0x00, addr: plx_acc); /*disable IRQs*/
4297	spin_unlock_irqrestore(lock: &plx_lock, flags: plx_flags);
4298	}
4299
4300	if (debug & DEBUG_HFCMULTI_INIT)
4301	printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4302	if (hc->irq) {
4303	free_irq(hc->irq, hc);
4304	hc->irq = 0;
4305	}
4306
4307	if (debug & DEBUG_HFCMULTI_INIT)
4308	printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4309	return err;
4310	}
4311
4312	/*
4313	* find pci device and set it up
4314	*/
4315
4316	static int
4317	setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4318	const struct pci_device_id *ent)
4319	{
4320	struct hm_map *m = (struct hm_map *)ent->driver_data;
4321
4322	printk(KERN_INFO
4323	"HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4324	m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4325
4326	hc->pci_dev = pdev;
4327	if (m->clock2)
4328	test_and_set_bit(HFC_CHIP_CLOCK2, addr: &hc->chip);
4329
4330	if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4331	ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4332	test_and_set_bit(HFC_CHIP_B410P, addr: &hc->chip);
4333	test_and_set_bit(HFC_CHIP_PCM_MASTER, addr: &hc->chip);
4334	test_and_clear_bit(HFC_CHIP_PCM_SLAVE, addr: &hc->chip);
4335	hc->slots = 32;
4336	}
4337
4338	if (hc->pci_dev->irq <= 0) {
4339	printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4340	return -EIO;
4341	}
4342	if (pci_enable_device(dev: hc->pci_dev)) {
4343	printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4344	return -EIO;
4345	}
4346	hc->leds = m->leds;
4347	hc->ledstate = 0xAFFEAFFE;
4348	hc->opticalsupport = m->opticalsupport;
4349
4350	hc->pci_iobase = 0;
4351	hc->pci_membase = NULL;
4352	hc->plx_membase = NULL;
4353
4354	/* set memory access methods */
4355	if (m->io_mode) /* use mode from card config */
4356	hc->io_mode = m->io_mode;
4357	switch (hc->io_mode) {
4358	case HFC_IO_MODE_PLXSD:
4359	test_and_set_bit(HFC_CHIP_PLXSD, addr: &hc->chip);
4360	hc->slots = 128; /* required */
4361	hc->HFC_outb = HFC_outb_pcimem;
4362	hc->HFC_inb = HFC_inb_pcimem;
4363	hc->HFC_inw = HFC_inw_pcimem;
4364	hc->HFC_wait = HFC_wait_pcimem;
4365	hc->read_fifo = read_fifo_pcimem;
4366	hc->write_fifo = write_fifo_pcimem;
4367	hc->plx_origmembase = hc->pci_dev->resource[0].start;
4368	/* MEMBASE 1 is PLX PCI Bridge */
4369
4370	if (!hc->plx_origmembase) {
4371	printk(KERN_WARNING
4372	"HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4373	pci_disable_device(dev: hc->pci_dev);
4374	return -EIO;
4375	}
4376
4377	hc->plx_membase = ioremap(offset: hc->plx_origmembase, size: 0x80);
4378	if (!hc->plx_membase) {
4379	printk(KERN_WARNING
4380	"HFC-multi: failed to remap plx address space. "
4381	"(internal error)\n");
4382	pci_disable_device(dev: hc->pci_dev);
4383	return -EIO;
4384	}
4385	printk(KERN_INFO
4386	"HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4387	(u_long)hc->plx_membase, hc->plx_origmembase);
4388
4389	hc->pci_origmembase = hc->pci_dev->resource[2].start;
4390	/* MEMBASE 1 is PLX PCI Bridge */
4391	if (!hc->pci_origmembase) {
4392	printk(KERN_WARNING
4393	"HFC-multi: No IO-Memory for PCI card found\n");
4394	pci_disable_device(dev: hc->pci_dev);
4395	return -EIO;
4396	}
4397
4398	hc->pci_membase = ioremap(offset: hc->pci_origmembase, size: 0x400);
4399	if (!hc->pci_membase) {
4400	printk(KERN_WARNING "HFC-multi: failed to remap io "
4401	"address space. (internal error)\n");
4402	pci_disable_device(dev: hc->pci_dev);
4403	return -EIO;
4404	}
4405
4406	printk(KERN_INFO
4407	"card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4408	"leds-type %d\n",
4409	hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4410	hc->pci_dev->irq, HZ, hc->leds);
4411	pci_write_config_word(dev: hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4412	break;
4413	case HFC_IO_MODE_PCIMEM:
4414	hc->HFC_outb = HFC_outb_pcimem;
4415	hc->HFC_inb = HFC_inb_pcimem;
4416	hc->HFC_inw = HFC_inw_pcimem;
4417	hc->HFC_wait = HFC_wait_pcimem;
4418	hc->read_fifo = read_fifo_pcimem;
4419	hc->write_fifo = write_fifo_pcimem;
4420	hc->pci_origmembase = hc->pci_dev->resource[1].start;
4421	if (!hc->pci_origmembase) {
4422	printk(KERN_WARNING
4423	"HFC-multi: No IO-Memory for PCI card found\n");
4424	pci_disable_device(dev: hc->pci_dev);
4425	return -EIO;
4426	}
4427
4428	hc->pci_membase = ioremap(offset: hc->pci_origmembase, size: 256);
4429	if (!hc->pci_membase) {
4430	printk(KERN_WARNING
4431	"HFC-multi: failed to remap io address space. "
4432	"(internal error)\n");
4433	pci_disable_device(dev: hc->pci_dev);
4434	return -EIO;
4435	}
4436	printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4437	"%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4438	hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4439	pci_write_config_word(dev: hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4440	break;
4441	case HFC_IO_MODE_REGIO:
4442	hc->HFC_outb = HFC_outb_regio;
4443	hc->HFC_inb = HFC_inb_regio;
4444	hc->HFC_inw = HFC_inw_regio;
4445	hc->HFC_wait = HFC_wait_regio;
4446	hc->read_fifo = read_fifo_regio;
4447	hc->write_fifo = write_fifo_regio;
4448	hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4449	if (!hc->pci_iobase) {
4450	printk(KERN_WARNING
4451	"HFC-multi: No IO for PCI card found\n");
4452	pci_disable_device(dev: hc->pci_dev);
4453	return -EIO;
4454	}
4455
4456	if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4457	printk(KERN_WARNING "HFC-multi: failed to request "
4458	"address space at 0x%08lx (internal error)\n",
4459	hc->pci_iobase);
4460	pci_disable_device(dev: hc->pci_dev);
4461	return -EIO;
4462	}
4463
4464	printk(KERN_INFO
4465	"%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4466	m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4467	hc->pci_dev->irq, HZ, hc->leds);
4468	pci_write_config_word(dev: hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4469	break;
4470	default:
4471	printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4472	pci_disable_device(dev: hc->pci_dev);
4473	return -EIO;
4474	}
4475
4476	pci_set_drvdata(pdev: hc->pci_dev, data: hc);
4477
4478	/* At this point the needed PCI config is done */
4479	/* fifos are still not enabled */
4480	return 0;
4481	}
4482
4483
4484	/*
4485	* remove port
4486	*/
4487
4488	static void
4489	release_port(struct hfc_multi *hc, struct dchannel *dch)
4490	{
4491	int pt, ci, i = 0;
4492	u_long flags;
4493	struct bchannel *pb;
4494
4495	ci = dch->slot;
4496	pt = hc->chan[ci].port;
4497
4498	if (debug & DEBUG_HFCMULTI_INIT)
4499	printk(KERN_DEBUG "%s: entered for port %d\n",
4500	__func__, pt + 1);
4501
4502	if (pt >= hc->ports) {
4503	printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4504	__func__, pt + 1);
4505	return;
4506	}
4507
4508	if (debug & DEBUG_HFCMULTI_INIT)
4509	printk(KERN_DEBUG "%s: releasing port=%d\n",
4510	__func__, pt + 1);
4511
4512	if (dch->dev.D.protocol == ISDN_P_TE_S0)
4513	l1_event(dch->l1, CLOSE_CHANNEL);
4514
4515	hc->chan[ci].dch = NULL;
4516
4517	if (hc->created[pt]) {
4518	hc->created[pt] = 0;
4519	mISDN_unregister_device(&dch->dev);
4520	}
4521
4522	spin_lock_irqsave(&hc->lock, flags);
4523
4524	if (dch->timer.function) {
4525	timer_delete(timer: &dch->timer);
4526	dch->timer.function = NULL;
4527	}
4528
4529	if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4530	/* remove sync */
4531	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4532	hc->syncronized = 0;
4533	plxsd_checksync(hc, rm: 1);
4534	}
4535	/* free channels */
4536	for (i = 0; i <= 31; i++) {
4537	if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4538	continue;
4539	if (hc->chan[i].bch) {
4540	if (debug & DEBUG_HFCMULTI_INIT)
4541	printk(KERN_DEBUG
4542	"%s: free port %d channel %d\n",
4543	__func__, hc->chan[i].port + 1, i);
4544	pb = hc->chan[i].bch;
4545	hc->chan[i].bch = NULL;
4546	spin_unlock_irqrestore(lock: &hc->lock, flags);
4547	mISDN_freebchannel(pb);
4548	kfree(objp: pb);
4549	kfree(objp: hc->chan[i].coeff);
4550	spin_lock_irqsave(&hc->lock, flags);
4551	}
4552	}
4553	} else {
4554	/* remove sync */
4555	if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4556	hc->syncronized &=
4557	~(1 << hc->chan[ci].port);
4558	plxsd_checksync(hc, rm: 1);
4559	}
4560	/* free channels */
4561	if (hc->chan[ci - 2].bch) {
4562	if (debug & DEBUG_HFCMULTI_INIT)
4563	printk(KERN_DEBUG
4564	"%s: free port %d channel %d\n",
4565	__func__, hc->chan[ci - 2].port + 1,
4566	ci - 2);
4567	pb = hc->chan[ci - 2].bch;
4568	hc->chan[ci - 2].bch = NULL;
4569	spin_unlock_irqrestore(lock: &hc->lock, flags);
4570	mISDN_freebchannel(pb);
4571	kfree(objp: pb);
4572	kfree(objp: hc->chan[ci - 2].coeff);
4573	spin_lock_irqsave(&hc->lock, flags);
4574	}
4575	if (hc->chan[ci - 1].bch) {
4576	if (debug & DEBUG_HFCMULTI_INIT)
4577	printk(KERN_DEBUG
4578	"%s: free port %d channel %d\n",
4579	__func__, hc->chan[ci - 1].port + 1,
4580	ci - 1);
4581	pb = hc->chan[ci - 1].bch;
4582	hc->chan[ci - 1].bch = NULL;
4583	spin_unlock_irqrestore(lock: &hc->lock, flags);
4584	mISDN_freebchannel(pb);
4585	kfree(objp: pb);
4586	kfree(objp: hc->chan[ci - 1].coeff);
4587	spin_lock_irqsave(&hc->lock, flags);
4588	}
4589	}
4590
4591	spin_unlock_irqrestore(lock: &hc->lock, flags);
4592
4593	if (debug & DEBUG_HFCMULTI_INIT)
4594	printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4595	pt+1, ci);
4596	mISDN_freedchannel(dch);
4597	kfree(objp: dch);
4598
4599	if (debug & DEBUG_HFCMULTI_INIT)
4600	printk(KERN_DEBUG "%s: done!\n", __func__);
4601	}
4602
4603	static void
4604	release_card(struct hfc_multi *hc)
4605	{
4606	u_long flags;
4607	int ch;
4608
4609	if (debug & DEBUG_HFCMULTI_INIT)
4610	printk(KERN_DEBUG "%s: release card (%d) entered\n",
4611	__func__, hc->id);
4612
4613	/* unregister clock source */
4614	if (hc->iclock)
4615	mISDN_unregister_clock(hc->iclock);
4616
4617	/* disable and free irq */
4618	spin_lock_irqsave(&hc->lock, flags);
4619	disable_hwirq(hc);
4620	spin_unlock_irqrestore(lock: &hc->lock, flags);
4621	udelay(usec: 1000);
4622	if (hc->irq) {
4623	if (debug & DEBUG_HFCMULTI_INIT)
4624	printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4625	__func__, hc->irq, hc);
4626	free_irq(hc->irq, hc);
4627	hc->irq = 0;
4628
4629	}
4630
4631	/* disable D-channels & B-channels */
4632	if (debug & DEBUG_HFCMULTI_INIT)
4633	printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4634	__func__);
4635	for (ch = 0; ch <= 31; ch++) {
4636	if (hc->chan[ch].dch)
4637	release_port(hc, dch: hc->chan[ch].dch);
4638	}
4639
4640	/* dimm leds */
4641	if (hc->leds)
4642	hfcmulti_leds(hc);
4643
4644	/* release hardware */
4645	release_io_hfcmulti(hc);
4646
4647	if (debug & DEBUG_HFCMULTI_INIT)
4648	printk(KERN_DEBUG "%s: remove instance from list\n",
4649	__func__);
4650	list_del(entry: &hc->list);
4651
4652	if (debug & DEBUG_HFCMULTI_INIT)
4653	printk(KERN_DEBUG "%s: delete instance\n", __func__);
4654	if (hc == syncmaster)
4655	syncmaster = NULL;
4656	kfree(objp: hc);
4657	if (debug & DEBUG_HFCMULTI_INIT)
4658	printk(KERN_DEBUG "%s: card successfully removed\n",
4659	__func__);
4660	}
4661
4662	static void
4663	init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4664	{
4665	/* set optical line type */
4666	if (port[Port_cnt] & 0x001) {
4667	if (!m->opticalsupport) {
4668	printk(KERN_INFO
4669	"This board has no optical "
4670	"support\n");
4671	} else {
4672	if (debug & DEBUG_HFCMULTI_INIT)
4673	printk(KERN_DEBUG
4674	"%s: PORT set optical "
4675	"interface: card(%d) "
4676	"port(%d)\n",
4677	__func__,
4678	HFC_cnt + 1, 1);
4679	test_and_set_bit(HFC_CFG_OPTICAL,
4680	addr: &hc->chan[hc->dnum[0]].cfg);
4681	}
4682	}
4683	/* set LOS report */
4684	if (port[Port_cnt] & 0x004) {
4685	if (debug & DEBUG_HFCMULTI_INIT)
4686	printk(KERN_DEBUG "%s: PORT set "
4687	"LOS report: card(%d) port(%d)\n",
4688	__func__, HFC_cnt + 1, 1);
4689	test_and_set_bit(HFC_CFG_REPORT_LOS,
4690	addr: &hc->chan[hc->dnum[0]].cfg);
4691	}
4692	/* set AIS report */
4693	if (port[Port_cnt] & 0x008) {
4694	if (debug & DEBUG_HFCMULTI_INIT)
4695	printk(KERN_DEBUG "%s: PORT set "
4696	"AIS report: card(%d) port(%d)\n",
4697	__func__, HFC_cnt + 1, 1);
4698	test_and_set_bit(HFC_CFG_REPORT_AIS,
4699	addr: &hc->chan[hc->dnum[0]].cfg);
4700	}
4701	/* set SLIP report */
4702	if (port[Port_cnt] & 0x010) {
4703	if (debug & DEBUG_HFCMULTI_INIT)
4704	printk(KERN_DEBUG
4705	"%s: PORT set SLIP report: "
4706	"card(%d) port(%d)\n",
4707	__func__, HFC_cnt + 1, 1);
4708	test_and_set_bit(HFC_CFG_REPORT_SLIP,
4709	addr: &hc->chan[hc->dnum[0]].cfg);
4710	}
4711	/* set RDI report */
4712	if (port[Port_cnt] & 0x020) {
4713	if (debug & DEBUG_HFCMULTI_INIT)
4714	printk(KERN_DEBUG
4715	"%s: PORT set RDI report: "
4716	"card(%d) port(%d)\n",
4717	__func__, HFC_cnt + 1, 1);
4718	test_and_set_bit(HFC_CFG_REPORT_RDI,
4719	addr: &hc->chan[hc->dnum[0]].cfg);
4720	}
4721	/* set CRC-4 Mode */
4722	if (!(port[Port_cnt] & 0x100)) {
4723	if (debug & DEBUG_HFCMULTI_INIT)
4724	printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4725	" card(%d) port(%d)\n",
4726	__func__, HFC_cnt + 1, 1);
4727	test_and_set_bit(HFC_CFG_CRC4,
4728	addr: &hc->chan[hc->dnum[0]].cfg);
4729	} else {
4730	if (debug & DEBUG_HFCMULTI_INIT)
4731	printk(KERN_DEBUG "%s: PORT turn off CRC4"
4732	" report: card(%d) port(%d)\n",
4733	__func__, HFC_cnt + 1, 1);
4734	}
4735	/* set forced clock */
4736	if (port[Port_cnt] & 0x0200) {
4737	if (debug & DEBUG_HFCMULTI_INIT)
4738	printk(KERN_DEBUG "%s: PORT force getting clock from "
4739	"E1: card(%d) port(%d)\n",
4740	__func__, HFC_cnt + 1, 1);
4741	test_and_set_bit(HFC_CHIP_E1CLOCK_GET, addr: &hc->chip);
4742	} else
4743	if (port[Port_cnt] & 0x0400) {
4744	if (debug & DEBUG_HFCMULTI_INIT)
4745	printk(KERN_DEBUG "%s: PORT force putting clock to "
4746	"E1: card(%d) port(%d)\n",
4747	__func__, HFC_cnt + 1, 1);
4748	test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, addr: &hc->chip);
4749	}
4750	/* set JATT PLL */
4751	if (port[Port_cnt] & 0x0800) {
4752	if (debug & DEBUG_HFCMULTI_INIT)
4753	printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4754	"E1: card(%d) port(%d)\n",
4755	__func__, HFC_cnt + 1, 1);
4756	test_and_set_bit(HFC_CHIP_RX_SYNC, addr: &hc->chip);
4757	}
4758	/* set elastic jitter buffer */
4759	if (port[Port_cnt] & 0x3000) {
4760	hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4761	if (debug & DEBUG_HFCMULTI_INIT)
4762	printk(KERN_DEBUG
4763	"%s: PORT set elastic "
4764	"buffer to %d: card(%d) port(%d)\n",
4765	__func__, hc->chan[hc->dnum[0]].jitter,
4766	HFC_cnt + 1, 1);
4767	} else
4768	hc->chan[hc->dnum[0]].jitter = 2; /* default */
4769	}
4770
4771	static int
4772	init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4773	{
4774	struct dchannel *dch;
4775	struct bchannel *bch;
4776	int ch, ret = 0;
4777	char name[MISDN_MAX_IDLEN];
4778	int bcount = 0;
4779
4780	dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4781	if (!dch)
4782	return -ENOMEM;
4783	dch->debug = debug;
4784	mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4785	dch->hw = hc;
4786	dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4787	dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4788	(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4789	dch->dev.D.send = handle_dmsg;
4790	dch->dev.D.ctrl = hfcm_dctrl;
4791	dch->slot = hc->dnum[pt];
4792	hc->chan[hc->dnum[pt]].dch = dch;
4793	hc->chan[hc->dnum[pt]].port = pt;
4794	hc->chan[hc->dnum[pt]].nt_timer = -1;
4795	for (ch = 1; ch <= 31; ch++) {
4796	if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4797	continue;
4798	bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4799	if (!bch) {
4800	printk(KERN_ERR "%s: no memory for bchannel\n",
4801	__func__);
4802	ret = -ENOMEM;
4803	goto free_chan;
4804	}
4805	hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4806	if (!hc->chan[ch].coeff) {
4807	printk(KERN_ERR "%s: no memory for coeffs\n",
4808	__func__);
4809	ret = -ENOMEM;
4810	kfree(objp: bch);
4811	goto free_chan;
4812	}
4813	bch->nr = ch;
4814	bch->slot = ch;
4815	bch->debug = debug;
4816	mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4817	bch->hw = hc;
4818	bch->ch.send = handle_bmsg;
4819	bch->ch.ctrl = hfcm_bctrl;
4820	bch->ch.nr = ch;
4821	list_add(new: &bch->ch.list, head: &dch->dev.bchannels);
4822	hc->chan[ch].bch = bch;
4823	hc->chan[ch].port = pt;
4824	set_channelmap(nr: bch->nr, map: dch->dev.channelmap);
4825	bcount++;
4826	}
4827	dch->dev.nrbchan = bcount;
4828	if (pt == 0)
4829	init_e1_port_hw(hc, m);
4830	if (hc->ports > 1)
4831	snprintf(buf: name, MISDN_MAX_IDLEN - 1, fmt: "hfc-e1.%d-%d",
4832	HFC_cnt + 1, pt+1);
4833	else
4834	snprintf(buf: name, MISDN_MAX_IDLEN - 1, fmt: "hfc-e1.%d", HFC_cnt + 1);
4835	ret = mISDN_register_device(&dch->dev, parent: &hc->pci_dev->dev, name);
4836	if (ret)
4837	goto free_chan;
4838	hc->created[pt] = 1;
4839	return ret;
4840	free_chan:
4841	release_port(hc, dch);
4842	return ret;
4843	}
4844
4845	static int
4846	init_multi_port(struct hfc_multi *hc, int pt)
4847	{
4848	struct dchannel *dch;
4849	struct bchannel *bch;
4850	int ch, i, ret = 0;
4851	char name[MISDN_MAX_IDLEN];
4852
4853	dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4854	if (!dch)
4855	return -ENOMEM;
4856	dch->debug = debug;
4857	mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4858	dch->hw = hc;
4859	dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4860	dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4861	(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4862	dch->dev.D.send = handle_dmsg;
4863	dch->dev.D.ctrl = hfcm_dctrl;
4864	dch->dev.nrbchan = 2;
4865	i = pt << 2;
4866	dch->slot = i + 2;
4867	hc->chan[i + 2].dch = dch;
4868	hc->chan[i + 2].port = pt;
4869	hc->chan[i + 2].nt_timer = -1;
4870	for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4871	bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4872	if (!bch) {
4873	printk(KERN_ERR "%s: no memory for bchannel\n",
4874	__func__);
4875	ret = -ENOMEM;
4876	goto free_chan;
4877	}
4878	hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4879	if (!hc->chan[i + ch].coeff) {
4880	printk(KERN_ERR "%s: no memory for coeffs\n",
4881	__func__);
4882	ret = -ENOMEM;
4883	kfree(objp: bch);
4884	goto free_chan;
4885	}
4886	bch->nr = ch + 1;
4887	bch->slot = i + ch;
4888	bch->debug = debug;
4889	mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4890	bch->hw = hc;
4891	bch->ch.send = handle_bmsg;
4892	bch->ch.ctrl = hfcm_bctrl;
4893	bch->ch.nr = ch + 1;
4894	list_add(new: &bch->ch.list, head: &dch->dev.bchannels);
4895	hc->chan[i + ch].bch = bch;
4896	hc->chan[i + ch].port = pt;
4897	set_channelmap(nr: bch->nr, map: dch->dev.channelmap);
4898	}
4899	/* set master clock */
4900	if (port[Port_cnt] & 0x001) {
4901	if (debug & DEBUG_HFCMULTI_INIT)
4902	printk(KERN_DEBUG
4903	"%s: PROTOCOL set master clock: "
4904	"card(%d) port(%d)\n",
4905	__func__, HFC_cnt + 1, pt + 1);
4906	if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4907	printk(KERN_ERR "Error: Master clock "
4908	"for port(%d) of card(%d) is only"
4909	" possible with TE-mode\n",
4910	pt + 1, HFC_cnt + 1);
4911	ret = -EINVAL;
4912	goto free_chan;
4913	}
4914	if (hc->masterclk >= 0) {
4915	printk(KERN_ERR "Error: Master clock "
4916	"for port(%d) of card(%d) already "
4917	"defined for port(%d)\n",
4918	pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4919	ret = -EINVAL;
4920	goto free_chan;
4921	}
4922	hc->masterclk = pt;
4923	}
4924	/* set transmitter line to non capacitive */
4925	if (port[Port_cnt] & 0x002) {
4926	if (debug & DEBUG_HFCMULTI_INIT)
4927	printk(KERN_DEBUG
4928	"%s: PROTOCOL set non capacitive "
4929	"transmitter: card(%d) port(%d)\n",
4930	__func__, HFC_cnt + 1, pt + 1);
4931	test_and_set_bit(HFC_CFG_NONCAP_TX,
4932	addr: &hc->chan[i + 2].cfg);
4933	}
4934	/* disable E-channel */
4935	if (port[Port_cnt] & 0x004) {
4936	if (debug & DEBUG_HFCMULTI_INIT)
4937	printk(KERN_DEBUG
4938	"%s: PROTOCOL disable E-channel: "
4939	"card(%d) port(%d)\n",
4940	__func__, HFC_cnt + 1, pt + 1);
4941	test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4942	addr: &hc->chan[i + 2].cfg);
4943	}
4944	if (hc->ctype == HFC_TYPE_XHFC) {
4945	snprintf(buf: name, MISDN_MAX_IDLEN - 1, fmt: "xhfc.%d-%d",
4946	HFC_cnt + 1, pt + 1);
4947	ret = mISDN_register_device(&dch->dev, NULL, name);
4948	} else {
4949	snprintf(buf: name, MISDN_MAX_IDLEN - 1, fmt: "hfc-%ds.%d-%d",
4950	hc->ctype, HFC_cnt + 1, pt + 1);
4951	ret = mISDN_register_device(&dch->dev, parent: &hc->pci_dev->dev, name);
4952	}
4953	if (ret)
4954	goto free_chan;
4955	hc->created[pt] = 1;
4956	return ret;
4957	free_chan:
4958	release_port(hc, dch);
4959	return ret;
4960	}
4961
4962	static int
4963	hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4964	const struct pci_device_id *ent)
4965	{
4966	int ret_err = 0;
4967	int pt;
4968	struct hfc_multi *hc;
4969	u_long flags;
4970	u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4971	int i, ch;
4972	u_int maskcheck;
4973
4974	if (HFC_cnt >= MAX_CARDS) {
4975	printk(KERN_ERR "too many cards (max=%d).\n",
4976	MAX_CARDS);
4977	return -EINVAL;
4978	}
4979	if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4980	printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4981	"type[%d] %d was supplied as module parameter\n",
4982	m->vendor_name, m->card_name, m->type, HFC_cnt,
4983	type[HFC_cnt] & 0xff);
4984	printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4985	"first, to see cards and their types.");
4986	return -EINVAL;
4987	}
4988	if (debug & DEBUG_HFCMULTI_INIT)
4989	printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4990	__func__, m->vendor_name, m->card_name, m->type,
4991	type[HFC_cnt]);
4992
4993	/* allocate card+fifo structure */
4994	hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4995	if (!hc) {
4996	printk(KERN_ERR "No kmem for HFC-Multi card\n");
4997	return -ENOMEM;
4998	}
4999	spin_lock_init(&hc->lock);
5000	hc->mtyp = m;
5001	hc->ctype = m->type;
5002	hc->ports = m->ports;
5003	hc->id = HFC_cnt;
5004	hc->pcm = pcm[HFC_cnt];
5005	hc->io_mode = iomode[HFC_cnt];
5006	if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5007	/* fragment card */
5008	pt = 0;
5009	maskcheck = 0;
5010	for (ch = 0; ch <= 31; ch++) {
5011	if (!((1 << ch) & dmask[E1_cnt]))
5012	continue;
5013	hc->dnum[pt] = ch;
5014	hc->bmask[pt] = bmask[bmask_cnt++];
5015	if ((maskcheck & hc->bmask[pt])
5016	|| (dmask[E1_cnt] & hc->bmask[pt])) {
5017	printk(KERN_INFO
5018	"HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5019	E1_cnt + 1, pt);
5020	kfree(objp: hc);
5021	return -EINVAL;
5022	}
5023	maskcheck |= hc->bmask[pt];
5024	printk(KERN_INFO
5025	"HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5026	E1_cnt + 1, ch, hc->bmask[pt]);
5027	pt++;
5028	}
5029	hc->ports = pt;
5030	}
5031	if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5032	/* default card layout */
5033	hc->dnum[0] = 16;
5034	hc->bmask[0] = 0xfffefffe;
5035	hc->ports = 1;
5036	}
5037
5038	/* set chip specific features */
5039	hc->masterclk = -1;
5040	if (type[HFC_cnt] & 0x100) {
5041	test_and_set_bit(HFC_CHIP_ULAW, addr: &hc->chip);
5042	hc->silence = 0xff; /* ulaw silence */
5043	} else
5044	hc->silence = 0x2a; /* alaw silence */
5045	if ((poll >> 1) > sizeof(hc->silence_data)) {
5046	printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5047	"please fix\n");
5048	kfree(objp: hc);
5049	return -EINVAL;
5050	}
5051	for (i = 0; i < (poll >> 1); i++)
5052	hc->silence_data[i] = hc->silence;
5053
5054	if (hc->ctype != HFC_TYPE_XHFC) {
5055	if (!(type[HFC_cnt] & 0x200))
5056	test_and_set_bit(HFC_CHIP_DTMF, addr: &hc->chip);
5057	test_and_set_bit(HFC_CHIP_CONF, addr: &hc->chip);
5058	}
5059
5060	if (type[HFC_cnt] & 0x800)
5061	test_and_set_bit(HFC_CHIP_PCM_SLAVE, addr: &hc->chip);
5062	if (type[HFC_cnt] & 0x1000) {
5063	test_and_set_bit(HFC_CHIP_PCM_MASTER, addr: &hc->chip);
5064	test_and_clear_bit(HFC_CHIP_PCM_SLAVE, addr: &hc->chip);
5065	}
5066	if (type[HFC_cnt] & 0x4000)
5067	test_and_set_bit(HFC_CHIP_EXRAM_128, addr: &hc->chip);
5068	if (type[HFC_cnt] & 0x8000)
5069	test_and_set_bit(HFC_CHIP_EXRAM_512, addr: &hc->chip);
5070	hc->slots = 32;
5071	if (type[HFC_cnt] & 0x10000)
5072	hc->slots = 64;
5073	if (type[HFC_cnt] & 0x20000)
5074	hc->slots = 128;
5075	if (type[HFC_cnt] & 0x80000) {
5076	test_and_set_bit(HFC_CHIP_WATCHDOG, addr: &hc->chip);
5077	hc->wdcount = 0;
5078	hc->wdbyte = V_GPIO_OUT2;
5079	printk(KERN_NOTICE "Watchdog enabled\n");
5080	}
5081
5082	if (pdev && ent)
5083	/* setup pci, hc->slots may change due to PLXSD */
5084	ret_err = setup_pci(hc, pdev, ent);
5085	else
5086	#ifdef CONFIG_MISDN_HFCMULTI_8xx
5087	ret_err = setup_embedded(hc, m);
5088	#else
5089	{
5090	printk(KERN_WARNING "Embedded IO Mode not selected\n");
5091	ret_err = -EIO;
5092	}
5093	#endif
5094	if (ret_err) {
5095	if (hc == syncmaster)
5096	syncmaster = NULL;
5097	kfree(objp: hc);
5098	return ret_err;
5099	}
5100
5101	hc->HFC_outb_nodebug = hc->HFC_outb;
5102	hc->HFC_inb_nodebug = hc->HFC_inb;
5103	hc->HFC_inw_nodebug = hc->HFC_inw;
5104	hc->HFC_wait_nodebug = hc->HFC_wait;
5105	#ifdef HFC_REGISTER_DEBUG
5106	hc->HFC_outb = HFC_outb_debug;
5107	hc->HFC_inb = HFC_inb_debug;
5108	hc->HFC_inw = HFC_inw_debug;
5109	hc->HFC_wait = HFC_wait_debug;
5110	#endif
5111	/* create channels */
5112	for (pt = 0; pt < hc->ports; pt++) {
5113	if (Port_cnt >= MAX_PORTS) {
5114	printk(KERN_ERR "too many ports (max=%d).\n",
5115	MAX_PORTS);
5116	ret_err = -EINVAL;
5117	goto free_card;
5118	}
5119	if (hc->ctype == HFC_TYPE_E1)
5120	ret_err = init_e1_port(hc, m, pt);
5121	else
5122	ret_err = init_multi_port(hc, pt);
5123	if (debug & DEBUG_HFCMULTI_INIT)
5124	printk(KERN_DEBUG
5125	"%s: Registering D-channel, card(%d) port(%d) "
5126	"result %d\n",
5127	__func__, HFC_cnt + 1, pt + 1, ret_err);
5128
5129	if (ret_err) {
5130	while (pt) { /* release already registered ports */
5131	pt--;
5132	if (hc->ctype == HFC_TYPE_E1)
5133	release_port(hc,
5134	dch: hc->chan[hc->dnum[pt]].dch);
5135	else
5136	release_port(hc,
5137	dch: hc->chan[(pt << 2) + 2].dch);
5138	}
5139	goto free_card;
5140	}
5141	if (hc->ctype != HFC_TYPE_E1)
5142	Port_cnt++; /* for each S0 port */
5143	}
5144	if (hc->ctype == HFC_TYPE_E1) {
5145	Port_cnt++; /* for each E1 port */
5146	E1_cnt++;
5147	}
5148
5149	/* disp switches */
5150	switch (m->dip_type) {
5151	case DIP_4S:
5152	/*
5153	* Get DIP setting for beroNet 1S/2S/4S cards
5154	* DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5155	* GPI 19/23 (R_GPI_IN2))
5156	*/
5157	dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5158	((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5159	(~HFC_inb(hc, R_GPI_IN2) & 0x08);
5160
5161	/* Port mode (TE/NT) jumpers */
5162	pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5163
5164	if (test_bit(HFC_CHIP_B410P, &hc->chip))
5165	pmj = ~pmj & 0xf;
5166
5167	printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5168	m->vendor_name, m->card_name, dips, pmj);
5169	break;
5170	case DIP_8S:
5171	/*
5172	* Get DIP Setting for beroNet 8S0+ cards
5173	* Enable PCI auxbridge function
5174	*/
5175	HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5176	/* prepare access to auxport */
5177	outw(value: 0x4000, port: hc->pci_iobase + 4);
5178	/*
5179	* some dummy reads are required to
5180	* read valid DIP switch data
5181	*/
5182	dips = inb(port: hc->pci_iobase);
5183	dips = inb(port: hc->pci_iobase);
5184	dips = inb(port: hc->pci_iobase);
5185	dips = ~inb(port: hc->pci_iobase) & 0x3F;
5186	outw(value: 0x0, port: hc->pci_iobase + 4);
5187	/* disable PCI auxbridge function */
5188	HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5189	printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5190	m->vendor_name, m->card_name, dips);
5191	break;
5192	case DIP_E1:
5193	/*
5194	* get DIP Setting for beroNet E1 cards
5195	* DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5196	*/
5197	dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5198	printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5199	m->vendor_name, m->card_name, dips);
5200	break;
5201	}
5202
5203	/* add to list */
5204	spin_lock_irqsave(&HFClock, flags);
5205	list_add_tail(new: &hc->list, head: &HFClist);
5206	spin_unlock_irqrestore(lock: &HFClock, flags);
5207
5208	/* use as clock source */
5209	if (clock == HFC_cnt + 1)
5210	hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5211
5212	/* initialize hardware */
5213	hc->irq = (m->irq) ? : hc->pci_dev->irq;
5214	ret_err = init_card(hc);
5215	if (ret_err) {
5216	printk(KERN_ERR "init card returns %d\n", ret_err);
5217	release_card(hc);
5218	return ret_err;
5219	}
5220
5221	/* start IRQ and return */
5222	spin_lock_irqsave(&hc->lock, flags);
5223	enable_hwirq(hc);
5224	spin_unlock_irqrestore(lock: &hc->lock, flags);
5225	return 0;
5226
5227	free_card:
5228	release_io_hfcmulti(hc);
5229	if (hc == syncmaster)
5230	syncmaster = NULL;
5231	kfree(objp: hc);
5232	return ret_err;
5233	}
5234
5235	static void hfc_remove_pci(struct pci_dev *pdev)
5236	{
5237	struct hfc_multi *card = pci_get_drvdata(pdev);
5238	u_long flags;
5239
5240	if (debug)
5241	printk(KERN_INFO "removing hfc_multi card vendor:%x "
5242	"device:%x subvendor:%x subdevice:%x\n",
5243	pdev->vendor, pdev->device,
5244	pdev->subsystem_vendor, pdev->subsystem_device);
5245
5246	if (card) {
5247	spin_lock_irqsave(&HFClock, flags);
5248	release_card(hc: card);
5249	spin_unlock_irqrestore(lock: &HFClock, flags);
5250	} else {
5251	if (debug)
5252	printk(KERN_DEBUG "%s: drvdata already removed\n",
5253	__func__);
5254	}
5255	}
5256
5257	#define VENDOR_CCD "Cologne Chip AG"
5258	#define VENDOR_BN "beroNet GmbH"
5259	#define VENDOR_DIG "Digium Inc."
5260	#define VENDOR_JH "Junghanns.NET GmbH"
5261	#define VENDOR_PRIM "PrimuX"
5262
5263	static const struct hm_map hfcm_map[] = {
5264	/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5265	/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5266	/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5267	/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5268	/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5269	/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5270	/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5271	/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5272	/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5273	/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5274	/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5275	/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5276
5277	/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5278	/*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5279	HFC_IO_MODE_REGIO, 0},
5280	/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5281	/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5282
5283	/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5284	/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5285	/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5286
5287	/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5288	/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5289	/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5290	/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5291
5292	/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5293	/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5294	/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5295
5296	/*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5297	HFC_IO_MODE_PLXSD, 0},
5298	/*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5299	HFC_IO_MODE_PLXSD, 0},
5300	/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5301	/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5302	/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5303	/*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5304	HFC_IO_MODE_EMBSD, XHFC_IRQ},
5305	/*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5306	/*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5307	/*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5308	};
5309
5310	#undef H
5311	#define H(x) ((unsigned long)&hfcm_map[x])
5312	static const struct pci_device_id hfmultipci_ids[] = {
5313
5314	/* Cards with HFC-4S Chip */
5315	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5316	PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5317	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5318	PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5319	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5320	PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5321	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5322	PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5323	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5324	PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5325	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5326	PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5327	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5328	PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5329	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5330	PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5331	{ PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5332	PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5333	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5334	PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5335	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5336	PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5337	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5338	PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5339	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5340	PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5341	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5342	PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5343	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5344	0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5345	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5346	0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5347
5348	/* Cards with HFC-8S Chip */
5349	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5350	PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5351	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5352	PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5353	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5354	PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5355	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5356	PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5357	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5358	PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5359	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5360	PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5361	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5362	PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5363	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5364	PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5365	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5366	PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5367
5368
5369	/* Cards with HFC-E1 Chip */
5370	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5371	PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5372	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5373	PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5374	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5375	PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5376	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5377	PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5378
5379	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5380	PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5381	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5382	PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5383	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5384	PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5385
5386	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5387	PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5388	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5389	PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5390
5391	{ PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5392	PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5393
5394	{ PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5395	{ PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5396	{ PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5397	{0, }
5398	};
5399	#undef H
5400
5401	MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5402
5403	static int
5404	hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5405	{
5406	struct hm_map *m = (struct hm_map *)ent->driver_data;
5407	int ret;
5408
5409	if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5410	ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5411	ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5412	ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5413	printk(KERN_ERR
5414	"Unknown HFC multiport controller (vendor:%04x device:%04x "
5415	"subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5416	pdev->device, pdev->subsystem_vendor,
5417	pdev->subsystem_device);
5418	printk(KERN_ERR
5419	"Please contact the driver maintainer for support.\n");
5420	return -ENODEV;
5421	}
5422	ret = hfcmulti_init(m, pdev, ent);
5423	if (ret)
5424	return ret;
5425	HFC_cnt++;
5426	printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5427	return 0;
5428	}
5429
5430	static struct pci_driver hfcmultipci_driver = {
5431	.name = "hfc_multi",
5432	.probe = hfcmulti_probe,
5433	.remove = hfc_remove_pci,
5434	.id_table = hfmultipci_ids,
5435	};
5436
5437	static void __exit
5438	HFCmulti_cleanup(void)
5439	{
5440	struct hfc_multi *card, *next;
5441
5442	/* get rid of all devices of this driver */
5443	list_for_each_entry_safe(card, next, &HFClist, list)
5444	release_card(hc: card);
5445	pci_unregister_driver(dev: &hfcmultipci_driver);
5446	}
5447
5448	static int __init
5449	HFCmulti_init(void)
5450	{
5451	int err;
5452	int i, xhfc = 0;
5453	struct hm_map m;
5454
5455	printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5456
5457	#ifdef IRQ_DEBUG
5458	printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5459	#endif
5460
5461	if (debug & DEBUG_HFCMULTI_INIT)
5462	printk(KERN_DEBUG "%s: init entered\n", __func__);
5463
5464	switch (poll) {
5465	case 0:
5466	poll_timer = 6;
5467	poll = 128;
5468	break;
5469	case 8:
5470	poll_timer = 2;
5471	break;
5472	case 16:
5473	poll_timer = 3;
5474	break;
5475	case 32:
5476	poll_timer = 4;
5477	break;
5478	case 64:
5479	poll_timer = 5;
5480	break;
5481	case 128:
5482	poll_timer = 6;
5483	break;
5484	case 256:
5485	poll_timer = 7;
5486	break;
5487	default:
5488	printk(KERN_ERR
5489	"%s: Wrong poll value (%d).\n", __func__, poll);
5490	err = -EINVAL;
5491	return err;
5492
5493	}
5494
5495	if (!clock)
5496	clock = 1;
5497
5498	/* Register the embedded devices.
5499	* This should be done before the PCI cards registration */
5500	switch (hwid) {
5501	case HWID_MINIP4:
5502	xhfc = 1;
5503	m = hfcm_map[31];
5504	break;
5505	case HWID_MINIP8:
5506	xhfc = 2;
5507	m = hfcm_map[31];
5508	break;
5509	case HWID_MINIP16:
5510	xhfc = 4;
5511	m = hfcm_map[31];
5512	break;
5513	default:
5514	xhfc = 0;
5515	}
5516
5517	for (i = 0; i < xhfc; ++i) {
5518	err = hfcmulti_init(m: &m, NULL, NULL);
5519	if (err) {
5520	printk(KERN_ERR "error registering embedded driver: "
5521	"%x\n", err);
5522	return err;
5523	}
5524	HFC_cnt++;
5525	printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5526	}
5527
5528	/* Register the PCI cards */
5529	err = pci_register_driver(&hfcmultipci_driver);
5530	if (err < 0) {
5531	printk(KERN_ERR "error registering pci driver: %x\n", err);
5532	return err;
5533	}
5534
5535	return 0;
5536	}
5537
5538
5539	module_init(HFCmulti_init);
5540	module_exit(HFCmulti_cleanup);
5541