1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <linux/clk.h>
8#include <linux/interrupt.h>
9#include <linux/irq.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/irqdomain.h>
12#include <linux/kernel.h>
13#include <linux/of.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/spinlock.h>
18
19#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
20#define CHANCTRL 0x0
21#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
22#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
23#define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
24#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
25#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
26
27#define CHAN_MAX_OUTPUT_INT 0xF
28
29struct irqsteer_data {
30 void __iomem *regs;
31 struct clk *ipg_clk;
32 int irq[CHAN_MAX_OUTPUT_INT];
33 int irq_count;
34 raw_spinlock_t lock;
35 int reg_num;
36 int channel;
37 struct irq_domain *domain;
38 u32 *saved_reg;
39 struct device *dev;
40};
41
42static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
43 unsigned long irqnum)
44{
45 return (data->reg_num - irqnum / 32 - 1);
46}
47
48static void imx_irqsteer_irq_unmask(struct irq_data *d)
49{
50 struct irqsteer_data *data = d->chip_data;
51 int idx = imx_irqsteer_get_reg_index(data, irqnum: d->hwirq);
52 unsigned long flags;
53 u32 val;
54
55 raw_spin_lock_irqsave(&data->lock, flags);
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
57 val |= BIT(d->hwirq % 32);
58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
59 raw_spin_unlock_irqrestore(&data->lock, flags);
60}
61
62static void imx_irqsteer_irq_mask(struct irq_data *d)
63{
64 struct irqsteer_data *data = d->chip_data;
65 int idx = imx_irqsteer_get_reg_index(data, irqnum: d->hwirq);
66 unsigned long flags;
67 u32 val;
68
69 raw_spin_lock_irqsave(&data->lock, flags);
70 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
71 val &= ~BIT(d->hwirq % 32);
72 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
73 raw_spin_unlock_irqrestore(&data->lock, flags);
74}
75
76static void imx_irqsteer_irq_bus_lock(struct irq_data *d)
77{
78 struct irqsteer_data *data = d->chip_data;
79
80 pm_runtime_get_sync(dev: data->dev);
81}
82
83static void imx_irqsteer_irq_bus_sync_unlock(struct irq_data *d)
84{
85 struct irqsteer_data *data = d->chip_data;
86
87 pm_runtime_put_autosuspend(dev: data->dev);
88}
89
90static const struct irq_chip imx_irqsteer_irq_chip = {
91 .name = "irqsteer",
92 .irq_mask = imx_irqsteer_irq_mask,
93 .irq_unmask = imx_irqsteer_irq_unmask,
94 .irq_bus_lock = imx_irqsteer_irq_bus_lock,
95 .irq_bus_sync_unlock = imx_irqsteer_irq_bus_sync_unlock,
96};
97
98static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
99 irq_hw_number_t hwirq)
100{
101 irq_set_status_flags(irq, set: IRQ_LEVEL);
102 irq_set_chip_data(irq, data: h->host_data);
103 irq_set_chip_and_handler(irq, chip: &imx_irqsteer_irq_chip, handle: handle_level_irq);
104
105 return 0;
106}
107
108static const struct irq_domain_ops imx_irqsteer_domain_ops = {
109 .map = imx_irqsteer_irq_map,
110 .xlate = irq_domain_xlate_onecell,
111};
112
113static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
114{
115 int i;
116
117 for (i = 0; i < data->irq_count; i++) {
118 if (data->irq[i] == irq)
119 return i * 64;
120 }
121
122 return -EINVAL;
123}
124
125static void imx_irqsteer_irq_handler(struct irq_desc *desc)
126{
127 struct irqsteer_data *data = irq_desc_get_handler_data(desc);
128 int hwirq;
129 int irq, i;
130
131 chained_irq_enter(chip: irq_desc_get_chip(desc), desc);
132
133 irq = irq_desc_get_irq(desc);
134 hwirq = imx_irqsteer_get_hwirq_base(data, irq);
135 if (hwirq < 0) {
136 pr_warn("%s: unable to get hwirq base for irq %d\n",
137 __func__, irq);
138 return;
139 }
140
141 for (i = 0; i < 2; i++, hwirq += 32) {
142 int idx = imx_irqsteer_get_reg_index(data, irqnum: hwirq);
143 unsigned long irqmap;
144 int pos;
145
146 if (hwirq >= data->reg_num * 32)
147 break;
148
149 irqmap = readl_relaxed(data->regs +
150 CHANSTATUS(idx, data->reg_num));
151
152 for_each_set_bit(pos, &irqmap, 32)
153 generic_handle_domain_irq(domain: data->domain, hwirq: pos + hwirq);
154 }
155
156 chained_irq_exit(chip: irq_desc_get_chip(desc), desc);
157}
158
159static int imx_irqsteer_probe(struct platform_device *pdev)
160{
161 struct device_node *np = pdev->dev.of_node;
162 struct irqsteer_data *data;
163 u32 irqs_num;
164 int i, ret;
165
166 data = devm_kzalloc(dev: &pdev->dev, size: sizeof(*data), GFP_KERNEL);
167 if (!data)
168 return -ENOMEM;
169
170 data->dev = &pdev->dev;
171 data->regs = devm_platform_ioremap_resource(pdev, index: 0);
172 if (IS_ERR(ptr: data->regs)) {
173 dev_err(&pdev->dev, "failed to initialize reg\n");
174 return PTR_ERR(ptr: data->regs);
175 }
176
177 data->ipg_clk = devm_clk_get(dev: &pdev->dev, id: "ipg");
178 if (IS_ERR(ptr: data->ipg_clk))
179 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: data->ipg_clk),
180 fmt: "failed to get ipg clk\n");
181
182 raw_spin_lock_init(&data->lock);
183
184 ret = of_property_read_u32(np, propname: "fsl,num-irqs", out_value: &irqs_num);
185 if (ret)
186 return ret;
187 ret = of_property_read_u32(np, propname: "fsl,channel", out_value: &data->channel);
188 if (ret)
189 return ret;
190
191 /*
192 * There is one output irq for each group of 64 inputs.
193 * One register bit map can represent 32 input interrupts.
194 */
195 data->irq_count = DIV_ROUND_UP(irqs_num, 64);
196 data->reg_num = irqs_num / 32;
197
198 if (IS_ENABLED(CONFIG_PM)) {
199 data->saved_reg = devm_kzalloc(dev: &pdev->dev,
200 size: sizeof(u32) * data->reg_num,
201 GFP_KERNEL);
202 if (!data->saved_reg)
203 return -ENOMEM;
204 }
205
206 ret = clk_prepare_enable(clk: data->ipg_clk);
207 if (ret) {
208 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
209 return ret;
210 }
211
212 /* steer all IRQs into configured channel */
213 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
214
215 data->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), size: data->reg_num * 32,
216 ops: &imx_irqsteer_domain_ops, host_data: data);
217 if (!data->domain) {
218 dev_err(&pdev->dev, "failed to create IRQ domain\n");
219 ret = -ENOMEM;
220 goto out;
221 }
222 irq_domain_set_pm_device(d: data->domain, dev: &pdev->dev);
223
224 if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
225 ret = -EINVAL;
226 goto out;
227 }
228
229 for (i = 0; i < data->irq_count; i++) {
230 data->irq[i] = irq_of_parse_and_map(node: np, index: i);
231 if (!data->irq[i])
232 break;
233
234 irq_set_chained_handler_and_data(irq: data->irq[i],
235 handle: imx_irqsteer_irq_handler,
236 data);
237 }
238
239 platform_set_drvdata(pdev, data);
240
241 pm_runtime_set_active(dev: &pdev->dev);
242 pm_runtime_enable(dev: &pdev->dev);
243
244 return 0;
245out:
246 clk_disable_unprepare(clk: data->ipg_clk);
247 return ret;
248}
249
250static void imx_irqsteer_remove(struct platform_device *pdev)
251{
252 struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
253 int i;
254
255 for (i = 0; i < irqsteer_data->irq_count; i++) {
256 if (!irqsteer_data->irq[i])
257 break;
258
259 irq_set_chained_handler_and_data(irq: irqsteer_data->irq[i],
260 NULL, NULL);
261 }
262
263 irq_domain_remove(domain: irqsteer_data->domain);
264
265 clk_disable_unprepare(clk: irqsteer_data->ipg_clk);
266}
267
268#ifdef CONFIG_PM
269static void imx_irqsteer_save_regs(struct irqsteer_data *data)
270{
271 int i;
272
273 for (i = 0; i < data->reg_num; i++)
274 data->saved_reg[i] = readl_relaxed(data->regs +
275 CHANMASK(i, data->reg_num));
276}
277
278static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
279{
280 int i;
281
282 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
283 for (i = 0; i < data->reg_num; i++)
284 writel_relaxed(data->saved_reg[i],
285 data->regs + CHANMASK(i, data->reg_num));
286}
287
288static int imx_irqsteer_suspend(struct device *dev)
289{
290 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
291
292 imx_irqsteer_save_regs(data: irqsteer_data);
293 clk_disable_unprepare(clk: irqsteer_data->ipg_clk);
294
295 return 0;
296}
297
298static int imx_irqsteer_resume(struct device *dev)
299{
300 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
301 int ret;
302
303 ret = clk_prepare_enable(clk: irqsteer_data->ipg_clk);
304 if (ret) {
305 dev_err(dev, "failed to enable ipg clk: %d\n", ret);
306 return ret;
307 }
308 imx_irqsteer_restore_regs(data: irqsteer_data);
309
310 return 0;
311}
312#endif
313
314static const struct dev_pm_ops imx_irqsteer_pm_ops = {
315 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
316 pm_runtime_force_resume)
317 SET_RUNTIME_PM_OPS(imx_irqsteer_suspend,
318 imx_irqsteer_resume, NULL)
319};
320
321static const struct of_device_id imx_irqsteer_dt_ids[] = {
322 { .compatible = "fsl,imx-irqsteer", },
323 {},
324};
325
326static struct platform_driver imx_irqsteer_driver = {
327 .driver = {
328 .name = "imx-irqsteer",
329 .of_match_table = imx_irqsteer_dt_ids,
330 .pm = &imx_irqsteer_pm_ops,
331 },
332 .probe = imx_irqsteer_probe,
333 .remove = imx_irqsteer_remove,
334};
335builtin_platform_driver(imx_irqsteer_driver);
336

source code of linux/drivers/irqchip/irq-imx-irqsteer.c