1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 *
5 * Max Schwarz <max.schwarz@online.de>
6 * based on the patches by Rockchip Inc.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/iopoll.h>
14#include <linux/errno.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/spinlock.h>
21#include <linux/clk.h>
22#include <linux/wait.h>
23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
25#include <linux/math64.h>
26
27
28/* Register Map */
29#define REG_CON 0x00 /* control register */
30#define REG_CLKDIV 0x04 /* clock divisor register */
31#define REG_MRXADDR 0x08 /* target address for REGISTER_TX */
32#define REG_MRXRADDR 0x0c /* target register address for REGISTER_TX */
33#define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
34#define REG_MRXCNT 0x14 /* number of bytes to be received */
35#define REG_IEN 0x18 /* interrupt enable */
36#define REG_IPD 0x1c /* interrupt pending */
37#define REG_FCNT 0x20 /* finished count */
38
39/* Data buffer offsets */
40#define TXBUFFER_BASE 0x100
41#define RXBUFFER_BASE 0x200
42
43/* REG_CON bits */
44#define REG_CON_EN BIT(0)
45enum {
46 REG_CON_MOD_TX = 0, /* transmit data */
47 REG_CON_MOD_REGISTER_TX, /* select register and restart */
48 REG_CON_MOD_RX, /* receive data */
49 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
50 * register addr */
51};
52#define REG_CON_MOD(mod) ((mod) << 1)
53#define REG_CON_MOD_MASK (BIT(1) | BIT(2))
54#define REG_CON_START BIT(3)
55#define REG_CON_STOP BIT(4)
56#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
57#define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
58
59#define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
60
61#define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
62#define REG_CON_STA_CFG(cfg) ((cfg) << 12)
63#define REG_CON_STO_CFG(cfg) ((cfg) << 14)
64
65/* REG_MRXADDR bits */
66#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
67
68/* REG_IEN/REG_IPD bits */
69#define REG_INT_BTF BIT(0) /* a byte was transmitted */
70#define REG_INT_BRF BIT(1) /* a byte was received */
71#define REG_INT_MBTF BIT(2) /* controller data transmit finished */
72#define REG_INT_MBRF BIT(3) /* controller data receive finished */
73#define REG_INT_START BIT(4) /* START condition generated */
74#define REG_INT_STOP BIT(5) /* STOP condition generated */
75#define REG_INT_NAKRCV BIT(6) /* NACK received */
76#define REG_INT_ALL 0x7f
77
78/* Constants */
79#define WAIT_TIMEOUT 1000 /* ms */
80#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
81
82/**
83 * struct i2c_spec_values - I2C specification values for various modes
84 * @min_hold_start_ns: min hold time (repeated) START condition
85 * @min_low_ns: min LOW period of the SCL clock
86 * @min_high_ns: min HIGH period of the SCL cloc
87 * @min_setup_start_ns: min set-up time for a repeated START conditio
88 * @max_data_hold_ns: max data hold time
89 * @min_data_setup_ns: min data set-up time
90 * @min_setup_stop_ns: min set-up time for STOP condition
91 * @min_hold_buffer_ns: min bus free time between a STOP and
92 * START condition
93 */
94struct i2c_spec_values {
95 unsigned long min_hold_start_ns;
96 unsigned long min_low_ns;
97 unsigned long min_high_ns;
98 unsigned long min_setup_start_ns;
99 unsigned long max_data_hold_ns;
100 unsigned long min_data_setup_ns;
101 unsigned long min_setup_stop_ns;
102 unsigned long min_hold_buffer_ns;
103};
104
105static const struct i2c_spec_values standard_mode_spec = {
106 .min_hold_start_ns = 4000,
107 .min_low_ns = 4700,
108 .min_high_ns = 4000,
109 .min_setup_start_ns = 4700,
110 .max_data_hold_ns = 3450,
111 .min_data_setup_ns = 250,
112 .min_setup_stop_ns = 4000,
113 .min_hold_buffer_ns = 4700,
114};
115
116static const struct i2c_spec_values fast_mode_spec = {
117 .min_hold_start_ns = 600,
118 .min_low_ns = 1300,
119 .min_high_ns = 600,
120 .min_setup_start_ns = 600,
121 .max_data_hold_ns = 900,
122 .min_data_setup_ns = 100,
123 .min_setup_stop_ns = 600,
124 .min_hold_buffer_ns = 1300,
125};
126
127static const struct i2c_spec_values fast_mode_plus_spec = {
128 .min_hold_start_ns = 260,
129 .min_low_ns = 500,
130 .min_high_ns = 260,
131 .min_setup_start_ns = 260,
132 .max_data_hold_ns = 400,
133 .min_data_setup_ns = 50,
134 .min_setup_stop_ns = 260,
135 .min_hold_buffer_ns = 500,
136};
137
138/**
139 * struct rk3x_i2c_calced_timings - calculated V1 timings
140 * @div_low: Divider output for low
141 * @div_high: Divider output for high
142 * @tuning: Used to adjust setup/hold data time,
143 * setup/hold start time and setup stop time for
144 * v1's calc_timings, the tuning should all be 0
145 * for old hardware anyone using v0's calc_timings.
146 */
147struct rk3x_i2c_calced_timings {
148 unsigned long div_low;
149 unsigned long div_high;
150 unsigned int tuning;
151};
152
153enum rk3x_i2c_state {
154 STATE_IDLE,
155 STATE_START,
156 STATE_READ,
157 STATE_WRITE,
158 STATE_STOP
159};
160
161/**
162 * struct rk3x_i2c_soc_data - SOC-specific data
163 * @grf_offset: offset inside the grf regmap for setting the i2c type
164 * @calc_timings: Callback function for i2c timing information calculated
165 */
166struct rk3x_i2c_soc_data {
167 int grf_offset;
168 int (*calc_timings)(unsigned long, struct i2c_timings *,
169 struct rk3x_i2c_calced_timings *);
170};
171
172/**
173 * struct rk3x_i2c - private data of the controller
174 * @adap: corresponding I2C adapter
175 * @dev: device for this controller
176 * @soc_data: related soc data struct
177 * @regs: virtual memory area
178 * @clk: function clk for rk3399 or function & Bus clks for others
179 * @pclk: Bus clk for rk3399
180 * @clk_rate_nb: i2c clk rate change notify
181 * @irq: irq number
182 * @t: I2C known timing information
183 * @lock: spinlock for the i2c bus
184 * @wait: the waitqueue to wait for i2c transfer
185 * @busy: the condition for the event to wait for
186 * @msg: current i2c message
187 * @addr: addr of i2c target device
188 * @mode: mode of i2c transfer
189 * @is_last_msg: flag determines whether it is the last msg in this transfer
190 * @state: state of i2c transfer
191 * @processed: byte length which has been send or received
192 * @error: error code for i2c transfer
193 */
194struct rk3x_i2c {
195 struct i2c_adapter adap;
196 struct device *dev;
197 const struct rk3x_i2c_soc_data *soc_data;
198
199 /* Hardware resources */
200 void __iomem *regs;
201 struct clk *clk;
202 struct clk *pclk;
203 struct notifier_block clk_rate_nb;
204 int irq;
205
206 /* Settings */
207 struct i2c_timings t;
208
209 /* Synchronization & notification */
210 spinlock_t lock;
211 wait_queue_head_t wait;
212 bool busy;
213
214 /* Current message */
215 struct i2c_msg *msg;
216 u8 addr;
217 unsigned int mode;
218 bool is_last_msg;
219
220 /* I2C state machine */
221 enum rk3x_i2c_state state;
222 unsigned int processed;
223 int error;
224};
225
226static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
227 unsigned int offset)
228{
229 writel(val: value, addr: i2c->regs + offset);
230}
231
232static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
233{
234 return readl(addr: i2c->regs + offset);
235}
236
237/* Reset all interrupt pending bits */
238static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
239{
240 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
241}
242
243/**
244 * rk3x_i2c_start - Generate a START condition, which triggers a REG_INT_START interrupt.
245 * @i2c: target controller data
246 */
247static void rk3x_i2c_start(struct rk3x_i2c *i2c)
248{
249 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
250
251 i2c_writel(i2c, REG_INT_START, REG_IEN);
252
253 /* enable adapter with correct mode, send START condition */
254 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
255
256 /* if we want to react to NACK, set ACTACK bit */
257 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
258 val |= REG_CON_ACTACK;
259
260 i2c_writel(i2c, value: val, REG_CON);
261}
262
263/**
264 * rk3x_i2c_stop - Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
265 * @i2c: target controller data
266 * @error: Error code to return in rk3x_i2c_xfer
267 */
268static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
269{
270 unsigned int ctrl;
271
272 i2c->processed = 0;
273 i2c->msg = NULL;
274 i2c->error = error;
275
276 if (i2c->is_last_msg) {
277 /* Enable stop interrupt */
278 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
279
280 i2c->state = STATE_STOP;
281
282 ctrl = i2c_readl(i2c, REG_CON);
283 ctrl |= REG_CON_STOP;
284 i2c_writel(i2c, value: ctrl, REG_CON);
285 } else {
286 /* Signal rk3x_i2c_xfer to start the next message. */
287 i2c->busy = false;
288 i2c->state = STATE_IDLE;
289
290 /*
291 * The HW is actually not capable of REPEATED START. But we can
292 * get the intended effect by resetting its internal state
293 * and issuing an ordinary START.
294 */
295 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
296 i2c_writel(i2c, value: ctrl, REG_CON);
297
298 /* signal that we are finished with the current msg */
299 wake_up(&i2c->wait);
300 }
301}
302
303/**
304 * rk3x_i2c_prepare_read - Setup a read according to i2c->msg
305 * @i2c: target controller data
306 */
307static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
308{
309 unsigned int len = i2c->msg->len - i2c->processed;
310 u32 con;
311
312 con = i2c_readl(i2c, REG_CON);
313
314 /*
315 * The hw can read up to 32 bytes at a time. If we need more than one
316 * chunk, send an ACK after the last byte of the current chunk.
317 */
318 if (len > 32) {
319 len = 32;
320 con &= ~REG_CON_LASTACK;
321 } else {
322 con |= REG_CON_LASTACK;
323 }
324
325 /* make sure we are in plain RX mode if we read a second chunk */
326 if (i2c->processed != 0) {
327 con &= ~REG_CON_MOD_MASK;
328 con |= REG_CON_MOD(REG_CON_MOD_RX);
329 }
330
331 i2c_writel(i2c, value: con, REG_CON);
332 i2c_writel(i2c, value: len, REG_MRXCNT);
333}
334
335/**
336 * rk3x_i2c_fill_transmit_buf - Fill the transmit buffer with data from i2c->msg
337 * @i2c: target controller data
338 */
339static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
340{
341 unsigned int i, j;
342 u32 cnt = 0;
343 u32 val;
344 u8 byte;
345
346 for (i = 0; i < 8; ++i) {
347 val = 0;
348 for (j = 0; j < 4; ++j) {
349 if ((i2c->processed == i2c->msg->len) && (cnt != 0))
350 break;
351
352 if (i2c->processed == 0 && cnt == 0)
353 byte = (i2c->addr & 0x7f) << 1;
354 else
355 byte = i2c->msg->buf[i2c->processed++];
356
357 val |= byte << (j * 8);
358 cnt++;
359 }
360
361 i2c_writel(i2c, value: val, TXBUFFER_BASE + 4 * i);
362
363 if (i2c->processed == i2c->msg->len)
364 break;
365 }
366
367 i2c_writel(i2c, value: cnt, REG_MTXCNT);
368}
369
370
371/* IRQ handlers for individual states */
372
373static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
374{
375 if (!(ipd & REG_INT_START)) {
376 rk3x_i2c_stop(i2c, error: -EIO);
377 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
378 rk3x_i2c_clean_ipd(i2c);
379 return;
380 }
381
382 /* ack interrupt */
383 i2c_writel(i2c, REG_INT_START, REG_IPD);
384
385 /* disable start bit */
386 i2c_writel(i2c, value: i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
387
388 /* enable appropriate interrupts and transition */
389 if (i2c->mode == REG_CON_MOD_TX) {
390 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
391 i2c->state = STATE_WRITE;
392 rk3x_i2c_fill_transmit_buf(i2c);
393 } else {
394 /* in any other case, we are going to be reading. */
395 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
396 i2c->state = STATE_READ;
397 rk3x_i2c_prepare_read(i2c);
398 }
399}
400
401static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
402{
403 if (!(ipd & REG_INT_MBTF)) {
404 rk3x_i2c_stop(i2c, error: -EIO);
405 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
406 rk3x_i2c_clean_ipd(i2c);
407 return;
408 }
409
410 /* ack interrupt */
411 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
412
413 /* are we finished? */
414 if (i2c->processed == i2c->msg->len)
415 rk3x_i2c_stop(i2c, error: i2c->error);
416 else
417 rk3x_i2c_fill_transmit_buf(i2c);
418}
419
420static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
421{
422 unsigned int i;
423 unsigned int len = i2c->msg->len - i2c->processed;
424 u32 val;
425 u8 byte;
426
427 /* we only care for MBRF here. */
428 if (!(ipd & REG_INT_MBRF))
429 return;
430
431 /* ack interrupt (read also produces a spurious START flag, clear it too) */
432 i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
433
434 /* Can only handle a maximum of 32 bytes at a time */
435 if (len > 32)
436 len = 32;
437
438 /* read the data from receive buffer */
439 for (i = 0; i < len; ++i) {
440 if (i % 4 == 0)
441 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
442
443 byte = (val >> ((i % 4) * 8)) & 0xff;
444 i2c->msg->buf[i2c->processed++] = byte;
445 }
446
447 /* are we finished? */
448 if (i2c->processed == i2c->msg->len)
449 rk3x_i2c_stop(i2c, error: i2c->error);
450 else
451 rk3x_i2c_prepare_read(i2c);
452}
453
454static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
455{
456 unsigned int con;
457
458 if (!(ipd & REG_INT_STOP)) {
459 rk3x_i2c_stop(i2c, error: -EIO);
460 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
461 rk3x_i2c_clean_ipd(i2c);
462 return;
463 }
464
465 /* ack interrupt */
466 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
467
468 /* disable STOP bit */
469 con = i2c_readl(i2c, REG_CON);
470 con &= ~REG_CON_STOP;
471 i2c_writel(i2c, value: con, REG_CON);
472
473 i2c->busy = false;
474 i2c->state = STATE_IDLE;
475
476 /* signal rk3x_i2c_xfer that we are finished */
477 wake_up(&i2c->wait);
478}
479
480static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
481{
482 struct rk3x_i2c *i2c = dev_id;
483 unsigned int ipd;
484
485 spin_lock(lock: &i2c->lock);
486
487 ipd = i2c_readl(i2c, REG_IPD);
488 if (i2c->state == STATE_IDLE) {
489 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
490 rk3x_i2c_clean_ipd(i2c);
491 goto out;
492 }
493
494 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
495
496 /* Clean interrupt bits we don't care about */
497 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
498
499 if (ipd & REG_INT_NAKRCV) {
500 /*
501 * We got a NACK in the last operation. Depending on whether
502 * IGNORE_NAK is set, we have to stop the operation and report
503 * an error.
504 */
505 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
506
507 ipd &= ~REG_INT_NAKRCV;
508
509 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
510 rk3x_i2c_stop(i2c, error: -ENXIO);
511 }
512
513 /* is there anything left to handle? */
514 if ((ipd & REG_INT_ALL) == 0)
515 goto out;
516
517 switch (i2c->state) {
518 case STATE_START:
519 rk3x_i2c_handle_start(i2c, ipd);
520 break;
521 case STATE_WRITE:
522 rk3x_i2c_handle_write(i2c, ipd);
523 break;
524 case STATE_READ:
525 rk3x_i2c_handle_read(i2c, ipd);
526 break;
527 case STATE_STOP:
528 rk3x_i2c_handle_stop(i2c, ipd);
529 break;
530 case STATE_IDLE:
531 break;
532 }
533
534out:
535 spin_unlock(lock: &i2c->lock);
536 return IRQ_HANDLED;
537}
538
539/**
540 * rk3x_i2c_get_spec - Get timing values of I2C specification
541 * @speed: Desired SCL frequency
542 *
543 * Return: Matched i2c_spec_values.
544 */
545static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
546{
547 if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
548 return &standard_mode_spec;
549 else if (speed <= I2C_MAX_FAST_MODE_FREQ)
550 return &fast_mode_spec;
551 else
552 return &fast_mode_plus_spec;
553}
554
555/**
556 * rk3x_i2c_v0_calc_timings - Calculate divider values for desired SCL frequency
557 * @clk_rate: I2C input clock rate
558 * @t: Known I2C timing information
559 * @t_calc: Caculated rk3x private timings that would be written into regs
560 *
561 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
562 * a best-effort divider value is returned in divs. If the target rate is
563 * too high, we silently use the highest possible rate.
564 */
565static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
566 struct i2c_timings *t,
567 struct rk3x_i2c_calced_timings *t_calc)
568{
569 unsigned long min_low_ns, min_high_ns;
570 unsigned long max_low_ns, min_total_ns;
571
572 unsigned long clk_rate_khz, scl_rate_khz;
573
574 unsigned long min_low_div, min_high_div;
575 unsigned long max_low_div;
576
577 unsigned long min_div_for_hold, min_total_div;
578 unsigned long extra_div, extra_low_div, ideal_low_div;
579
580 unsigned long data_hold_buffer_ns = 50;
581 const struct i2c_spec_values *spec;
582 int ret = 0;
583
584 /* Only support standard-mode and fast-mode */
585 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ))
586 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
587
588 /* prevent scl_rate_khz from becoming 0 */
589 if (WARN_ON(t->bus_freq_hz < 1000))
590 t->bus_freq_hz = 1000;
591
592 /*
593 * min_low_ns: The minimum number of ns we need to hold low to
594 * meet I2C specification, should include fall time.
595 * min_high_ns: The minimum number of ns we need to hold high to
596 * meet I2C specification, should include rise time.
597 * max_low_ns: The maximum number of ns we can hold low to meet
598 * I2C specification.
599 *
600 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
601 * This is because the i2c host on Rockchip holds the data line
602 * for half the low time.
603 */
604 spec = rk3x_i2c_get_spec(speed: t->bus_freq_hz);
605 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
606
607 /*
608 * Timings for repeated start:
609 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
610 * - controller appears to keep SCL high for 2x programmed clk high.
611 *
612 * We need to account for those rules in picking our "high" time so
613 * we meet tSU;STA and tHD;STA times.
614 */
615 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
616 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
617 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
618 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
619 spec->min_high_ns), 2));
620
621 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
622 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
623 min_total_ns = min_low_ns + min_high_ns;
624
625 /* Adjust to avoid overflow */
626 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
627 scl_rate_khz = t->bus_freq_hz / 1000;
628
629 /*
630 * We need the total div to be >= this number
631 * so we don't clock too fast.
632 */
633 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
634
635 /* These are the min dividers needed for min hold times. */
636 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
637 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
638 min_div_for_hold = (min_low_div + min_high_div);
639
640 /*
641 * This is the maximum divider so we don't go over the maximum.
642 * We don't round up here (we round down) since this is a maximum.
643 */
644 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
645
646 if (min_low_div > max_low_div) {
647 WARN_ONCE(true,
648 "Conflicting, min_low_div %lu, max_low_div %lu\n",
649 min_low_div, max_low_div);
650 max_low_div = min_low_div;
651 }
652
653 if (min_div_for_hold > min_total_div) {
654 /*
655 * Time needed to meet hold requirements is important.
656 * Just use that.
657 */
658 t_calc->div_low = min_low_div;
659 t_calc->div_high = min_high_div;
660 } else {
661 /*
662 * We've got to distribute some time among the low and high
663 * so we don't run too fast.
664 */
665 extra_div = min_total_div - min_div_for_hold;
666
667 /*
668 * We'll try to split things up perfectly evenly,
669 * biasing slightly towards having a higher div
670 * for low (spend more time low).
671 */
672 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
673 scl_rate_khz * 8 * min_total_ns);
674
675 /* Don't allow it to go over the maximum */
676 if (ideal_low_div > max_low_div)
677 ideal_low_div = max_low_div;
678
679 /*
680 * Handle when the ideal low div is going to take up
681 * more than we have.
682 */
683 if (ideal_low_div > min_low_div + extra_div)
684 ideal_low_div = min_low_div + extra_div;
685
686 /* Give low the "ideal" and give high whatever extra is left */
687 extra_low_div = ideal_low_div - min_low_div;
688 t_calc->div_low = ideal_low_div;
689 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
690 }
691
692 /*
693 * Adjust to the fact that the hardware has an implicit "+1".
694 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
695 */
696 t_calc->div_low--;
697 t_calc->div_high--;
698
699 /* Give the tuning value 0, that would not update con register */
700 t_calc->tuning = 0;
701 /* Maximum divider supported by hw is 0xffff */
702 if (t_calc->div_low > 0xffff) {
703 t_calc->div_low = 0xffff;
704 ret = -EINVAL;
705 }
706
707 if (t_calc->div_high > 0xffff) {
708 t_calc->div_high = 0xffff;
709 ret = -EINVAL;
710 }
711
712 return ret;
713}
714
715/**
716 * rk3x_i2c_v1_calc_timings - Calculate timing values for desired SCL frequency
717 * @clk_rate: I2C input clock rate
718 * @t: Known I2C timing information
719 * @t_calc: Caculated rk3x private timings that would be written into regs
720 *
721 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
722 * a best-effort divider value is returned in divs. If the target rate is
723 * too high, we silently use the highest possible rate.
724 * The following formulas are v1's method to calculate timings.
725 *
726 * l = divl + 1;
727 * h = divh + 1;
728 * s = sda_update_config + 1;
729 * u = start_setup_config + 1;
730 * p = stop_setup_config + 1;
731 * T = Tclk_i2c;
732 *
733 * tHigh = 8 * h * T;
734 * tLow = 8 * l * T;
735 *
736 * tHD;sda = (l * s + 1) * T;
737 * tSU;sda = [(8 - s) * l + 1] * T;
738 * tI2C = 8 * (l + h) * T;
739 *
740 * tSU;sta = (8h * u + 1) * T;
741 * tHD;sta = [8h * (u + 1) - 1] * T;
742 * tSU;sto = (8h * p + 1) * T;
743 */
744static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
745 struct i2c_timings *t,
746 struct rk3x_i2c_calced_timings *t_calc)
747{
748 unsigned long min_low_ns, min_high_ns;
749 unsigned long min_setup_start_ns, min_setup_data_ns;
750 unsigned long min_setup_stop_ns, max_hold_data_ns;
751
752 unsigned long clk_rate_khz, scl_rate_khz;
753
754 unsigned long min_low_div, min_high_div;
755
756 unsigned long min_div_for_hold, min_total_div;
757 unsigned long extra_div, extra_low_div;
758 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
759
760 const struct i2c_spec_values *spec;
761 int ret = 0;
762
763 /* Support standard-mode, fast-mode and fast-mode plus */
764 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ))
765 t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
766
767 /* prevent scl_rate_khz from becoming 0 */
768 if (WARN_ON(t->bus_freq_hz < 1000))
769 t->bus_freq_hz = 1000;
770
771 /*
772 * min_low_ns: The minimum number of ns we need to hold low to
773 * meet I2C specification, should include fall time.
774 * min_high_ns: The minimum number of ns we need to hold high to
775 * meet I2C specification, should include rise time.
776 */
777 spec = rk3x_i2c_get_spec(speed: t->bus_freq_hz);
778
779 /* calculate min-divh and min-divl */
780 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
781 scl_rate_khz = t->bus_freq_hz / 1000;
782 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
783
784 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
785 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
786
787 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
788 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
789
790 /*
791 * Final divh and divl must be greater than 0, otherwise the
792 * hardware would not output the i2c clk.
793 */
794 min_high_div = (min_high_div < 1) ? 2 : min_high_div;
795 min_low_div = (min_low_div < 1) ? 2 : min_low_div;
796
797 /* These are the min dividers needed for min hold times. */
798 min_div_for_hold = (min_low_div + min_high_div);
799
800 /*
801 * This is the maximum divider so we don't go over the maximum.
802 * We don't round up here (we round down) since this is a maximum.
803 */
804 if (min_div_for_hold >= min_total_div) {
805 /*
806 * Time needed to meet hold requirements is important.
807 * Just use that.
808 */
809 t_calc->div_low = min_low_div;
810 t_calc->div_high = min_high_div;
811 } else {
812 /*
813 * We've got to distribute some time among the low and high
814 * so we don't run too fast.
815 * We'll try to split things up by the scale of min_low_div and
816 * min_high_div, biasing slightly towards having a higher div
817 * for low (spend more time low).
818 */
819 extra_div = min_total_div - min_div_for_hold;
820 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
821 min_div_for_hold);
822
823 t_calc->div_low = min_low_div + extra_low_div;
824 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
825 }
826
827 /*
828 * calculate sda data hold count by the rules, data_upd_st:3
829 * is a appropriate value to reduce calculated times.
830 */
831 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
832 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
833 * (t_calc->div_low) + 1)
834 * 1000000, clk_rate_khz);
835 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
836 * (t_calc->div_low) + 1)
837 * 1000000, clk_rate_khz);
838 if ((max_hold_data_ns < spec->max_data_hold_ns) &&
839 (min_setup_data_ns > spec->min_data_setup_ns))
840 break;
841 }
842
843 /* calculate setup start config */
844 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
845 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
846 - 1000000, 8 * 1000000 * (t_calc->div_high));
847
848 /* calculate setup stop config */
849 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
850 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
851 - 1000000, 8 * 1000000 * (t_calc->div_high));
852
853 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
854 REG_CON_STA_CFG(--stp_sta_cfg) |
855 REG_CON_STO_CFG(--stp_sto_cfg);
856
857 t_calc->div_low--;
858 t_calc->div_high--;
859
860 /* Maximum divider supported by hw is 0xffff */
861 if (t_calc->div_low > 0xffff) {
862 t_calc->div_low = 0xffff;
863 ret = -EINVAL;
864 }
865
866 if (t_calc->div_high > 0xffff) {
867 t_calc->div_high = 0xffff;
868 ret = -EINVAL;
869 }
870
871 return ret;
872}
873
874static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
875{
876 struct i2c_timings *t = &i2c->t;
877 struct rk3x_i2c_calced_timings calc;
878 u64 t_low_ns, t_high_ns;
879 unsigned long flags;
880 u32 val;
881 int ret;
882
883 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
884 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
885
886 clk_enable(clk: i2c->pclk);
887
888 spin_lock_irqsave(&i2c->lock, flags);
889 val = i2c_readl(i2c, REG_CON);
890 val &= ~REG_CON_TUNING_MASK;
891 val |= calc.tuning;
892 i2c_writel(i2c, value: val, REG_CON);
893 i2c_writel(i2c, value: (calc.div_high << 16) | (calc.div_low & 0xffff),
894 REG_CLKDIV);
895 spin_unlock_irqrestore(lock: &i2c->lock, flags);
896
897 clk_disable(clk: i2c->pclk);
898
899 t_low_ns = div_u64(dividend: ((u64)calc.div_low + 1) * 8 * 1000000000, divisor: clk_rate);
900 t_high_ns = div_u64(dividend: ((u64)calc.div_high + 1) * 8 * 1000000000,
901 divisor: clk_rate);
902 dev_dbg(i2c->dev,
903 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
904 clk_rate / 1000,
905 1000000000 / t->bus_freq_hz,
906 t_low_ns, t_high_ns);
907}
908
909/**
910 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
911 * @nb: Pointer to notifier block
912 * @event: Notification reason
913 * @data: Pointer to notification data object
914 *
915 * The callback checks whether a valid bus frequency can be generated after the
916 * change. If so, the change is acknowledged, otherwise the change is aborted.
917 * New dividers are written to the HW in the pre- or post change notification
918 * depending on the scaling direction.
919 *
920 * Code adapted from i2c-cadence.c.
921 *
922 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
923 * to acknowledge the change, NOTIFY_DONE if the notification is
924 * considered irrelevant.
925 */
926static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
927 event, void *data)
928{
929 struct clk_notifier_data *ndata = data;
930 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
931 struct rk3x_i2c_calced_timings calc;
932
933 switch (event) {
934 case PRE_RATE_CHANGE:
935 /*
936 * Try the calculation (but don't store the result) ahead of
937 * time to see if we need to block the clock change. Timings
938 * shouldn't actually take effect until rk3x_i2c_adapt_div().
939 */
940 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
941 &calc) != 0)
942 return NOTIFY_STOP;
943
944 /* scale up */
945 if (ndata->new_rate > ndata->old_rate)
946 rk3x_i2c_adapt_div(i2c, clk_rate: ndata->new_rate);
947
948 return NOTIFY_OK;
949 case POST_RATE_CHANGE:
950 /* scale down */
951 if (ndata->new_rate < ndata->old_rate)
952 rk3x_i2c_adapt_div(i2c, clk_rate: ndata->new_rate);
953 return NOTIFY_OK;
954 case ABORT_RATE_CHANGE:
955 /* scale up */
956 if (ndata->new_rate > ndata->old_rate)
957 rk3x_i2c_adapt_div(i2c, clk_rate: ndata->old_rate);
958 return NOTIFY_OK;
959 default:
960 return NOTIFY_DONE;
961 }
962}
963
964/**
965 * rk3x_i2c_setup - Setup I2C registers for an I2C operation specified by msgs, num.
966 * @i2c: target controller data
967 * @msgs: I2C msgs to process
968 * @num: Number of msgs
969 *
970 * Must be called with i2c->lock held.
971 *
972 * Return: Number of I2C msgs processed or negative in case of error
973 */
974static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
975{
976 u32 addr = (msgs[0].addr & 0x7f) << 1;
977 int ret = 0;
978
979 /*
980 * The I2C adapter can issue a small (len < 4) write packet before
981 * reading. This speeds up SMBus-style register reads.
982 * The MRXADDR/MRXRADDR hold the target address and the target register
983 * address in this case.
984 */
985
986 if (num >= 2 && msgs[0].len < 4 &&
987 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
988 u32 reg_addr = 0;
989 int i;
990
991 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
992 addr >> 1);
993
994 /* Fill MRXRADDR with the register address(es) */
995 for (i = 0; i < msgs[0].len; ++i) {
996 reg_addr |= msgs[0].buf[i] << (i * 8);
997 reg_addr |= REG_MRXADDR_VALID(i);
998 }
999
1000 /* msgs[0] is handled by hw. */
1001 i2c->msg = &msgs[1];
1002
1003 i2c->mode = REG_CON_MOD_REGISTER_TX;
1004
1005 i2c_writel(i2c, value: addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1006 i2c_writel(i2c, value: reg_addr, REG_MRXRADDR);
1007
1008 ret = 2;
1009 } else {
1010 /*
1011 * We'll have to do it the boring way and process the msgs
1012 * one-by-one.
1013 */
1014
1015 if (msgs[0].flags & I2C_M_RD) {
1016 addr |= 1; /* set read bit */
1017
1018 /*
1019 * We have to transmit the target addr first. Use
1020 * MOD_REGISTER_TX for that purpose.
1021 */
1022 i2c->mode = REG_CON_MOD_REGISTER_TX;
1023 i2c_writel(i2c, value: addr | REG_MRXADDR_VALID(0),
1024 REG_MRXADDR);
1025 i2c_writel(i2c, value: 0, REG_MRXRADDR);
1026 } else {
1027 i2c->mode = REG_CON_MOD_TX;
1028 }
1029
1030 i2c->msg = &msgs[0];
1031
1032 ret = 1;
1033 }
1034
1035 i2c->addr = msgs[0].addr;
1036 i2c->busy = true;
1037 i2c->state = STATE_START;
1038 i2c->processed = 0;
1039 i2c->error = 0;
1040
1041 rk3x_i2c_clean_ipd(i2c);
1042
1043 return ret;
1044}
1045
1046static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c)
1047{
1048 ktime_t timeout = ktime_add_ms(kt: ktime_get(), WAIT_TIMEOUT);
1049
1050 while (READ_ONCE(i2c->busy) &&
1051 ktime_compare(cmp1: ktime_get(), cmp2: timeout) < 0) {
1052 udelay(usec: 5);
1053 rk3x_i2c_irq(irqno: 0, dev_id: i2c);
1054 }
1055
1056 return !i2c->busy;
1057}
1058
1059static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
1060 struct i2c_msg *msgs, int num, bool polling)
1061{
1062 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1063 unsigned long flags;
1064 long time_left;
1065 u32 val;
1066 int ret = 0;
1067 int i;
1068
1069 spin_lock_irqsave(&i2c->lock, flags);
1070
1071 clk_enable(clk: i2c->clk);
1072 clk_enable(clk: i2c->pclk);
1073
1074 i2c->is_last_msg = false;
1075
1076 /*
1077 * Process msgs. We can handle more than one message at once (see
1078 * rk3x_i2c_setup()).
1079 */
1080 for (i = 0; i < num; i += ret) {
1081 ret = rk3x_i2c_setup(i2c, msgs: msgs + i, num: num - i);
1082
1083 if (ret < 0) {
1084 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1085 break;
1086 }
1087
1088 if (i + ret >= num)
1089 i2c->is_last_msg = true;
1090
1091 spin_unlock_irqrestore(lock: &i2c->lock, flags);
1092
1093 if (!polling) {
1094 rk3x_i2c_start(i2c);
1095
1096 time_left = wait_event_timeout(i2c->wait, !i2c->busy,
1097 msecs_to_jiffies(WAIT_TIMEOUT));
1098 } else {
1099 disable_irq(irq: i2c->irq);
1100 rk3x_i2c_start(i2c);
1101
1102 time_left = rk3x_i2c_wait_xfer_poll(i2c);
1103
1104 enable_irq(irq: i2c->irq);
1105 }
1106
1107 spin_lock_irqsave(&i2c->lock, flags);
1108
1109 if (time_left == 0) {
1110 /* Force a STOP condition without interrupt */
1111 i2c_writel(i2c, value: 0, REG_IEN);
1112 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1113 val |= REG_CON_EN | REG_CON_STOP;
1114 i2c_writel(i2c, value: val, REG_CON);
1115
1116 i2c->state = STATE_IDLE;
1117
1118 ret = -ETIMEDOUT;
1119 break;
1120 }
1121
1122 if (i2c->error) {
1123 ret = i2c->error;
1124 break;
1125 }
1126 }
1127
1128 clk_disable(clk: i2c->pclk);
1129 clk_disable(clk: i2c->clk);
1130
1131 spin_unlock_irqrestore(lock: &i2c->lock, flags);
1132
1133 return ret < 0 ? ret : num;
1134}
1135
1136static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1137 struct i2c_msg *msgs, int num)
1138{
1139 return rk3x_i2c_xfer_common(adap, msgs, num, polling: false);
1140}
1141
1142static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap,
1143 struct i2c_msg *msgs, int num)
1144{
1145 return rk3x_i2c_xfer_common(adap, msgs, num, polling: true);
1146}
1147
1148static __maybe_unused int rk3x_i2c_resume(struct device *dev)
1149{
1150 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1151
1152 rk3x_i2c_adapt_div(i2c, clk_rate: clk_get_rate(clk: i2c->clk));
1153
1154 return 0;
1155}
1156
1157static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1158{
1159 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1160}
1161
1162static const struct i2c_algorithm rk3x_i2c_algorithm = {
1163 .xfer = rk3x_i2c_xfer,
1164 .xfer_atomic = rk3x_i2c_xfer_polling,
1165 .functionality = rk3x_i2c_func,
1166};
1167
1168static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1169 .grf_offset = -1,
1170 .calc_timings = rk3x_i2c_v1_calc_timings,
1171};
1172
1173static const struct rk3x_i2c_soc_data rv1126_soc_data = {
1174 .grf_offset = 0x118,
1175 .calc_timings = rk3x_i2c_v1_calc_timings,
1176};
1177
1178static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1179 .grf_offset = 0x154,
1180 .calc_timings = rk3x_i2c_v0_calc_timings,
1181};
1182
1183static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1184 .grf_offset = 0x0a4,
1185 .calc_timings = rk3x_i2c_v0_calc_timings,
1186};
1187
1188static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1189 .grf_offset = -1,
1190 .calc_timings = rk3x_i2c_v0_calc_timings,
1191};
1192
1193static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1194 .grf_offset = -1,
1195 .calc_timings = rk3x_i2c_v0_calc_timings,
1196};
1197
1198static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1199 .grf_offset = -1,
1200 .calc_timings = rk3x_i2c_v1_calc_timings,
1201};
1202
1203static const struct of_device_id rk3x_i2c_match[] = {
1204 {
1205 .compatible = "rockchip,rv1108-i2c",
1206 .data = &rv1108_soc_data
1207 },
1208 {
1209 .compatible = "rockchip,rv1126-i2c",
1210 .data = &rv1126_soc_data
1211 },
1212 {
1213 .compatible = "rockchip,rk3066-i2c",
1214 .data = &rk3066_soc_data
1215 },
1216 {
1217 .compatible = "rockchip,rk3188-i2c",
1218 .data = &rk3188_soc_data
1219 },
1220 {
1221 .compatible = "rockchip,rk3228-i2c",
1222 .data = &rk3228_soc_data
1223 },
1224 {
1225 .compatible = "rockchip,rk3288-i2c",
1226 .data = &rk3288_soc_data
1227 },
1228 {
1229 .compatible = "rockchip,rk3399-i2c",
1230 .data = &rk3399_soc_data
1231 },
1232 {},
1233};
1234MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1235
1236static int rk3x_i2c_probe(struct platform_device *pdev)
1237{
1238 struct device_node *np = pdev->dev.of_node;
1239 const struct of_device_id *match;
1240 struct rk3x_i2c *i2c;
1241 int ret = 0;
1242 int bus_nr;
1243 u32 value;
1244 int irq;
1245 unsigned long clk_rate;
1246
1247 i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct rk3x_i2c), GFP_KERNEL);
1248 if (!i2c)
1249 return -ENOMEM;
1250
1251 match = of_match_node(matches: rk3x_i2c_match, node: np);
1252 i2c->soc_data = match->data;
1253
1254 /* use common interface to get I2C timing properties */
1255 i2c_parse_fw_timings(dev: &pdev->dev, t: &i2c->t, use_defaults: true);
1256
1257 strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1258 i2c->adap.owner = THIS_MODULE;
1259 i2c->adap.algo = &rk3x_i2c_algorithm;
1260 i2c->adap.retries = 3;
1261 i2c->adap.dev.of_node = np;
1262 i2c->adap.algo_data = i2c;
1263 i2c->adap.dev.parent = &pdev->dev;
1264
1265 i2c->dev = &pdev->dev;
1266
1267 spin_lock_init(&i2c->lock);
1268 init_waitqueue_head(&i2c->wait);
1269
1270 i2c->regs = devm_platform_ioremap_resource(pdev, index: 0);
1271 if (IS_ERR(ptr: i2c->regs))
1272 return PTR_ERR(ptr: i2c->regs);
1273
1274 /* Try to set the I2C adapter number from dt */
1275 bus_nr = of_alias_get_id(np, stem: "i2c");
1276
1277 /*
1278 * Switch to new interface if the SoC also offers the old one.
1279 * The control bit is located in the GRF register space.
1280 */
1281 if (i2c->soc_data->grf_offset >= 0) {
1282 struct regmap *grf;
1283
1284 grf = syscon_regmap_lookup_by_phandle(np, property: "rockchip,grf");
1285 if (IS_ERR(ptr: grf)) {
1286 dev_err(&pdev->dev,
1287 "rk3x-i2c needs 'rockchip,grf' property\n");
1288 return PTR_ERR(ptr: grf);
1289 }
1290
1291 if (bus_nr < 0) {
1292 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1293 return -EINVAL;
1294 }
1295
1296 /* rv1126 i2c2 uses non-sequential write mask 20, value 4 */
1297 if (i2c->soc_data == &rv1126_soc_data && bus_nr == 2)
1298 value = BIT(20) | BIT(4);
1299 else
1300 /* 27+i: write mask, 11+i: value */
1301 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1302
1303 ret = regmap_write(map: grf, reg: i2c->soc_data->grf_offset, val: value);
1304 if (ret != 0) {
1305 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1306 return ret;
1307 }
1308 }
1309
1310 /* IRQ setup */
1311 irq = platform_get_irq(pdev, 0);
1312 if (irq < 0)
1313 return irq;
1314
1315 ret = devm_request_irq(dev: &pdev->dev, irq, handler: rk3x_i2c_irq,
1316 irqflags: 0, devname: dev_name(dev: &pdev->dev), dev_id: i2c);
1317 if (ret < 0) {
1318 dev_err(&pdev->dev, "cannot request IRQ\n");
1319 return ret;
1320 }
1321
1322 i2c->irq = irq;
1323
1324 platform_set_drvdata(pdev, data: i2c);
1325
1326 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1327 /* Only one clock to use for bus clock and peripheral clock */
1328 i2c->clk = devm_clk_get(dev: &pdev->dev, NULL);
1329 i2c->pclk = i2c->clk;
1330 } else {
1331 i2c->clk = devm_clk_get(dev: &pdev->dev, id: "i2c");
1332 i2c->pclk = devm_clk_get(dev: &pdev->dev, id: "pclk");
1333 }
1334
1335 if (IS_ERR(ptr: i2c->clk))
1336 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: i2c->clk),
1337 fmt: "Can't get bus clk\n");
1338
1339 if (IS_ERR(ptr: i2c->pclk))
1340 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: i2c->pclk),
1341 fmt: "Can't get periph clk\n");
1342
1343 ret = clk_prepare(clk: i2c->clk);
1344 if (ret < 0) {
1345 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1346 return ret;
1347 }
1348 ret = clk_prepare(clk: i2c->pclk);
1349 if (ret < 0) {
1350 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1351 goto err_clk;
1352 }
1353
1354 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1355 ret = clk_notifier_register(clk: i2c->clk, nb: &i2c->clk_rate_nb);
1356 if (ret != 0) {
1357 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1358 goto err_pclk;
1359 }
1360
1361 ret = clk_enable(clk: i2c->clk);
1362 if (ret < 0) {
1363 dev_err(&pdev->dev, "Can't enable bus clk: %d\n", ret);
1364 goto err_clk_notifier;
1365 }
1366
1367 clk_rate = clk_get_rate(clk: i2c->clk);
1368 rk3x_i2c_adapt_div(i2c, clk_rate);
1369 clk_disable(clk: i2c->clk);
1370
1371 ret = i2c_add_adapter(adap: &i2c->adap);
1372 if (ret < 0)
1373 goto err_clk_notifier;
1374
1375 return 0;
1376
1377err_clk_notifier:
1378 clk_notifier_unregister(clk: i2c->clk, nb: &i2c->clk_rate_nb);
1379err_pclk:
1380 clk_unprepare(clk: i2c->pclk);
1381err_clk:
1382 clk_unprepare(clk: i2c->clk);
1383 return ret;
1384}
1385
1386static void rk3x_i2c_remove(struct platform_device *pdev)
1387{
1388 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1389
1390 i2c_del_adapter(adap: &i2c->adap);
1391
1392 clk_notifier_unregister(clk: i2c->clk, nb: &i2c->clk_rate_nb);
1393 clk_unprepare(clk: i2c->pclk);
1394 clk_unprepare(clk: i2c->clk);
1395}
1396
1397static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume);
1398
1399static struct platform_driver rk3x_i2c_driver = {
1400 .probe = rk3x_i2c_probe,
1401 .remove = rk3x_i2c_remove,
1402 .driver = {
1403 .name = "rk3x-i2c",
1404 .of_match_table = rk3x_i2c_match,
1405 .pm = &rk3x_i2c_pm_ops,
1406 },
1407};
1408
1409module_platform_driver(rk3x_i2c_driver);
1410
1411MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1412MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1413MODULE_LICENSE("GPL v2");
1414

source code of linux/drivers/i2c/busses/i2c-rk3x.c