1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2023-2024 Intel Corporation
4 */
5
6#ifndef _XE_GT_SRIOV_PF_CONFIG_TYPES_H_
7#define _XE_GT_SRIOV_PF_CONFIG_TYPES_H_
8
9#include "xe_ggtt_types.h"
10#include "xe_guc_klv_thresholds_set_types.h"
11
12struct xe_bo;
13
14/**
15 * struct xe_gt_sriov_config - GT level per-VF configuration data.
16 *
17 * Used by the PF driver to maintain per-VF provisioning data.
18 */
19struct xe_gt_sriov_config {
20 /** @ggtt_region: GGTT region assigned to the VF. */
21 struct xe_ggtt_node *ggtt_region;
22 /** @lmem_obj: LMEM allocation for use by the VF. */
23 struct xe_bo *lmem_obj;
24 /** @num_ctxs: number of GuC contexts IDs. */
25 u16 num_ctxs;
26 /** @begin_ctx: start index of GuC context ID range. */
27 u16 begin_ctx;
28 /** @num_dbs: number of GuC doorbells IDs. */
29 u16 num_dbs;
30 /** @begin_db: start index of GuC doorbell ID range. */
31 u16 begin_db;
32 /** @exec_quantum: execution-quantum in milliseconds. */
33 u32 exec_quantum;
34 /** @preempt_timeout: preemption timeout in microseconds. */
35 u32 preempt_timeout;
36 /** @sched_priority: scheduling priority. */
37 u32 sched_priority;
38 /** @thresholds: GuC thresholds for adverse events notifications. */
39 u32 thresholds[XE_GUC_KLV_NUM_THRESHOLDS];
40};
41
42/**
43 * struct xe_gt_sriov_spare_config - GT-level PF spare configuration data.
44 *
45 * Used by the PF driver to maintain it's own reserved (spare) provisioning
46 * data that is not applicable to be tracked in struct xe_gt_sriov_config.
47 */
48struct xe_gt_sriov_spare_config {
49 /** @ggtt_size: GGTT size. */
50 u64 ggtt_size;
51 /** @lmem_size: LMEM size. */
52 u64 lmem_size;
53 /** @num_ctxs: number of GuC submission contexts. */
54 u16 num_ctxs;
55 /** @num_dbs: number of GuC doorbells. */
56 u16 num_dbs;
57};
58
59#endif
60

source code of linux/drivers/gpu/drm/xe/xe_gt_sriov_pf_config_types.h