1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (C) 2013 NVIDIA Corporation
4	*/
5
6	#include <linux/clk.h>
7	#include <linux/clk-provider.h>
8	#include <linux/debugfs.h>
9	#include <linux/io.h>
10	#include <linux/module.h>
11	#include <linux/of.h>
12	#include <linux/platform_device.h>
13	#include <linux/pm_runtime.h>
14	#include <linux/regulator/consumer.h>
15	#include <linux/reset.h>
16
17	#include <soc/tegra/pmc.h>
18
19	#include <drm/display/drm_dp_helper.h>
20	#include <drm/display/drm_scdc_helper.h>
21	#include <drm/drm_atomic_helper.h>
22	#include <drm/drm_debugfs.h>
23	#include <drm/drm_edid.h>
24	#include <drm/drm_eld.h>
25	#include <drm/drm_file.h>
26	#include <drm/drm_panel.h>
27	#include <drm/drm_print.h>
28	#include <drm/drm_simple_kms_helper.h>
29
30	#include "dc.h"
31	#include "dp.h"
32	#include "drm.h"
33	#include "hda.h"
34	#include "sor.h"
35	#include "trace.h"
36
37	#define SOR_REKEY 0x38
38
39	struct tegra_sor_hdmi_settings {
40	unsigned long frequency;
41
42	u8 vcocap;
43	u8 filter;
44	u8 ichpmp;
45	u8 loadadj;
46	u8 tmds_termadj;
47	u8 tx_pu_value;
48	u8 bg_temp_coef;
49	u8 bg_vref_level;
50	u8 avdd10_level;
51	u8 avdd14_level;
52	u8 sparepll;
53
54	u8 drive_current[4];
55	u8 preemphasis[4];
56	};
57
58	#if 1
59	static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
60	{
61	.frequency = 54000000,
62	.vcocap = 0x0,
63	.filter = 0x0,
64	.ichpmp = 0x1,
65	.loadadj = 0x3,
66	.tmds_termadj = 0x9,
67	.tx_pu_value = 0x10,
68	.bg_temp_coef = 0x3,
69	.bg_vref_level = 0x8,
70	.avdd10_level = 0x4,
71	.avdd14_level = 0x4,
72	.sparepll = 0x0,
73	.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
74	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
75	}, {
76	.frequency = 75000000,
77	.vcocap = 0x3,
78	.filter = 0x0,
79	.ichpmp = 0x1,
80	.loadadj = 0x3,
81	.tmds_termadj = 0x9,
82	.tx_pu_value = 0x40,
83	.bg_temp_coef = 0x3,
84	.bg_vref_level = 0x8,
85	.avdd10_level = 0x4,
86	.avdd14_level = 0x4,
87	.sparepll = 0x0,
88	.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
89	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
90	}, {
91	.frequency = 150000000,
92	.vcocap = 0x3,
93	.filter = 0x0,
94	.ichpmp = 0x1,
95	.loadadj = 0x3,
96	.tmds_termadj = 0x9,
97	.tx_pu_value = 0x66,
98	.bg_temp_coef = 0x3,
99	.bg_vref_level = 0x8,
100	.avdd10_level = 0x4,
101	.avdd14_level = 0x4,
102	.sparepll = 0x0,
103	.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
104	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
105	}, {
106	.frequency = 300000000,
107	.vcocap = 0x3,
108	.filter = 0x0,
109	.ichpmp = 0x1,
110	.loadadj = 0x3,
111	.tmds_termadj = 0x9,
112	.tx_pu_value = 0x66,
113	.bg_temp_coef = 0x3,
114	.bg_vref_level = 0xa,
115	.avdd10_level = 0x4,
116	.avdd14_level = 0x4,
117	.sparepll = 0x0,
118	.drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
119	.preemphasis = { 0x00, 0x17, 0x17, 0x17 },
120	}, {
121	.frequency = 600000000,
122	.vcocap = 0x3,
123	.filter = 0x0,
124	.ichpmp = 0x1,
125	.loadadj = 0x3,
126	.tmds_termadj = 0x9,
127	.tx_pu_value = 0x66,
128	.bg_temp_coef = 0x3,
129	.bg_vref_level = 0x8,
130	.avdd10_level = 0x4,
131	.avdd14_level = 0x4,
132	.sparepll = 0x0,
133	.drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
134	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
135	},
136	};
137	#else
138	static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
139	{
140	.frequency = 75000000,
141	.vcocap = 0x3,
142	.filter = 0x0,
143	.ichpmp = 0x1,
144	.loadadj = 0x3,
145	.tmds_termadj = 0x9,
146	.tx_pu_value = 0x40,
147	.bg_temp_coef = 0x3,
148	.bg_vref_level = 0x8,
149	.avdd10_level = 0x4,
150	.avdd14_level = 0x4,
151	.sparepll = 0x0,
152	.drive_current = { 0x29, 0x29, 0x29, 0x29 },
153	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
154	}, {
155	.frequency = 150000000,
156	.vcocap = 0x3,
157	.filter = 0x0,
158	.ichpmp = 0x1,
159	.loadadj = 0x3,
160	.tmds_termadj = 0x9,
161	.tx_pu_value = 0x66,
162	.bg_temp_coef = 0x3,
163	.bg_vref_level = 0x8,
164	.avdd10_level = 0x4,
165	.avdd14_level = 0x4,
166	.sparepll = 0x0,
167	.drive_current = { 0x30, 0x37, 0x37, 0x37 },
168	.preemphasis = { 0x01, 0x02, 0x02, 0x02 },
169	}, {
170	.frequency = 300000000,
171	.vcocap = 0x3,
172	.filter = 0x0,
173	.ichpmp = 0x6,
174	.loadadj = 0x3,
175	.tmds_termadj = 0x9,
176	.tx_pu_value = 0x66,
177	.bg_temp_coef = 0x3,
178	.bg_vref_level = 0xf,
179	.avdd10_level = 0x4,
180	.avdd14_level = 0x4,
181	.sparepll = 0x0,
182	.drive_current = { 0x30, 0x37, 0x37, 0x37 },
183	.preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
184	}, {
185	.frequency = 600000000,
186	.vcocap = 0x3,
187	.filter = 0x0,
188	.ichpmp = 0xa,
189	.loadadj = 0x3,
190	.tmds_termadj = 0xb,
191	.tx_pu_value = 0x66,
192	.bg_temp_coef = 0x3,
193	.bg_vref_level = 0xe,
194	.avdd10_level = 0x4,
195	.avdd14_level = 0x4,
196	.sparepll = 0x0,
197	.drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
198	.preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
199	},
200	};
201	#endif
202
203	static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
204	{
205	.frequency = 54000000,
206	.vcocap = 0,
207	.filter = 5,
208	.ichpmp = 5,
209	.loadadj = 3,
210	.tmds_termadj = 0xf,
211	.tx_pu_value = 0,
212	.bg_temp_coef = 3,
213	.bg_vref_level = 8,
214	.avdd10_level = 4,
215	.avdd14_level = 4,
216	.sparepll = 0x54,
217	.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
218	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
219	}, {
220	.frequency = 75000000,
221	.vcocap = 1,
222	.filter = 5,
223	.ichpmp = 5,
224	.loadadj = 3,
225	.tmds_termadj = 0xf,
226	.tx_pu_value = 0,
227	.bg_temp_coef = 3,
228	.bg_vref_level = 8,
229	.avdd10_level = 4,
230	.avdd14_level = 4,
231	.sparepll = 0x44,
232	.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
233	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
234	}, {
235	.frequency = 150000000,
236	.vcocap = 3,
237	.filter = 5,
238	.ichpmp = 5,
239	.loadadj = 3,
240	.tmds_termadj = 15,
241	.tx_pu_value = 0x66 /* 0 */,
242	.bg_temp_coef = 3,
243	.bg_vref_level = 8,
244	.avdd10_level = 4,
245	.avdd14_level = 4,
246	.sparepll = 0x00, /* 0x34 */
247	.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
248	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
249	}, {
250	.frequency = 300000000,
251	.vcocap = 3,
252	.filter = 5,
253	.ichpmp = 5,
254	.loadadj = 3,
255	.tmds_termadj = 15,
256	.tx_pu_value = 64,
257	.bg_temp_coef = 3,
258	.bg_vref_level = 8,
259	.avdd10_level = 4,
260	.avdd14_level = 4,
261	.sparepll = 0x34,
262	.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
263	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
264	}, {
265	.frequency = 600000000,
266	.vcocap = 3,
267	.filter = 5,
268	.ichpmp = 5,
269	.loadadj = 3,
270	.tmds_termadj = 12,
271	.tx_pu_value = 96,
272	.bg_temp_coef = 3,
273	.bg_vref_level = 8,
274	.avdd10_level = 4,
275	.avdd14_level = 4,
276	.sparepll = 0x34,
277	.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
278	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
279	}
280	};
281
282	static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
283	{
284	.frequency = 54000000,
285	.vcocap = 0,
286	.filter = 5,
287	.ichpmp = 5,
288	.loadadj = 3,
289	.tmds_termadj = 0xf,
290	.tx_pu_value = 0,
291	.bg_temp_coef = 3,
292	.bg_vref_level = 8,
293	.avdd10_level = 4,
294	.avdd14_level = 4,
295	.sparepll = 0x54,
296	.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
297	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
298	}, {
299	.frequency = 75000000,
300	.vcocap = 1,
301	.filter = 5,
302	.ichpmp = 5,
303	.loadadj = 3,
304	.tmds_termadj = 0xf,
305	.tx_pu_value = 0,
306	.bg_temp_coef = 3,
307	.bg_vref_level = 8,
308	.avdd10_level = 4,
309	.avdd14_level = 4,
310	.sparepll = 0x44,
311	.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
312	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
313	}, {
314	.frequency = 150000000,
315	.vcocap = 3,
316	.filter = 5,
317	.ichpmp = 5,
318	.loadadj = 3,
319	.tmds_termadj = 15,
320	.tx_pu_value = 0x66 /* 0 */,
321	.bg_temp_coef = 3,
322	.bg_vref_level = 8,
323	.avdd10_level = 4,
324	.avdd14_level = 4,
325	.sparepll = 0x00, /* 0x34 */
326	.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
327	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
328	}, {
329	.frequency = 300000000,
330	.vcocap = 3,
331	.filter = 5,
332	.ichpmp = 5,
333	.loadadj = 3,
334	.tmds_termadj = 15,
335	.tx_pu_value = 64,
336	.bg_temp_coef = 3,
337	.bg_vref_level = 8,
338	.avdd10_level = 4,
339	.avdd14_level = 4,
340	.sparepll = 0x34,
341	.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
342	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
343	}, {
344	.frequency = 600000000,
345	.vcocap = 3,
346	.filter = 5,
347	.ichpmp = 5,
348	.loadadj = 3,
349	.tmds_termadj = 12,
350	.tx_pu_value = 96,
351	.bg_temp_coef = 3,
352	.bg_vref_level = 8,
353	.avdd10_level = 4,
354	.avdd14_level = 4,
355	.sparepll = 0x34,
356	.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
357	.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
358	}
359	};
360
361	struct tegra_sor_regs {
362	unsigned int head_state0;
363	unsigned int head_state1;
364	unsigned int head_state2;
365	unsigned int head_state3;
366	unsigned int head_state4;
367	unsigned int head_state5;
368	unsigned int pll0;
369	unsigned int pll1;
370	unsigned int pll2;
371	unsigned int pll3;
372	unsigned int dp_padctl0;
373	unsigned int dp_padctl2;
374	};
375
376	struct tegra_sor_soc {
377	bool supports_lvds;
378	bool supports_hdmi;
379	bool supports_dp;
380	bool supports_audio;
381	bool supports_hdcp;
382
383	const struct tegra_sor_regs *regs;
384	bool has_nvdisplay;
385
386	const struct tegra_sor_hdmi_settings *settings;
387	unsigned int num_settings;
388
389	const u8 *xbar_cfg;
390	const u8 *lane_map;
391
392	const u8 (*voltage_swing)[4][4];
393	const u8 (*pre_emphasis)[4][4];
394	const u8 (*post_cursor)[4][4];
395	const u8 (*tx_pu)[4][4];
396	};
397
398	struct tegra_sor;
399
400	struct tegra_sor_ops {
401	const char *name;
402	int (*probe)(struct tegra_sor *sor);
403	void (*audio_enable)(struct tegra_sor *sor);
404	void (*audio_disable)(struct tegra_sor *sor);
405	};
406
407	struct tegra_sor {
408	struct host1x_client client;
409	struct tegra_output output;
410	struct device *dev;
411
412	const struct tegra_sor_soc *soc;
413	void __iomem *regs;
414	unsigned int index;
415	unsigned int irq;
416
417	struct reset_control *rst;
418	struct clk *clk_parent;
419	struct clk *clk_safe;
420	struct clk *clk_out;
421	struct clk *clk_pad;
422	struct clk *clk_dp;
423	struct clk *clk;
424
425	u8 xbar_cfg[5];
426
427	struct drm_dp_link link;
428	struct drm_dp_aux *aux;
429
430	struct drm_info_list *debugfs_files;
431
432	const struct tegra_sor_ops *ops;
433	enum tegra_io_pad pad;
434
435	/* for HDMI 2.0 */
436	struct tegra_sor_hdmi_settings *settings;
437	unsigned int num_settings;
438
439	struct regulator *avdd_io_supply;
440	struct regulator *vdd_pll_supply;
441	struct regulator *hdmi_supply;
442
443	struct delayed_work scdc;
444	bool scdc_enabled;
445
446	struct tegra_hda_format format;
447	};
448
449	struct tegra_sor_state {
450	struct drm_connector_state base;
451
452	unsigned int link_speed;
453	unsigned long pclk;
454	unsigned int bpc;
455	};
456
457	static inline struct tegra_sor_state *
458	to_sor_state(struct drm_connector_state *state)
459	{
460	return container_of(state, struct tegra_sor_state, base);
461	}
462
463	struct tegra_sor_config {
464	u32 bits_per_pixel;
465
466	u32 active_polarity;
467	u32 active_count;
468	u32 tu_size;
469	u32 active_frac;
470	u32 watermark;
471
472	u32 hblank_symbols;
473	u32 vblank_symbols;
474	};
475
476	static inline struct tegra_sor *
477	host1x_client_to_sor(struct host1x_client *client)
478	{
479	return container_of(client, struct tegra_sor, client);
480	}
481
482	static inline struct tegra_sor *to_sor(struct tegra_output *output)
483	{
484	return container_of(output, struct tegra_sor, output);
485	}
486
487	static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
488	{
489	u32 value = readl(addr: sor->regs + (offset << 2));
490
491	trace_sor_readl(dev: sor->dev, offset, value);
492
493	return value;
494	}
495
496	static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
497	unsigned int offset)
498	{
499	trace_sor_writel(dev: sor->dev, offset, value);
500	writel(val: value, addr: sor->regs + (offset << 2));
501	}
502
503	static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
504	{
505	int err;
506
507	clk_disable_unprepare(clk: sor->clk);
508
509	err = clk_set_parent(clk: sor->clk_out, parent);
510	if (err < 0)
511	return err;
512
513	err = clk_prepare_enable(clk: sor->clk);
514	if (err < 0)
515	return err;
516
517	return 0;
518	}
519
520	struct tegra_clk_sor_pad {
521	struct clk_hw hw;
522	struct tegra_sor *sor;
523	};
524
525	static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
526	{
527	return container_of(hw, struct tegra_clk_sor_pad, hw);
528	}
529
530	static const char * const tegra_clk_sor_pad_parents[2][2] = {
531	{ "pll_d_out0", "pll_dp" },
532	{ "pll_d2_out0", "pll_dp" },
533	};
534
535	/*
536	* Implementing ->set_parent() here isn't really required because the parent
537	* will be explicitly selected in the driver code via the DP_CLK_SEL mux in
538	* the SOR_CLK_CNTRL register. This is primarily for compatibility with the
539	* Tegra186 and later SoC generations where the BPMP implements this clock
540	* and doesn't expose the mux via the common clock framework.
541	*/
542
543	static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
544	{
545	struct tegra_clk_sor_pad *pad = to_pad(hw);
546	struct tegra_sor *sor = pad->sor;
547	u32 value;
548
549	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
550	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
551
552	switch (index) {
553	case 0:
554	value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
555	break;
556
557	case 1:
558	value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
559	break;
560	}
561
562	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
563
564	return 0;
565	}
566
567	static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
568	{
569	struct tegra_clk_sor_pad *pad = to_pad(hw);
570	struct tegra_sor *sor = pad->sor;
571	u8 parent = U8_MAX;
572	u32 value;
573
574	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
575
576	switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
577	case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
578	case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
579	parent = 0;
580	break;
581
582	case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
583	case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
584	parent = 1;
585	break;
586	}
587
588	return parent;
589	}
590
591	static const struct clk_ops tegra_clk_sor_pad_ops = {
592	.determine_rate = clk_hw_determine_rate_no_reparent,
593	.set_parent = tegra_clk_sor_pad_set_parent,
594	.get_parent = tegra_clk_sor_pad_get_parent,
595	};
596
597	static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
598	const char *name)
599	{
600	struct tegra_clk_sor_pad *pad;
601	struct clk_init_data init;
602	struct clk *clk;
603
604	pad = devm_kzalloc(dev: sor->dev, size: sizeof(*pad), GFP_KERNEL);
605	if (!pad)
606	return ERR_PTR(error: -ENOMEM);
607
608	pad->sor = sor;
609
610	init.name = name;
611	init.flags = 0;
612	init.parent_names = tegra_clk_sor_pad_parents[sor->index];
613	init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
614	init.ops = &tegra_clk_sor_pad_ops;
615
616	pad->hw.init = &init;
617
618	clk = devm_clk_register(dev: sor->dev, hw: &pad->hw);
619
620	return clk;
621	}
622
623	static void tegra_sor_filter_rates(struct tegra_sor *sor)
624	{
625	struct drm_dp_link *link = &sor->link;
626	unsigned int i;
627
628	/* Tegra only supports RBR, HBR and HBR2 */
629	for (i = 0; i < link->num_rates; i++) {
630	switch (link->rates[i]) {
631	case 1620000:
632	case 2700000:
633	case 5400000:
634	break;
635
636	default:
637	DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
638	link->rates[i]);
639	link->rates[i] = 0;
640	break;
641	}
642	}
643
644	drm_dp_link_update_rates(link);
645	}
646
647	static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
648	{
649	unsigned long timeout;
650	u32 value;
651
652	/*
653	* Clear or set the PD_TXD bit corresponding to each lane, depending
654	* on whether it is used or not.
655	*/
656	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
657
658	if (lanes <= 2)
659	value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
660	SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
661	else
662	value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
663	SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
664
665	if (lanes <= 1)
666	value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
667	else
668	value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
669
670	if (lanes == 0)
671	value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
672	else
673	value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
674
675	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
676
677	/* start lane sequencer */
678	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
679	SOR_LANE_SEQ_CTL_POWER_STATE_UP;
680	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
681
682	timeout = jiffies + msecs_to_jiffies(m: 250);
683
684	while (time_before(jiffies, timeout)) {
685	value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
686	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
687	break;
688
689	usleep_range(min: 250, max: 1000);
690	}
691
692	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
693	return -ETIMEDOUT;
694
695	return 0;
696	}
697
698	static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
699	{
700	unsigned long timeout;
701	u32 value;
702
703	/* power down all lanes */
704	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
705	value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
706	SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
707	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
708
709	/* start lane sequencer */
710	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
711	SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
712	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
713
714	timeout = jiffies + msecs_to_jiffies(m: 250);
715
716	while (time_before(jiffies, timeout)) {
717	value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
718	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
719	break;
720
721	usleep_range(min: 25, max: 100);
722	}
723
724	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
725	return -ETIMEDOUT;
726
727	return 0;
728	}
729
730	static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
731	{
732	u32 value;
733
734	/* pre-charge all used lanes */
735	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
736
737	if (lanes <= 2)
738	value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
739	SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
740	else
741	value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
742	SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
743
744	if (lanes <= 1)
745	value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
746	else
747	value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
748
749	if (lanes == 0)
750	value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
751	else
752	value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
753
754	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
755
756	usleep_range(min: 15, max: 100);
757
758	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
759	value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
760	SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
761	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
762	}
763
764	static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
765	{
766	u32 mask = 0x08, adj = 0, value;
767
768	/* enable pad calibration logic */
769	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
770	value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
771	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
772
773	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
774	value |= SOR_PLL1_TMDS_TERM;
775	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll1);
776
777	while (mask) {
778	adj |= mask;
779
780	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
781	value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
782	value |= SOR_PLL1_TMDS_TERMADJ(adj);
783	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll1);
784
785	usleep_range(min: 100, max: 200);
786
787	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
788	if (value & SOR_PLL1_TERM_COMPOUT)
789	adj &= ~mask;
790
791	mask >>= 1;
792	}
793
794	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
795	value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
796	value |= SOR_PLL1_TMDS_TERMADJ(adj);
797	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll1);
798
799	/* disable pad calibration logic */
800	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
801	value |= SOR_DP_PADCTL_PAD_CAL_PD;
802	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
803	}
804
805	static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
806	{
807	struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
808	u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
809	const struct tegra_sor_soc *soc = sor->soc;
810	u32 pattern = 0, tx_pu = 0, value;
811	unsigned int i;
812
813	for (value = 0, i = 0; i < link->lanes; i++) {
814	u8 vs = link->train.request.voltage_swing[i];
815	u8 pe = link->train.request.pre_emphasis[i];
816	u8 pc = link->train.request.post_cursor[i];
817	u8 shift = sor->soc->lane_map[i] << 3;
818
819	voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
820	pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
821	post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
822
823	if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
824	tx_pu = sor->soc->tx_pu[pc][vs][pe];
825
826	switch (link->train.pattern) {
827	case DP_TRAINING_PATTERN_DISABLE:
828	value = SOR_DP_TPG_SCRAMBLER_GALIOS |
829	SOR_DP_TPG_PATTERN_NONE;
830	break;
831
832	case DP_TRAINING_PATTERN_1:
833	value = SOR_DP_TPG_SCRAMBLER_NONE |
834	SOR_DP_TPG_PATTERN_TRAIN1;
835	break;
836
837	case DP_TRAINING_PATTERN_2:
838	value = SOR_DP_TPG_SCRAMBLER_NONE |
839	SOR_DP_TPG_PATTERN_TRAIN2;
840	break;
841
842	case DP_TRAINING_PATTERN_3:
843	value = SOR_DP_TPG_SCRAMBLER_NONE |
844	SOR_DP_TPG_PATTERN_TRAIN3;
845	break;
846
847	default:
848	return -EINVAL;
849	}
850
851	if (link->caps.channel_coding)
852	value |= SOR_DP_TPG_CHANNEL_CODING;
853
854	pattern = pattern << 8 | value;
855	}
856
857	tegra_sor_writel(sor, value: voltage_swing, SOR_LANE_DRIVE_CURRENT0);
858	tegra_sor_writel(sor, value: pre_emphasis, SOR_LANE_PREEMPHASIS0);
859
860	if (link->caps.tps3_supported)
861	tegra_sor_writel(sor, value: post_cursor, SOR_LANE_POSTCURSOR0);
862
863	tegra_sor_writel(sor, value: pattern, SOR_DP_TPG);
864
865	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
866	value &= ~SOR_DP_PADCTL_TX_PU_MASK;
867	value |= SOR_DP_PADCTL_TX_PU_ENABLE;
868	value |= SOR_DP_PADCTL_TX_PU(tx_pu);
869	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
870
871	usleep_range(min: 20, max: 100);
872
873	return 0;
874	}
875
876	static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
877	{
878	struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
879	unsigned int rate, lanes;
880	u32 value;
881	int err;
882
883	rate = drm_dp_link_rate_to_bw_code(link_rate: link->rate);
884	lanes = link->lanes;
885
886	/* configure link speed and lane count */
887	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
888	value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
889	value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
890	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
891
892	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
893	value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
894	value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
895
896	if (link->caps.enhanced_framing)
897	value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
898
899	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
900
901	usleep_range(min: 400, max: 1000);
902
903	/* configure load pulse position adjustment */
904	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
905	value &= ~SOR_PLL1_LOADADJ_MASK;
906
907	switch (rate) {
908	case DP_LINK_BW_1_62:
909	value |= SOR_PLL1_LOADADJ(0x3);
910	break;
911
912	case DP_LINK_BW_2_7:
913	value |= SOR_PLL1_LOADADJ(0x4);
914	break;
915
916	case DP_LINK_BW_5_4:
917	value |= SOR_PLL1_LOADADJ(0x6);
918	break;
919	}
920
921	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll1);
922
923	/* use alternate scrambler reset for eDP */
924	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
925
926	if (link->edp == 0)
927	value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
928	else
929	value |= SOR_DP_SPARE_PANEL_INTERNAL;
930
931	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
932
933	err = tegra_sor_power_down_lanes(sor);
934	if (err < 0) {
935	dev_err(sor->dev, "failed to power down lanes: %d\n", err);
936	return err;
937	}
938
939	/* power up and pre-charge lanes */
940	err = tegra_sor_power_up_lanes(sor, lanes);
941	if (err < 0) {
942	dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
943	lanes, (lanes != 1) ? "s" : "", err);
944	return err;
945	}
946
947	tegra_sor_dp_precharge(sor, lanes);
948
949	return 0;
950	}
951
952	static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
953	.apply_training = tegra_sor_dp_link_apply_training,
954	.configure = tegra_sor_dp_link_configure,
955	};
956
957	static void tegra_sor_super_update(struct tegra_sor *sor)
958	{
959	tegra_sor_writel(sor, value: 0, SOR_SUPER_STATE0);
960	tegra_sor_writel(sor, value: 1, SOR_SUPER_STATE0);
961	tegra_sor_writel(sor, value: 0, SOR_SUPER_STATE0);
962	}
963
964	static void tegra_sor_update(struct tegra_sor *sor)
965	{
966	tegra_sor_writel(sor, value: 0, SOR_STATE0);
967	tegra_sor_writel(sor, value: 1, SOR_STATE0);
968	tegra_sor_writel(sor, value: 0, SOR_STATE0);
969	}
970
971	static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
972	{
973	u32 value;
974
975	value = tegra_sor_readl(sor, SOR_PWM_DIV);
976	value &= ~SOR_PWM_DIV_MASK;
977	value |= 0x400; /* period */
978	tegra_sor_writel(sor, value, SOR_PWM_DIV);
979
980	value = tegra_sor_readl(sor, SOR_PWM_CTL);
981	value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
982	value |= 0x400; /* duty cycle */
983	value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
984	value |= SOR_PWM_CTL_TRIGGER;
985	tegra_sor_writel(sor, value, SOR_PWM_CTL);
986
987	timeout = jiffies + msecs_to_jiffies(m: timeout);
988
989	while (time_before(jiffies, timeout)) {
990	value = tegra_sor_readl(sor, SOR_PWM_CTL);
991	if ((value & SOR_PWM_CTL_TRIGGER) == 0)
992	return 0;
993
994	usleep_range(min: 25, max: 100);
995	}
996
997	return -ETIMEDOUT;
998	}
999
1000	static int tegra_sor_attach(struct tegra_sor *sor)
1001	{
1002	unsigned long value, timeout;
1003
1004	/* wake up in normal mode */
1005	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1006	value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1007	value |= SOR_SUPER_STATE_MODE_NORMAL;
1008	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1009	tegra_sor_super_update(sor);
1010
1011	/* attach */
1012	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1013	value |= SOR_SUPER_STATE_ATTACHED;
1014	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1015	tegra_sor_super_update(sor);
1016
1017	timeout = jiffies + msecs_to_jiffies(m: 250);
1018
1019	while (time_before(jiffies, timeout)) {
1020	value = tegra_sor_readl(sor, SOR_TEST);
1021	if ((value & SOR_TEST_ATTACHED) != 0)
1022	return 0;
1023
1024	usleep_range(min: 25, max: 100);
1025	}
1026
1027	return -ETIMEDOUT;
1028	}
1029
1030	static int tegra_sor_wakeup(struct tegra_sor *sor)
1031	{
1032	unsigned long value, timeout;
1033
1034	timeout = jiffies + msecs_to_jiffies(m: 250);
1035
1036	/* wait for head to wake up */
1037	while (time_before(jiffies, timeout)) {
1038	value = tegra_sor_readl(sor, SOR_TEST);
1039	value &= SOR_TEST_HEAD_MODE_MASK;
1040
1041	if (value == SOR_TEST_HEAD_MODE_AWAKE)
1042	return 0;
1043
1044	usleep_range(min: 25, max: 100);
1045	}
1046
1047	return -ETIMEDOUT;
1048	}
1049
1050	static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1051	{
1052	u32 value;
1053
1054	value = tegra_sor_readl(sor, SOR_PWR);
1055	value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1056	tegra_sor_writel(sor, value, SOR_PWR);
1057
1058	timeout = jiffies + msecs_to_jiffies(m: timeout);
1059
1060	while (time_before(jiffies, timeout)) {
1061	value = tegra_sor_readl(sor, SOR_PWR);
1062	if ((value & SOR_PWR_TRIGGER) == 0)
1063	return 0;
1064
1065	usleep_range(min: 25, max: 100);
1066	}
1067
1068	return -ETIMEDOUT;
1069	}
1070
1071	struct tegra_sor_params {
1072	/* number of link clocks per line */
1073	unsigned int num_clocks;
1074	/* ratio between input and output */
1075	u64 ratio;
1076	/* precision factor */
1077	u64 precision;
1078
1079	unsigned int active_polarity;
1080	unsigned int active_count;
1081	unsigned int active_frac;
1082	unsigned int tu_size;
1083	unsigned int error;
1084	};
1085
1086	static int tegra_sor_compute_params(struct tegra_sor *sor,
1087	struct tegra_sor_params *params,
1088	unsigned int tu_size)
1089	{
1090	u64 active_sym, active_count, frac, approx;
1091	u32 active_polarity, active_frac = 0;
1092	const u64 f = params->precision;
1093	s64 error;
1094
1095	active_sym = params->ratio * tu_size;
1096	active_count = div_u64(dividend: active_sym, divisor: f) * f;
1097	frac = active_sym - active_count;
1098
1099	/* fraction < 0.5 */
1100	if (frac >= (f / 2)) {
1101	active_polarity = 1;
1102	frac = f - frac;
1103	} else {
1104	active_polarity = 0;
1105	}
1106
1107	if (frac != 0) {
1108	frac = div_u64(dividend: f * f, divisor: frac); /* 1/fraction */
1109	if (frac <= (15 * f)) {
1110	active_frac = div_u64(dividend: frac, divisor: f);
1111
1112	/* round up */
1113	if (active_polarity)
1114	active_frac++;
1115	} else {
1116	active_frac = active_polarity ? 1 : 15;
1117	}
1118	}
1119
1120	if (active_frac == 1)
1121	active_polarity = 0;
1122
1123	if (active_polarity == 1) {
1124	if (active_frac) {
1125	approx = active_count + (active_frac * (f - 1)) * f;
1126	approx = div_u64(dividend: approx, divisor: active_frac * f);
1127	} else {
1128	approx = active_count + f;
1129	}
1130	} else {
1131	if (active_frac)
1132	approx = active_count + div_u64(dividend: f, divisor: active_frac);
1133	else
1134	approx = active_count;
1135	}
1136
1137	error = div_s64(dividend: active_sym - approx, divisor: tu_size);
1138	error *= params->num_clocks;
1139
1140	if (error <= 0 && abs(error) < params->error) {
1141	params->active_count = div_u64(dividend: active_count, divisor: f);
1142	params->active_polarity = active_polarity;
1143	params->active_frac = active_frac;
1144	params->error = abs(error);
1145	params->tu_size = tu_size;
1146
1147	if (error == 0)
1148	return true;
1149	}
1150
1151	return false;
1152	}
1153
1154	static int tegra_sor_compute_config(struct tegra_sor *sor,
1155	const struct drm_display_mode *mode,
1156	struct tegra_sor_config *config,
1157	struct drm_dp_link *link)
1158	{
1159	const u64 f = 100000, link_rate = link->rate * 1000;
1160	const u64 pclk = (u64)mode->clock * 1000;
1161	u64 input, output, watermark, num;
1162	struct tegra_sor_params params;
1163	u32 num_syms_per_line;
1164	unsigned int i;
1165
1166	if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1167	return -EINVAL;
1168
1169	input = pclk * config->bits_per_pixel;
1170	output = link_rate * 8 * link->lanes;
1171
1172	if (input >= output)
1173	return -ERANGE;
1174
1175	memset(&params, 0, sizeof(params));
1176	params.ratio = div64_u64(dividend: input * f, divisor: output);
1177	params.num_clocks = div_u64(dividend: link_rate * mode->hdisplay, divisor: pclk);
1178	params.precision = f;
1179	params.error = 64 * f;
1180	params.tu_size = 64;
1181
1182	for (i = params.tu_size; i >= 32; i--)
1183	if (tegra_sor_compute_params(sor, params: &params, tu_size: i))
1184	break;
1185
1186	if (params.active_frac == 0) {
1187	config->active_polarity = 0;
1188	config->active_count = params.active_count;
1189
1190	if (!params.active_polarity)
1191	config->active_count--;
1192
1193	config->tu_size = params.tu_size;
1194	config->active_frac = 1;
1195	} else {
1196	config->active_polarity = params.active_polarity;
1197	config->active_count = params.active_count;
1198	config->active_frac = params.active_frac;
1199	config->tu_size = params.tu_size;
1200	}
1201
1202	dev_dbg(sor->dev,
1203	"polarity: %d active count: %d tu size: %d active frac: %d\n",
1204	config->active_polarity, config->active_count,
1205	config->tu_size, config->active_frac);
1206
1207	watermark = params.ratio * config->tu_size * (f - params.ratio);
1208	watermark = div_u64(dividend: watermark, divisor: f);
1209
1210	watermark = div_u64(dividend: watermark + params.error, divisor: f);
1211	config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1212	num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1213	(link->lanes * 8);
1214
1215	if (config->watermark > 30) {
1216	config->watermark = 30;
1217	dev_err(sor->dev,
1218	"unable to compute TU size, forcing watermark to %u\n",
1219	config->watermark);
1220	} else if (config->watermark > num_syms_per_line) {
1221	config->watermark = num_syms_per_line;
1222	dev_err(sor->dev, "watermark too high, forcing to %u\n",
1223	config->watermark);
1224	}
1225
1226	/* compute the number of symbols per horizontal blanking interval */
1227	num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1228	config->hblank_symbols = div_u64(dividend: num, divisor: pclk);
1229
1230	if (link->caps.enhanced_framing)
1231	config->hblank_symbols -= 3;
1232
1233	config->hblank_symbols -= 12 / link->lanes;
1234
1235	/* compute the number of symbols per vertical blanking interval */
1236	num = (mode->hdisplay - 25) * link_rate;
1237	config->vblank_symbols = div_u64(dividend: num, divisor: pclk);
1238	config->vblank_symbols -= 36 / link->lanes + 4;
1239
1240	dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1241	config->vblank_symbols);
1242
1243	return 0;
1244	}
1245
1246	static void tegra_sor_apply_config(struct tegra_sor *sor,
1247	const struct tegra_sor_config *config)
1248	{
1249	u32 value;
1250
1251	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1252	value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1253	value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1254	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1255
1256	value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1257	value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1258	value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1259
1260	value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1261	value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1262
1263	value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1264	value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1265
1266	if (config->active_polarity)
1267	value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1268	else
1269	value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1270
1271	value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1272	value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1273	tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1274
1275	value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1276	value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1277	value |= config->hblank_symbols & 0xffff;
1278	tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1279
1280	value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1281	value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1282	value |= config->vblank_symbols & 0xffff;
1283	tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1284	}
1285
1286	static void tegra_sor_mode_set(struct tegra_sor *sor,
1287	const struct drm_display_mode *mode,
1288	struct tegra_sor_state *state)
1289	{
1290	struct tegra_dc *dc = to_tegra_dc(crtc: sor->output.encoder.crtc);
1291	unsigned int vbe, vse, hbe, hse, vbs, hbs;
1292	u32 value;
1293
1294	value = tegra_sor_readl(sor, SOR_STATE1);
1295	value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1296	value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1297	value &= ~SOR_STATE_ASY_OWNER_MASK;
1298
1299	value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1300	SOR_STATE_ASY_OWNER(dc->pipe + 1);
1301
1302	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1303	value &= ~SOR_STATE_ASY_HSYNCPOL;
1304
1305	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1306	value |= SOR_STATE_ASY_HSYNCPOL;
1307
1308	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1309	value &= ~SOR_STATE_ASY_VSYNCPOL;
1310
1311	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1312	value |= SOR_STATE_ASY_VSYNCPOL;
1313
1314	switch (state->bpc) {
1315	case 16:
1316	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1317	break;
1318
1319	case 12:
1320	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1321	break;
1322
1323	case 10:
1324	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1325	break;
1326
1327	case 8:
1328	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1329	break;
1330
1331	case 6:
1332	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1333	break;
1334
1335	default:
1336	value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1337	break;
1338	}
1339
1340	tegra_sor_writel(sor, value, SOR_STATE1);
1341
1342	/*
1343	* TODO: The video timing programming below doesn't seem to match the
1344	* register definitions.
1345	*/
1346
1347	value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1348	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state1 + dc->pipe);
1349
1350	/* sync end = sync width - 1 */
1351	vse = mode->vsync_end - mode->vsync_start - 1;
1352	hse = mode->hsync_end - mode->hsync_start - 1;
1353
1354	value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1355	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state2 + dc->pipe);
1356
1357	/* blank end = sync end + back porch */
1358	vbe = vse + (mode->vtotal - mode->vsync_end);
1359	hbe = hse + (mode->htotal - mode->hsync_end);
1360
1361	value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1362	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state3 + dc->pipe);
1363
1364	/* blank start = blank end + active */
1365	vbs = vbe + mode->vdisplay;
1366	hbs = hbe + mode->hdisplay;
1367
1368	value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1369	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state4 + dc->pipe);
1370
1371	/* XXX interlacing support */
1372	tegra_sor_writel(sor, value: 0x001, offset: sor->soc->regs->head_state5 + dc->pipe);
1373	}
1374
1375	static int tegra_sor_detach(struct tegra_sor *sor)
1376	{
1377	unsigned long value, timeout;
1378
1379	/* switch to safe mode */
1380	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1381	value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1382	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1383	tegra_sor_super_update(sor);
1384
1385	timeout = jiffies + msecs_to_jiffies(m: 250);
1386
1387	while (time_before(jiffies, timeout)) {
1388	value = tegra_sor_readl(sor, SOR_PWR);
1389	if (value & SOR_PWR_MODE_SAFE)
1390	break;
1391	}
1392
1393	if ((value & SOR_PWR_MODE_SAFE) == 0)
1394	return -ETIMEDOUT;
1395
1396	/* go to sleep */
1397	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1398	value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1399	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1400	tegra_sor_super_update(sor);
1401
1402	/* detach */
1403	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1404	value &= ~SOR_SUPER_STATE_ATTACHED;
1405	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1406	tegra_sor_super_update(sor);
1407
1408	timeout = jiffies + msecs_to_jiffies(m: 250);
1409
1410	while (time_before(jiffies, timeout)) {
1411	value = tegra_sor_readl(sor, SOR_TEST);
1412	if ((value & SOR_TEST_ATTACHED) == 0)
1413	break;
1414
1415	usleep_range(min: 25, max: 100);
1416	}
1417
1418	if ((value & SOR_TEST_ATTACHED) != 0)
1419	return -ETIMEDOUT;
1420
1421	return 0;
1422	}
1423
1424	static int tegra_sor_power_down(struct tegra_sor *sor)
1425	{
1426	unsigned long value, timeout;
1427	int err;
1428
1429	value = tegra_sor_readl(sor, SOR_PWR);
1430	value &= ~SOR_PWR_NORMAL_STATE_PU;
1431	value |= SOR_PWR_TRIGGER;
1432	tegra_sor_writel(sor, value, SOR_PWR);
1433
1434	timeout = jiffies + msecs_to_jiffies(m: 250);
1435
1436	while (time_before(jiffies, timeout)) {
1437	value = tegra_sor_readl(sor, SOR_PWR);
1438	if ((value & SOR_PWR_TRIGGER) == 0)
1439	return 0;
1440
1441	usleep_range(min: 25, max: 100);
1442	}
1443
1444	if ((value & SOR_PWR_TRIGGER) != 0)
1445	return -ETIMEDOUT;
1446
1447	/* switch to safe parent clock */
1448	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_safe);
1449	if (err < 0) {
1450	dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1451	return err;
1452	}
1453
1454	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
1455	value |= SOR_PLL2_PORT_POWERDOWN;
1456	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
1457
1458	usleep_range(min: 20, max: 100);
1459
1460	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll0);
1461	value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1462	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll0);
1463
1464	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
1465	value |= SOR_PLL2_SEQ_PLLCAPPD;
1466	value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1467	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
1468
1469	usleep_range(min: 20, max: 100);
1470
1471	return 0;
1472	}
1473
1474	static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1475	{
1476	u32 value;
1477
1478	timeout = jiffies + msecs_to_jiffies(m: timeout);
1479
1480	while (time_before(jiffies, timeout)) {
1481	value = tegra_sor_readl(sor, SOR_CRCA);
1482	if (value & SOR_CRCA_VALID)
1483	return 0;
1484
1485	usleep_range(min: 100, max: 200);
1486	}
1487
1488	return -ETIMEDOUT;
1489	}
1490
1491	static int tegra_sor_show_crc(struct seq_file *s, void *data)
1492	{
1493	struct drm_info_node *node = s->private;
1494	struct tegra_sor *sor = node->info_ent->data;
1495	struct drm_crtc *crtc = sor->output.encoder.crtc;
1496	struct drm_device *drm = node->minor->dev;
1497	int err = 0;
1498	u32 value;
1499
1500	drm_modeset_lock_all(dev: drm);
1501
1502	if (!crtc || !crtc->state->active) {
1503	err = -EBUSY;
1504	goto unlock;
1505	}
1506
1507	value = tegra_sor_readl(sor, SOR_STATE1);
1508	value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1509	tegra_sor_writel(sor, value, SOR_STATE1);
1510
1511	value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1512	value |= SOR_CRC_CNTRL_ENABLE;
1513	tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1514
1515	value = tegra_sor_readl(sor, SOR_TEST);
1516	value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1517	tegra_sor_writel(sor, value, SOR_TEST);
1518
1519	err = tegra_sor_crc_wait(sor, timeout: 100);
1520	if (err < 0)
1521	goto unlock;
1522
1523	tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1524	value = tegra_sor_readl(sor, SOR_CRCB);
1525
1526	seq_printf(m: s, fmt: "%08x\n", value);
1527
1528	unlock:
1529	drm_modeset_unlock_all(dev: drm);
1530	return err;
1531	}
1532
1533	#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1534
1535	static const struct debugfs_reg32 tegra_sor_regs[] = {
1536	DEBUGFS_REG32(SOR_CTXSW),
1537	DEBUGFS_REG32(SOR_SUPER_STATE0),
1538	DEBUGFS_REG32(SOR_SUPER_STATE1),
1539	DEBUGFS_REG32(SOR_STATE0),
1540	DEBUGFS_REG32(SOR_STATE1),
1541	DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1542	DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1543	DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1544	DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1545	DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1546	DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1547	DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1548	DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1549	DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1550	DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1551	DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1552	DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1553	DEBUGFS_REG32(SOR_CRC_CNTRL),
1554	DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1555	DEBUGFS_REG32(SOR_CLK_CNTRL),
1556	DEBUGFS_REG32(SOR_CAP),
1557	DEBUGFS_REG32(SOR_PWR),
1558	DEBUGFS_REG32(SOR_TEST),
1559	DEBUGFS_REG32(SOR_PLL0),
1560	DEBUGFS_REG32(SOR_PLL1),
1561	DEBUGFS_REG32(SOR_PLL2),
1562	DEBUGFS_REG32(SOR_PLL3),
1563	DEBUGFS_REG32(SOR_CSTM),
1564	DEBUGFS_REG32(SOR_LVDS),
1565	DEBUGFS_REG32(SOR_CRCA),
1566	DEBUGFS_REG32(SOR_CRCB),
1567	DEBUGFS_REG32(SOR_BLANK),
1568	DEBUGFS_REG32(SOR_SEQ_CTL),
1569	DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1570	DEBUGFS_REG32(SOR_SEQ_INST(0)),
1571	DEBUGFS_REG32(SOR_SEQ_INST(1)),
1572	DEBUGFS_REG32(SOR_SEQ_INST(2)),
1573	DEBUGFS_REG32(SOR_SEQ_INST(3)),
1574	DEBUGFS_REG32(SOR_SEQ_INST(4)),
1575	DEBUGFS_REG32(SOR_SEQ_INST(5)),
1576	DEBUGFS_REG32(SOR_SEQ_INST(6)),
1577	DEBUGFS_REG32(SOR_SEQ_INST(7)),
1578	DEBUGFS_REG32(SOR_SEQ_INST(8)),
1579	DEBUGFS_REG32(SOR_SEQ_INST(9)),
1580	DEBUGFS_REG32(SOR_SEQ_INST(10)),
1581	DEBUGFS_REG32(SOR_SEQ_INST(11)),
1582	DEBUGFS_REG32(SOR_SEQ_INST(12)),
1583	DEBUGFS_REG32(SOR_SEQ_INST(13)),
1584	DEBUGFS_REG32(SOR_SEQ_INST(14)),
1585	DEBUGFS_REG32(SOR_SEQ_INST(15)),
1586	DEBUGFS_REG32(SOR_PWM_DIV),
1587	DEBUGFS_REG32(SOR_PWM_CTL),
1588	DEBUGFS_REG32(SOR_VCRC_A0),
1589	DEBUGFS_REG32(SOR_VCRC_A1),
1590	DEBUGFS_REG32(SOR_VCRC_B0),
1591	DEBUGFS_REG32(SOR_VCRC_B1),
1592	DEBUGFS_REG32(SOR_CCRC_A0),
1593	DEBUGFS_REG32(SOR_CCRC_A1),
1594	DEBUGFS_REG32(SOR_CCRC_B0),
1595	DEBUGFS_REG32(SOR_CCRC_B1),
1596	DEBUGFS_REG32(SOR_EDATA_A0),
1597	DEBUGFS_REG32(SOR_EDATA_A1),
1598	DEBUGFS_REG32(SOR_EDATA_B0),
1599	DEBUGFS_REG32(SOR_EDATA_B1),
1600	DEBUGFS_REG32(SOR_COUNT_A0),
1601	DEBUGFS_REG32(SOR_COUNT_A1),
1602	DEBUGFS_REG32(SOR_COUNT_B0),
1603	DEBUGFS_REG32(SOR_COUNT_B1),
1604	DEBUGFS_REG32(SOR_DEBUG_A0),
1605	DEBUGFS_REG32(SOR_DEBUG_A1),
1606	DEBUGFS_REG32(SOR_DEBUG_B0),
1607	DEBUGFS_REG32(SOR_DEBUG_B1),
1608	DEBUGFS_REG32(SOR_TRIG),
1609	DEBUGFS_REG32(SOR_MSCHECK),
1610	DEBUGFS_REG32(SOR_XBAR_CTRL),
1611	DEBUGFS_REG32(SOR_XBAR_POL),
1612	DEBUGFS_REG32(SOR_DP_LINKCTL0),
1613	DEBUGFS_REG32(SOR_DP_LINKCTL1),
1614	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1615	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1616	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1617	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1618	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1619	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1620	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1621	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1622	DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1623	DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1624	DEBUGFS_REG32(SOR_DP_CONFIG0),
1625	DEBUGFS_REG32(SOR_DP_CONFIG1),
1626	DEBUGFS_REG32(SOR_DP_MN0),
1627	DEBUGFS_REG32(SOR_DP_MN1),
1628	DEBUGFS_REG32(SOR_DP_PADCTL0),
1629	DEBUGFS_REG32(SOR_DP_PADCTL1),
1630	DEBUGFS_REG32(SOR_DP_PADCTL2),
1631	DEBUGFS_REG32(SOR_DP_DEBUG0),
1632	DEBUGFS_REG32(SOR_DP_DEBUG1),
1633	DEBUGFS_REG32(SOR_DP_SPARE0),
1634	DEBUGFS_REG32(SOR_DP_SPARE1),
1635	DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1636	DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1637	DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1638	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1639	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1640	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1641	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1642	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1643	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1644	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1645	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1646	DEBUGFS_REG32(SOR_DP_TPG),
1647	DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1648	DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1649	DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1650	DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1651	};
1652
1653	static int tegra_sor_show_regs(struct seq_file *s, void *data)
1654	{
1655	struct drm_info_node *node = s->private;
1656	struct tegra_sor *sor = node->info_ent->data;
1657	struct drm_crtc *crtc = sor->output.encoder.crtc;
1658	struct drm_device *drm = node->minor->dev;
1659	unsigned int i;
1660	int err = 0;
1661
1662	drm_modeset_lock_all(dev: drm);
1663
1664	if (!crtc || !crtc->state->active) {
1665	err = -EBUSY;
1666	goto unlock;
1667	}
1668
1669	for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1670	unsigned int offset = tegra_sor_regs[i].offset;
1671
1672	seq_printf(m: s, fmt: "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1673	offset, tegra_sor_readl(sor, offset));
1674	}
1675
1676	unlock:
1677	drm_modeset_unlock_all(dev: drm);
1678	return err;
1679	}
1680
1681	static const struct drm_info_list debugfs_files[] = {
1682	{ "crc", tegra_sor_show_crc, 0, NULL },
1683	{ "regs", tegra_sor_show_regs, 0, NULL },
1684	};
1685
1686	static int tegra_sor_late_register(struct drm_connector *connector)
1687	{
1688	struct tegra_output *output = connector_to_output(c: connector);
1689	unsigned int i, count = ARRAY_SIZE(debugfs_files);
1690	struct drm_minor *minor = connector->dev->primary;
1691	struct dentry *root = connector->debugfs_entry;
1692	struct tegra_sor *sor = to_sor(output);
1693
1694	sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1695	GFP_KERNEL);
1696	if (!sor->debugfs_files)
1697	return -ENOMEM;
1698
1699	for (i = 0; i < count; i++)
1700	sor->debugfs_files[i].data = sor;
1701
1702	drm_debugfs_create_files(files: sor->debugfs_files, count, root, minor);
1703
1704	return 0;
1705	}
1706
1707	static void tegra_sor_early_unregister(struct drm_connector *connector)
1708	{
1709	struct tegra_output *output = connector_to_output(c: connector);
1710	unsigned int count = ARRAY_SIZE(debugfs_files);
1711	struct tegra_sor *sor = to_sor(output);
1712
1713	drm_debugfs_remove_files(files: sor->debugfs_files, count,
1714	root: connector->debugfs_entry,
1715	minor: connector->dev->primary);
1716	kfree(objp: sor->debugfs_files);
1717	sor->debugfs_files = NULL;
1718	}
1719
1720	static void tegra_sor_connector_reset(struct drm_connector *connector)
1721	{
1722	struct tegra_sor_state *state;
1723
1724	state = kzalloc(sizeof(*state), GFP_KERNEL);
1725	if (!state)
1726	return;
1727
1728	if (connector->state) {
1729	__drm_atomic_helper_connector_destroy_state(state: connector->state);
1730	kfree(objp: connector->state);
1731	}
1732
1733	__drm_atomic_helper_connector_reset(connector, conn_state: &state->base);
1734	}
1735
1736	static enum drm_connector_status
1737	tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1738	{
1739	struct tegra_output *output = connector_to_output(c: connector);
1740	struct tegra_sor *sor = to_sor(output);
1741
1742	if (sor->aux)
1743	return drm_dp_aux_detect(aux: sor->aux);
1744
1745	return tegra_output_connector_detect(connector, force);
1746	}
1747
1748	static struct drm_connector_state *
1749	tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1750	{
1751	struct tegra_sor_state *state = to_sor_state(state: connector->state);
1752	struct tegra_sor_state *copy;
1753
1754	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1755	if (!copy)
1756	return NULL;
1757
1758	__drm_atomic_helper_connector_duplicate_state(connector, state: &copy->base);
1759
1760	return &copy->base;
1761	}
1762
1763	static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1764	.reset = tegra_sor_connector_reset,
1765	.detect = tegra_sor_connector_detect,
1766	.fill_modes = drm_helper_probe_single_connector_modes,
1767	.destroy = tegra_output_connector_destroy,
1768	.atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1769	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1770	.late_register = tegra_sor_late_register,
1771	.early_unregister = tegra_sor_early_unregister,
1772	};
1773
1774	static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1775	{
1776	struct tegra_output *output = connector_to_output(c: connector);
1777	struct tegra_sor *sor = to_sor(output);
1778	int err;
1779
1780	if (sor->aux)
1781	drm_dp_aux_enable(aux: sor->aux);
1782
1783	err = tegra_output_connector_get_modes(connector);
1784
1785	if (sor->aux)
1786	drm_dp_aux_disable(aux: sor->aux);
1787
1788	return err;
1789	}
1790
1791	static enum drm_mode_status
1792	tegra_sor_connector_mode_valid(struct drm_connector *connector,
1793	const struct drm_display_mode *mode)
1794	{
1795	return MODE_OK;
1796	}
1797
1798	static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1799	.get_modes = tegra_sor_connector_get_modes,
1800	.mode_valid = tegra_sor_connector_mode_valid,
1801	};
1802
1803	static int
1804	tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1805	struct drm_crtc_state *crtc_state,
1806	struct drm_connector_state *conn_state)
1807	{
1808	struct tegra_output *output = encoder_to_output(e: encoder);
1809	struct tegra_sor_state *state = to_sor_state(state: conn_state);
1810	struct tegra_dc *dc = to_tegra_dc(crtc: conn_state->crtc);
1811	unsigned long pclk = crtc_state->mode.clock * 1000;
1812	struct tegra_sor *sor = to_sor(output);
1813	struct drm_display_info *info;
1814	int err;
1815
1816	info = &output->connector.display_info;
1817
1818	/*
1819	* For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1820	* the pixel clock must be corrected accordingly.
1821	*/
1822	if (pclk >= 340000000) {
1823	state->link_speed = 20;
1824	state->pclk = pclk / 2;
1825	} else {
1826	state->link_speed = 10;
1827	state->pclk = pclk;
1828	}
1829
1830	err = tegra_dc_state_setup_clock(dc, crtc_state, clk: sor->clk_parent,
1831	pclk, div: 0);
1832	if (err < 0) {
1833	dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1834	return err;
1835	}
1836
1837	switch (info->bpc) {
1838	case 8:
1839	case 6:
1840	state->bpc = info->bpc;
1841	break;
1842
1843	default:
1844	DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1845	state->bpc = 8;
1846	break;
1847	}
1848
1849	return 0;
1850	}
1851
1852	static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1853	{
1854	u32 value = 0;
1855	size_t i;
1856
1857	for (i = size; i > 0; i--)
1858	value = (value << 8) | ptr[i - 1];
1859
1860	return value;
1861	}
1862
1863	static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1864	const void *data, size_t size)
1865	{
1866	const u8 *ptr = data;
1867	unsigned long offset;
1868	size_t i;
1869	u32 value;
1870
1871	switch (ptr[0]) {
1872	case HDMI_INFOFRAME_TYPE_AVI:
1873	offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1874	break;
1875
1876	case HDMI_INFOFRAME_TYPE_AUDIO:
1877	offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1878	break;
1879
1880	case HDMI_INFOFRAME_TYPE_VENDOR:
1881	offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1882	break;
1883
1884	default:
1885	dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1886	ptr[0]);
1887	return;
1888	}
1889
1890	value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1891	INFOFRAME_HEADER_VERSION(ptr[1]) |
1892	INFOFRAME_HEADER_LEN(ptr[2]);
1893	tegra_sor_writel(sor, value, offset);
1894	offset++;
1895
1896	/*
1897	* Each subpack contains 7 bytes, divided into:
1898	* - subpack_low: bytes 0 - 3
1899	* - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1900	*/
1901	for (i = 3; i < size; i += 7) {
1902	size_t rem = size - i, num = min_t(size_t, rem, 4);
1903
1904	value = tegra_sor_hdmi_subpack(ptr: &ptr[i], size: num);
1905	tegra_sor_writel(sor, value, offset: offset++);
1906
1907	num = min_t(size_t, rem - num, 3);
1908
1909	value = tegra_sor_hdmi_subpack(ptr: &ptr[i + 4], size: num);
1910	tegra_sor_writel(sor, value, offset: offset++);
1911	}
1912	}
1913
1914	static int
1915	tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1916	const struct drm_display_mode *mode)
1917	{
1918	u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1919	struct hdmi_avi_infoframe frame;
1920	u32 value;
1921	int err;
1922
1923	/* disable AVI infoframe */
1924	value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1925	value &= ~INFOFRAME_CTRL_SINGLE;
1926	value &= ~INFOFRAME_CTRL_OTHER;
1927	value &= ~INFOFRAME_CTRL_ENABLE;
1928	tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1929
1930	err = drm_hdmi_avi_infoframe_from_display_mode(frame: &frame,
1931	connector: &sor->output.connector, mode);
1932	if (err < 0) {
1933	dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1934	return err;
1935	}
1936
1937	err = hdmi_avi_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer));
1938	if (err < 0) {
1939	dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1940	return err;
1941	}
1942
1943	tegra_sor_hdmi_write_infopack(sor, data: buffer, size: err);
1944
1945	/* enable AVI infoframe */
1946	value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1947	value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1948	value |= INFOFRAME_CTRL_ENABLE;
1949	tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1950
1951	return 0;
1952	}
1953
1954	static void tegra_sor_write_eld(struct tegra_sor *sor)
1955	{
1956	size_t length = drm_eld_size(eld: sor->output.connector.eld), i;
1957
1958	for (i = 0; i < length; i++)
1959	tegra_sor_writel(sor, value: i << 8 | sor->output.connector.eld[i],
1960	SOR_AUDIO_HDA_ELD_BUFWR);
1961
1962	/*
1963	* The HDA codec will always report an ELD buffer size of 96 bytes and
1964	* the HDA codec driver will check that each byte read from the buffer
1965	* is valid. Therefore every byte must be written, even if no 96 bytes
1966	* were parsed from EDID.
1967	*/
1968	for (i = length; i < 96; i++)
1969	tegra_sor_writel(sor, value: i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1970	}
1971
1972	static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1973	{
1974	u32 value;
1975
1976	/*
1977	* Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1978	* is used for interoperability between the HDA codec driver and the
1979	* HDMI/DP driver.
1980	*/
1981	value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1982	tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1983	tegra_sor_writel(sor, value, SOR_INT_MASK);
1984
1985	tegra_sor_write_eld(sor);
1986
1987	value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1988	tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1989	}
1990
1991	static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1992	{
1993	tegra_sor_writel(sor, value: 0, SOR_AUDIO_HDA_PRESENSE);
1994	tegra_sor_writel(sor, value: 0, SOR_INT_MASK);
1995	tegra_sor_writel(sor, value: 0, SOR_INT_ENABLE);
1996	}
1997
1998	static void tegra_sor_audio_enable(struct tegra_sor *sor)
1999	{
2000	u32 value;
2001
2002	value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2003
2004	/* select HDA audio input */
2005	value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2006	value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2007
2008	/* inject null samples */
2009	if (sor->format.channels != 2)
2010	value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2011	else
2012	value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2013
2014	value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2015
2016	tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2017
2018	/* enable advertising HBR capability */
2019	tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2020	}
2021
2022	static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2023	{
2024	u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2025	struct hdmi_audio_infoframe frame;
2026	u32 value;
2027	int err;
2028
2029	err = hdmi_audio_infoframe_init(frame: &frame);
2030	if (err < 0) {
2031	dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2032	return err;
2033	}
2034
2035	frame.channels = sor->format.channels;
2036
2037	err = hdmi_audio_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer));
2038	if (err < 0) {
2039	dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2040	return err;
2041	}
2042
2043	tegra_sor_hdmi_write_infopack(sor, data: buffer, size: err);
2044
2045	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2046	value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2047	value |= INFOFRAME_CTRL_ENABLE;
2048	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2049
2050	return 0;
2051	}
2052
2053	static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2054	{
2055	u32 value;
2056
2057	tegra_sor_audio_enable(sor);
2058
2059	tegra_sor_writel(sor, value: 0, SOR_HDMI_ACR_CTRL);
2060
2061	value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2062	SOR_HDMI_SPARE_CTS_RESET(1) |
2063	SOR_HDMI_SPARE_HW_CTS_ENABLE;
2064	tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2065
2066	/* enable HW CTS */
2067	value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2068	tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2069
2070	/* allow packet to be sent */
2071	value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2072	tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2073
2074	/* reset N counter and enable lookup */
2075	value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2076	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2077
2078	value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2079	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2080	tegra_sor_writel(sor, value: 4096, SOR_AUDIO_NVAL_0320);
2081
2082	tegra_sor_writel(sor, value: 20000, SOR_AUDIO_AVAL_0441);
2083	tegra_sor_writel(sor, value: 4704, SOR_AUDIO_NVAL_0441);
2084
2085	tegra_sor_writel(sor, value: 20000, SOR_AUDIO_AVAL_0882);
2086	tegra_sor_writel(sor, value: 9408, SOR_AUDIO_NVAL_0882);
2087
2088	tegra_sor_writel(sor, value: 20000, SOR_AUDIO_AVAL_1764);
2089	tegra_sor_writel(sor, value: 18816, SOR_AUDIO_NVAL_1764);
2090
2091	value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2092	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2093	tegra_sor_writel(sor, value: 6144, SOR_AUDIO_NVAL_0480);
2094
2095	value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2096	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2097	tegra_sor_writel(sor, value: 12288, SOR_AUDIO_NVAL_0960);
2098
2099	value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2100	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2101	tegra_sor_writel(sor, value: 24576, SOR_AUDIO_NVAL_1920);
2102
2103	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2104	value &= ~SOR_HDMI_AUDIO_N_RESET;
2105	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2106
2107	tegra_sor_hdmi_enable_audio_infoframe(sor);
2108	}
2109
2110	static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2111	{
2112	u32 value;
2113
2114	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2115	value &= ~INFOFRAME_CTRL_ENABLE;
2116	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2117	}
2118
2119	static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2120	{
2121	tegra_sor_hdmi_disable_audio_infoframe(sor);
2122	}
2123
2124	static struct tegra_sor_hdmi_settings *
2125	tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2126	{
2127	unsigned int i;
2128
2129	for (i = 0; i < sor->num_settings; i++)
2130	if (frequency <= sor->settings[i].frequency)
2131	return &sor->settings[i];
2132
2133	return NULL;
2134	}
2135
2136	static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2137	{
2138	u32 value;
2139
2140	value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2141	value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2142	value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2143	tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2144	}
2145
2146	static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2147	{
2148	drm_scdc_set_high_tmds_clock_ratio(connector: &sor->output.connector, set: false);
2149	drm_scdc_set_scrambling(connector: &sor->output.connector, enable: false);
2150
2151	tegra_sor_hdmi_disable_scrambling(sor);
2152	}
2153
2154	static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2155	{
2156	if (sor->scdc_enabled) {
2157	cancel_delayed_work_sync(dwork: &sor->scdc);
2158	tegra_sor_hdmi_scdc_disable(sor);
2159	}
2160	}
2161
2162	static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2163	{
2164	u32 value;
2165
2166	value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2167	value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2168	value |= SOR_HDMI2_CTRL_SCRAMBLE;
2169	tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2170	}
2171
2172	static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2173	{
2174	drm_scdc_set_high_tmds_clock_ratio(connector: &sor->output.connector, set: true);
2175	drm_scdc_set_scrambling(connector: &sor->output.connector, enable: true);
2176
2177	tegra_sor_hdmi_enable_scrambling(sor);
2178	}
2179
2180	static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2181	{
2182	struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2183
2184	if (!drm_scdc_get_scrambling_status(connector: &sor->output.connector)) {
2185	DRM_DEBUG_KMS("SCDC not scrambled\n");
2186	tegra_sor_hdmi_scdc_enable(sor);
2187	}
2188
2189	schedule_delayed_work(dwork: &sor->scdc, delay: msecs_to_jiffies(m: 5000));
2190	}
2191
2192	static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2193	{
2194	struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2195	struct drm_display_mode *mode;
2196
2197	mode = &sor->output.encoder.crtc->state->adjusted_mode;
2198
2199	if (mode->clock >= 340000 && scdc->supported) {
2200	schedule_delayed_work(dwork: &sor->scdc, delay: msecs_to_jiffies(m: 5000));
2201	tegra_sor_hdmi_scdc_enable(sor);
2202	sor->scdc_enabled = true;
2203	}
2204	}
2205
2206	static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2207	{
2208	struct tegra_output *output = encoder_to_output(e: encoder);
2209	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
2210	struct tegra_sor *sor = to_sor(output);
2211	u32 value;
2212	int err;
2213
2214	tegra_sor_audio_unprepare(sor);
2215	tegra_sor_hdmi_scdc_stop(sor);
2216
2217	err = tegra_sor_detach(sor);
2218	if (err < 0)
2219	dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2220
2221	tegra_sor_writel(sor, value: 0, SOR_STATE1);
2222	tegra_sor_update(sor);
2223
2224	/* disable display to SOR clock */
2225	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2226
2227	if (!sor->soc->has_nvdisplay)
2228	value &= ~SOR1_TIMING_CYA;
2229
2230	value &= ~SOR_ENABLE(sor->index);
2231
2232	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2233
2234	tegra_dc_commit(dc);
2235
2236	err = tegra_sor_power_down(sor);
2237	if (err < 0)
2238	dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2239
2240	err = tegra_io_pad_power_disable(id: sor->pad);
2241	if (err < 0)
2242	dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2243
2244	host1x_client_suspend(client: &sor->client);
2245	}
2246
2247	static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2248	{
2249	struct tegra_output *output = encoder_to_output(e: encoder);
2250	unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2251	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
2252	struct tegra_sor_hdmi_settings *settings;
2253	struct tegra_sor *sor = to_sor(output);
2254	struct tegra_sor_state *state;
2255	struct drm_display_mode *mode;
2256	unsigned long rate, pclk;
2257	unsigned int div, i;
2258	u32 value;
2259	int err;
2260
2261	state = to_sor_state(state: output->connector.state);
2262	mode = &encoder->crtc->state->adjusted_mode;
2263	pclk = mode->clock * 1000;
2264
2265	err = host1x_client_resume(client: &sor->client);
2266	if (err < 0) {
2267	dev_err(sor->dev, "failed to resume: %d\n", err);
2268	return;
2269	}
2270
2271	/* switch to safe parent clock */
2272	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_safe);
2273	if (err < 0) {
2274	dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2275	return;
2276	}
2277
2278	div = clk_get_rate(clk: sor->clk) / 1000000 * 4;
2279
2280	err = tegra_io_pad_power_enable(id: sor->pad);
2281	if (err < 0)
2282	dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2283
2284	usleep_range(min: 20, max: 100);
2285
2286	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2287	value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2288	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2289
2290	usleep_range(min: 20, max: 100);
2291
2292	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll3);
2293	value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2294	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll3);
2295
2296	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll0);
2297	value &= ~SOR_PLL0_VCOPD;
2298	value &= ~SOR_PLL0_PWR;
2299	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll0);
2300
2301	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2302	value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2303	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2304
2305	usleep_range(min: 200, max: 400);
2306
2307	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2308	value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2309	value &= ~SOR_PLL2_PORT_POWERDOWN;
2310	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2311
2312	usleep_range(min: 20, max: 100);
2313
2314	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
2315	value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2316	SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2317	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
2318
2319	while (true) {
2320	value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2321	if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2322	break;
2323
2324	usleep_range(min: 250, max: 1000);
2325	}
2326
2327	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2328	SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2329	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2330
2331	while (true) {
2332	value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2333	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2334	break;
2335
2336	usleep_range(min: 250, max: 1000);
2337	}
2338
2339	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2340	value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2341	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2342
2343	if (mode->clock < 340000) {
2344	DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2345	value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2346	} else {
2347	DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2348	value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2349	}
2350
2351	value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2352	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2353
2354	/* SOR pad PLL stabilization time */
2355	usleep_range(min: 250, max: 1000);
2356
2357	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2358	value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2359	value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2360	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2361
2362	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2363	value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2364	value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2365	value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2366	value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2367	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2368
2369	value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2370	SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2371	tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2372
2373	value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2374	SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2375	tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2376	tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2377
2378	if (!sor->soc->has_nvdisplay) {
2379	/* program the reference clock */
2380	value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2381	tegra_sor_writel(sor, value, SOR_REFCLK);
2382	}
2383
2384	/* XXX not in TRM */
2385	for (value = 0, i = 0; i < 5; i++)
2386	value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2387	SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2388
2389	tegra_sor_writel(sor, value: 0x00000000, SOR_XBAR_POL);
2390	tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2391
2392	/*
2393	* Switch the pad clock to the DP clock. Note that we cannot actually
2394	* do this because Tegra186 and later don't support clk_set_parent()
2395	* on the sorX_pad_clkout clocks. We already do the equivalent above
2396	* using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2397	*/
2398	#if 0
2399	err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2400	if (err < 0) {
2401	dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2402	err);
2403	return;
2404	}
2405	#endif
2406
2407	/* switch the SOR clock to the pad clock */
2408	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_pad);
2409	if (err < 0) {
2410	dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2411	err);
2412	return;
2413	}
2414
2415	/* switch the output clock to the parent pixel clock */
2416	err = clk_set_parent(clk: sor->clk, parent: sor->clk_parent);
2417	if (err < 0) {
2418	dev_err(sor->dev, "failed to select output parent clock: %d\n",
2419	err);
2420	return;
2421	}
2422
2423	/* adjust clock rate for HDMI 2.0 modes */
2424	rate = clk_get_rate(clk: sor->clk_parent);
2425
2426	if (mode->clock >= 340000)
2427	rate /= 2;
2428
2429	DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2430
2431	clk_set_rate(clk: sor->clk, rate);
2432
2433	if (!sor->soc->has_nvdisplay) {
2434	value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2435
2436	/* XXX is this the proper check? */
2437	if (mode->clock < 75000)
2438	value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2439
2440	tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2441	}
2442
2443	max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2444
2445	value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2446	SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2447	tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2448
2449	if (!dc->soc->has_nvdisplay) {
2450	/* H_PULSE2 setup */
2451	pulse_start = h_ref_to_sync +
2452	(mode->hsync_end - mode->hsync_start) +
2453	(mode->htotal - mode->hsync_end) - 10;
2454
2455	value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2456	PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2457	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2458
2459	value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2460	tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2461
2462	value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2463	value |= H_PULSE2_ENABLE;
2464	tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2465	}
2466
2467	/* infoframe setup */
2468	err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2469	if (err < 0)
2470	dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2471
2472	/* XXX HDMI audio support not implemented yet */
2473	tegra_sor_hdmi_disable_audio_infoframe(sor);
2474
2475	/* use single TMDS protocol */
2476	value = tegra_sor_readl(sor, SOR_STATE1);
2477	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2478	value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2479	tegra_sor_writel(sor, value, SOR_STATE1);
2480
2481	/* power up pad calibration */
2482	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
2483	value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2484	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
2485
2486	/* production settings */
2487	settings = tegra_sor_hdmi_find_settings(sor, frequency: mode->clock * 1000);
2488	if (!settings) {
2489	dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2490	mode->clock * 1000);
2491	return;
2492	}
2493
2494	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll0);
2495	value &= ~SOR_PLL0_ICHPMP_MASK;
2496	value &= ~SOR_PLL0_FILTER_MASK;
2497	value &= ~SOR_PLL0_VCOCAP_MASK;
2498	value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2499	value |= SOR_PLL0_FILTER(settings->filter);
2500	value |= SOR_PLL0_VCOCAP(settings->vcocap);
2501	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll0);
2502
2503	/* XXX not in TRM */
2504	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll1);
2505	value &= ~SOR_PLL1_LOADADJ_MASK;
2506	value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2507	value |= SOR_PLL1_LOADADJ(settings->loadadj);
2508	value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2509	value |= SOR_PLL1_TMDS_TERM;
2510	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll1);
2511
2512	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll3);
2513	value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2514	value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2515	value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2516	value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2517	value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2518	value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2519	value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2520	value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2521	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll3);
2522
2523	value = settings->drive_current[3] << 24 |
2524	settings->drive_current[2] << 16 |
2525	settings->drive_current[1] << 8 |
2526	settings->drive_current[0] << 0;
2527	tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2528
2529	value = settings->preemphasis[3] << 24 |
2530	settings->preemphasis[2] << 16 |
2531	settings->preemphasis[1] << 8 |
2532	settings->preemphasis[0] << 0;
2533	tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2534
2535	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
2536	value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2537	value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2538	value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2539	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
2540
2541	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl2);
2542	value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2543	value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2544	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl2);
2545
2546	/* power down pad calibration */
2547	value = tegra_sor_readl(sor, offset: sor->soc->regs->dp_padctl0);
2548	value |= SOR_DP_PADCTL_PAD_CAL_PD;
2549	tegra_sor_writel(sor, value, offset: sor->soc->regs->dp_padctl0);
2550
2551	if (!dc->soc->has_nvdisplay) {
2552	/* miscellaneous display controller settings */
2553	value = VSYNC_H_POSITION(1);
2554	tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2555	}
2556
2557	value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2558	value &= ~DITHER_CONTROL_MASK;
2559	value &= ~BASE_COLOR_SIZE_MASK;
2560
2561	switch (state->bpc) {
2562	case 6:
2563	value |= BASE_COLOR_SIZE_666;
2564	break;
2565
2566	case 8:
2567	value |= BASE_COLOR_SIZE_888;
2568	break;
2569
2570	case 10:
2571	value |= BASE_COLOR_SIZE_101010;
2572	break;
2573
2574	case 12:
2575	value |= BASE_COLOR_SIZE_121212;
2576	break;
2577
2578	default:
2579	WARN(1, "%u bits-per-color not supported\n", state->bpc);
2580	value |= BASE_COLOR_SIZE_888;
2581	break;
2582	}
2583
2584	tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2585
2586	/* XXX set display head owner */
2587	value = tegra_sor_readl(sor, SOR_STATE1);
2588	value &= ~SOR_STATE_ASY_OWNER_MASK;
2589	value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2590	tegra_sor_writel(sor, value, SOR_STATE1);
2591
2592	err = tegra_sor_power_up(sor, timeout: 250);
2593	if (err < 0)
2594	dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2595
2596	/* configure dynamic range of output */
2597	value = tegra_sor_readl(sor, offset: sor->soc->regs->head_state0 + dc->pipe);
2598	value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2599	value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2600	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state0 + dc->pipe);
2601
2602	/* configure colorspace */
2603	value = tegra_sor_readl(sor, offset: sor->soc->regs->head_state0 + dc->pipe);
2604	value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2605	value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2606	tegra_sor_writel(sor, value, offset: sor->soc->regs->head_state0 + dc->pipe);
2607
2608	tegra_sor_mode_set(sor, mode, state);
2609
2610	tegra_sor_update(sor);
2611
2612	/* program preamble timing in SOR (XXX) */
2613	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2614	value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2615	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2616
2617	err = tegra_sor_attach(sor);
2618	if (err < 0)
2619	dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2620
2621	/* enable display to SOR clock and generate HDMI preamble */
2622	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2623
2624	if (!sor->soc->has_nvdisplay)
2625	value |= SOR1_TIMING_CYA;
2626
2627	value |= SOR_ENABLE(sor->index);
2628
2629	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2630
2631	if (dc->soc->has_nvdisplay) {
2632	value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2633	value &= ~PROTOCOL_MASK;
2634	value |= PROTOCOL_SINGLE_TMDS_A;
2635	tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2636	}
2637
2638	tegra_dc_commit(dc);
2639
2640	err = tegra_sor_wakeup(sor);
2641	if (err < 0)
2642	dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2643
2644	tegra_sor_hdmi_scdc_start(sor);
2645	tegra_sor_audio_prepare(sor);
2646	}
2647
2648	static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2649	.disable = tegra_sor_hdmi_disable,
2650	.enable = tegra_sor_hdmi_enable,
2651	.atomic_check = tegra_sor_encoder_atomic_check,
2652	};
2653
2654	static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2655	{
2656	struct tegra_output *output = encoder_to_output(e: encoder);
2657	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
2658	struct tegra_sor *sor = to_sor(output);
2659	u32 value;
2660	int err;
2661
2662	if (output->panel)
2663	drm_panel_disable(panel: output->panel);
2664
2665	/*
2666	* Do not attempt to power down a DP link if we're not connected since
2667	* the AUX transactions would just be timing out.
2668	*/
2669	if (output->connector.status != connector_status_disconnected) {
2670	err = drm_dp_link_power_down(aux: sor->aux, revision: sor->link.revision);
2671	if (err < 0)
2672	dev_err(sor->dev, "failed to power down link: %d\n",
2673	err);
2674	}
2675
2676	err = tegra_sor_detach(sor);
2677	if (err < 0)
2678	dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2679
2680	tegra_sor_writel(sor, value: 0, SOR_STATE1);
2681	tegra_sor_update(sor);
2682
2683	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2684	value &= ~SOR_ENABLE(sor->index);
2685	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2686	tegra_dc_commit(dc);
2687
2688	value = tegra_sor_readl(sor, SOR_STATE1);
2689	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2690	value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2691	value &= ~SOR_STATE_ASY_OWNER_MASK;
2692	tegra_sor_writel(sor, value, SOR_STATE1);
2693	tegra_sor_update(sor);
2694
2695	/* switch to safe parent clock */
2696	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_safe);
2697	if (err < 0)
2698	dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2699
2700	err = tegra_sor_power_down(sor);
2701	if (err < 0)
2702	dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2703
2704	err = tegra_io_pad_power_disable(id: sor->pad);
2705	if (err < 0)
2706	dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2707
2708	err = drm_dp_aux_disable(aux: sor->aux);
2709	if (err < 0)
2710	dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2711
2712	if (output->panel)
2713	drm_panel_unprepare(panel: output->panel);
2714
2715	host1x_client_suspend(client: &sor->client);
2716	}
2717
2718	static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2719	{
2720	struct tegra_output *output = encoder_to_output(e: encoder);
2721	struct tegra_dc *dc = to_tegra_dc(crtc: encoder->crtc);
2722	struct tegra_sor *sor = to_sor(output);
2723	struct tegra_sor_config config;
2724	struct tegra_sor_state *state;
2725	struct drm_display_mode *mode;
2726	struct drm_display_info *info;
2727	unsigned int i;
2728	u32 value;
2729	int err;
2730
2731	state = to_sor_state(state: output->connector.state);
2732	mode = &encoder->crtc->state->adjusted_mode;
2733	info = &output->connector.display_info;
2734
2735	err = host1x_client_resume(client: &sor->client);
2736	if (err < 0) {
2737	dev_err(sor->dev, "failed to resume: %d\n", err);
2738	return;
2739	}
2740
2741	/* switch to safe parent clock */
2742	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_safe);
2743	if (err < 0)
2744	dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2745
2746	err = tegra_io_pad_power_enable(id: sor->pad);
2747	if (err < 0)
2748	dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2749
2750	usleep_range(min: 20, max: 100);
2751
2752	err = drm_dp_aux_enable(aux: sor->aux);
2753	if (err < 0)
2754	dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2755
2756	err = drm_dp_link_probe(aux: sor->aux, link: &sor->link);
2757	if (err < 0)
2758	dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2759
2760	tegra_sor_filter_rates(sor);
2761
2762	err = drm_dp_link_choose(link: &sor->link, mode, info);
2763	if (err < 0)
2764	dev_err(sor->dev, "failed to choose link: %d\n", err);
2765
2766	if (output->panel)
2767	drm_panel_prepare(panel: output->panel);
2768
2769	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2770	value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2771	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2772
2773	usleep_range(min: 20, max: 40);
2774
2775	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll3);
2776	value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2777	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll3);
2778
2779	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll0);
2780	value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2781	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll0);
2782
2783	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2784	value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2785	value |= SOR_PLL2_SEQ_PLLCAPPD;
2786	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2787
2788	usleep_range(min: 200, max: 400);
2789
2790	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll2);
2791	value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2792	value &= ~SOR_PLL2_PORT_POWERDOWN;
2793	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll2);
2794
2795	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2796	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2797
2798	if (output->panel)
2799	value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2800	else
2801	value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2802
2803	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2804
2805	usleep_range(min: 200, max: 400);
2806
2807	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2808	/* XXX not in TRM */
2809	if (output->panel)
2810	value |= SOR_DP_SPARE_PANEL_INTERNAL;
2811	else
2812	value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2813
2814	value |= SOR_DP_SPARE_SEQ_ENABLE;
2815	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2816
2817	/* XXX not in TRM */
2818	tegra_sor_writel(sor, value: 0, SOR_LVDS);
2819
2820	value = tegra_sor_readl(sor, offset: sor->soc->regs->pll0);
2821	value &= ~SOR_PLL0_ICHPMP_MASK;
2822	value &= ~SOR_PLL0_VCOCAP_MASK;
2823	value |= SOR_PLL0_ICHPMP(0x1);
2824	value |= SOR_PLL0_VCOCAP(0x3);
2825	value |= SOR_PLL0_RESISTOR_EXT;
2826	tegra_sor_writel(sor, value, offset: sor->soc->regs->pll0);
2827
2828	/* XXX not in TRM */
2829	for (value = 0, i = 0; i < 5; i++)
2830	value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2831	SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2832
2833	tegra_sor_writel(sor, value: 0x00000000, SOR_XBAR_POL);
2834	tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2835
2836	/*
2837	* Switch the pad clock to the DP clock. Note that we cannot actually
2838	* do this because Tegra186 and later don't support clk_set_parent()
2839	* on the sorX_pad_clkout clocks. We already do the equivalent above
2840	* using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2841	*/
2842	#if 0
2843	err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2844	if (err < 0) {
2845	dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2846	err);
2847	return;
2848	}
2849	#endif
2850
2851	/* switch the SOR clock to the pad clock */
2852	err = tegra_sor_set_parent_clock(sor, parent: sor->clk_pad);
2853	if (err < 0) {
2854	dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2855	err);
2856	return;
2857	}
2858
2859	/* switch the output clock to the parent pixel clock */
2860	err = clk_set_parent(clk: sor->clk, parent: sor->clk_parent);
2861	if (err < 0) {
2862	dev_err(sor->dev, "failed to select output parent clock: %d\n",
2863	err);
2864	return;
2865	}
2866
2867	/* use DP-A protocol */
2868	value = tegra_sor_readl(sor, SOR_STATE1);
2869	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2870	value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2871	tegra_sor_writel(sor, value, SOR_STATE1);
2872
2873	/* enable port */
2874	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2875	value |= SOR_DP_LINKCTL_ENABLE;
2876	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2877
2878	tegra_sor_dp_term_calibrate(sor);
2879
2880	err = drm_dp_link_train(link: &sor->link);
2881	if (err < 0)
2882	dev_err(sor->dev, "link training failed: %d\n", err);
2883	else
2884	dev_dbg(sor->dev, "link training succeeded\n");
2885
2886	err = drm_dp_link_power_up(aux: sor->aux, revision: sor->link.revision);
2887	if (err < 0)
2888	dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2889
2890	/* compute configuration */
2891	memset(&config, 0, sizeof(config));
2892	config.bits_per_pixel = state->bpc * 3;
2893
2894	err = tegra_sor_compute_config(sor, mode, config: &config, link: &sor->link);
2895	if (err < 0)
2896	dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2897
2898	tegra_sor_apply_config(sor, config: &config);
2899	tegra_sor_mode_set(sor, mode, state);
2900
2901	if (output->panel) {
2902	/* CSTM (LVDS, link A/B, upper) */
2903	value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2904	SOR_CSTM_UPPER;
2905	tegra_sor_writel(sor, value, SOR_CSTM);
2906
2907	/* PWM setup */
2908	err = tegra_sor_setup_pwm(sor, timeout: 250);
2909	if (err < 0)
2910	dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2911	}
2912
2913	tegra_sor_update(sor);
2914
2915	err = tegra_sor_power_up(sor, timeout: 250);
2916	if (err < 0)
2917	dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2918
2919	/* attach and wake up */
2920	err = tegra_sor_attach(sor);
2921	if (err < 0)
2922	dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2923
2924	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2925	value |= SOR_ENABLE(sor->index);
2926	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2927
2928	tegra_dc_commit(dc);
2929
2930	err = tegra_sor_wakeup(sor);
2931	if (err < 0)
2932	dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2933
2934	if (output->panel)
2935	drm_panel_enable(panel: output->panel);
2936	}
2937
2938	static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2939	.disable = tegra_sor_dp_disable,
2940	.enable = tegra_sor_dp_enable,
2941	.atomic_check = tegra_sor_encoder_atomic_check,
2942	};
2943
2944	static void tegra_sor_disable_regulator(void *data)
2945	{
2946	struct regulator *reg = data;
2947
2948	regulator_disable(regulator: reg);
2949	}
2950
2951	static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2952	{
2953	int err;
2954
2955	err = regulator_enable(regulator: reg);
2956	if (err)
2957	return err;
2958
2959	return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2960	}
2961
2962	static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2963	{
2964	int err;
2965
2966	sor->avdd_io_supply = devm_regulator_get(dev: sor->dev, id: "avdd-io-hdmi-dp");
2967	if (IS_ERR(ptr: sor->avdd_io_supply))
2968	return dev_err_probe(dev: sor->dev, err: PTR_ERR(ptr: sor->avdd_io_supply),
2969	fmt: "cannot get AVDD I/O supply\n");
2970
2971	err = tegra_sor_enable_regulator(sor, reg: sor->avdd_io_supply);
2972	if (err < 0) {
2973	dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2974	err);
2975	return err;
2976	}
2977
2978	sor->vdd_pll_supply = devm_regulator_get(dev: sor->dev, id: "vdd-hdmi-dp-pll");
2979	if (IS_ERR(ptr: sor->vdd_pll_supply))
2980	return dev_err_probe(dev: sor->dev, err: PTR_ERR(ptr: sor->vdd_pll_supply),
2981	fmt: "cannot get VDD PLL supply\n");
2982
2983	err = tegra_sor_enable_regulator(sor, reg: sor->vdd_pll_supply);
2984	if (err < 0) {
2985	dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2986	err);
2987	return err;
2988	}
2989
2990	sor->hdmi_supply = devm_regulator_get(dev: sor->dev, id: "hdmi");
2991	if (IS_ERR(ptr: sor->hdmi_supply))
2992	return dev_err_probe(dev: sor->dev, err: PTR_ERR(ptr: sor->hdmi_supply),
2993	fmt: "cannot get HDMI supply\n");
2994
2995	err = tegra_sor_enable_regulator(sor, reg: sor->hdmi_supply);
2996	if (err < 0) {
2997	dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2998	return err;
2999	}
3000
3001	INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3002
3003	return 0;
3004	}
3005
3006	static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3007	.name = "HDMI",
3008	.probe = tegra_sor_hdmi_probe,
3009	.audio_enable = tegra_sor_hdmi_audio_enable,
3010	.audio_disable = tegra_sor_hdmi_audio_disable,
3011	};
3012
3013	static int tegra_sor_dp_probe(struct tegra_sor *sor)
3014	{
3015	int err;
3016
3017	sor->avdd_io_supply = devm_regulator_get(dev: sor->dev, id: "avdd-io-hdmi-dp");
3018	if (IS_ERR(ptr: sor->avdd_io_supply))
3019	return PTR_ERR(ptr: sor->avdd_io_supply);
3020
3021	err = tegra_sor_enable_regulator(sor, reg: sor->avdd_io_supply);
3022	if (err < 0)
3023	return err;
3024
3025	sor->vdd_pll_supply = devm_regulator_get(dev: sor->dev, id: "vdd-hdmi-dp-pll");
3026	if (IS_ERR(ptr: sor->vdd_pll_supply))
3027	return PTR_ERR(ptr: sor->vdd_pll_supply);
3028
3029	err = tegra_sor_enable_regulator(sor, reg: sor->vdd_pll_supply);
3030	if (err < 0)
3031	return err;
3032
3033	return 0;
3034	}
3035
3036	static const struct tegra_sor_ops tegra_sor_dp_ops = {
3037	.name = "DP",
3038	.probe = tegra_sor_dp_probe,
3039	};
3040
3041	static int tegra_sor_init(struct host1x_client *client)
3042	{
3043	struct drm_device *drm = dev_get_drvdata(dev: client->host);
3044	const struct drm_encoder_helper_funcs *helpers = NULL;
3045	struct tegra_sor *sor = host1x_client_to_sor(client);
3046	int connector = DRM_MODE_CONNECTOR_Unknown;
3047	int encoder = DRM_MODE_ENCODER_NONE;
3048	int err;
3049
3050	if (!sor->aux) {
3051	if (sor->ops == &tegra_sor_hdmi_ops) {
3052	connector = DRM_MODE_CONNECTOR_HDMIA;
3053	encoder = DRM_MODE_ENCODER_TMDS;
3054	helpers = &tegra_sor_hdmi_helpers;
3055	} else if (sor->soc->supports_lvds) {
3056	connector = DRM_MODE_CONNECTOR_LVDS;
3057	encoder = DRM_MODE_ENCODER_LVDS;
3058	}
3059	} else {
3060	if (sor->output.panel) {
3061	connector = DRM_MODE_CONNECTOR_eDP;
3062	encoder = DRM_MODE_ENCODER_TMDS;
3063	helpers = &tegra_sor_dp_helpers;
3064	} else {
3065	connector = DRM_MODE_CONNECTOR_DisplayPort;
3066	encoder = DRM_MODE_ENCODER_TMDS;
3067	helpers = &tegra_sor_dp_helpers;
3068	}
3069
3070	sor->link.ops = &tegra_sor_dp_link_ops;
3071	sor->link.aux = sor->aux;
3072	}
3073
3074	sor->output.dev = sor->dev;
3075
3076	drm_connector_init_with_ddc(dev: drm, connector: &sor->output.connector,
3077	funcs: &tegra_sor_connector_funcs,
3078	connector_type: connector,
3079	ddc: sor->output.ddc);
3080	drm_connector_helper_add(connector: &sor->output.connector,
3081	funcs: &tegra_sor_connector_helper_funcs);
3082	sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3083
3084	drm_simple_encoder_init(dev: drm, encoder: &sor->output.encoder, encoder_type: encoder);
3085	drm_encoder_helper_add(encoder: &sor->output.encoder, funcs: helpers);
3086
3087	drm_connector_attach_encoder(connector: &sor->output.connector,
3088	encoder: &sor->output.encoder);
3089	drm_connector_register(connector: &sor->output.connector);
3090
3091	err = tegra_output_init(drm, output: &sor->output);
3092	if (err < 0) {
3093	dev_err(client->dev, "failed to initialize output: %d\n", err);
3094	return err;
3095	}
3096
3097	tegra_output_find_possible_crtcs(output: &sor->output, drm);
3098
3099	if (sor->aux) {
3100	err = drm_dp_aux_attach(aux: sor->aux, output: &sor->output);
3101	if (err < 0) {
3102	dev_err(sor->dev, "failed to attach DP: %d\n", err);
3103	return err;
3104	}
3105	}
3106
3107	/*
3108	* XXX: Remove this reset once proper hand-over from firmware to
3109	* kernel is possible.
3110	*/
3111	if (sor->rst) {
3112	err = pm_runtime_resume_and_get(dev: sor->dev);
3113	if (err < 0) {
3114	dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3115	return err;
3116	}
3117
3118	err = reset_control_acquire(rstc: sor->rst);
3119	if (err < 0) {
3120	dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3121	err);
3122	goto rpm_put;
3123	}
3124
3125	err = reset_control_assert(rstc: sor->rst);
3126	if (err < 0) {
3127	dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3128	err);
3129	goto rpm_put;
3130	}
3131	}
3132
3133	err = clk_prepare_enable(clk: sor->clk);
3134	if (err < 0) {
3135	dev_err(sor->dev, "failed to enable clock: %d\n", err);
3136	goto rpm_put;
3137	}
3138
3139	usleep_range(min: 1000, max: 3000);
3140
3141	if (sor->rst) {
3142	err = reset_control_deassert(rstc: sor->rst);
3143	if (err < 0) {
3144	dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3145	err);
3146	clk_disable_unprepare(clk: sor->clk);
3147	goto rpm_put;
3148	}
3149
3150	reset_control_release(rstc: sor->rst);
3151	pm_runtime_put(dev: sor->dev);
3152	}
3153
3154	err = clk_prepare_enable(clk: sor->clk_safe);
3155	if (err < 0) {
3156	clk_disable_unprepare(clk: sor->clk);
3157	return err;
3158	}
3159
3160	err = clk_prepare_enable(clk: sor->clk_dp);
3161	if (err < 0) {
3162	clk_disable_unprepare(clk: sor->clk_safe);
3163	clk_disable_unprepare(clk: sor->clk);
3164	return err;
3165	}
3166
3167	return 0;
3168
3169	rpm_put:
3170	if (sor->rst)
3171	pm_runtime_put(dev: sor->dev);
3172
3173	return err;
3174	}
3175
3176	static int tegra_sor_exit(struct host1x_client *client)
3177	{
3178	struct tegra_sor *sor = host1x_client_to_sor(client);
3179	int err;
3180
3181	tegra_output_exit(output: &sor->output);
3182
3183	if (sor->aux) {
3184	err = drm_dp_aux_detach(aux: sor->aux);
3185	if (err < 0) {
3186	dev_err(sor->dev, "failed to detach DP: %d\n", err);
3187	return err;
3188	}
3189	}
3190
3191	clk_disable_unprepare(clk: sor->clk_safe);
3192	clk_disable_unprepare(clk: sor->clk_dp);
3193	clk_disable_unprepare(clk: sor->clk);
3194
3195	return 0;
3196	}
3197
3198	static int tegra_sor_runtime_suspend(struct host1x_client *client)
3199	{
3200	struct tegra_sor *sor = host1x_client_to_sor(client);
3201	struct device *dev = client->dev;
3202	int err;
3203
3204	if (sor->rst) {
3205	err = reset_control_assert(rstc: sor->rst);
3206	if (err < 0) {
3207	dev_err(dev, "failed to assert reset: %d\n", err);
3208	return err;
3209	}
3210
3211	reset_control_release(rstc: sor->rst);
3212	}
3213
3214	usleep_range(min: 1000, max: 2000);
3215
3216	clk_disable_unprepare(clk: sor->clk);
3217	pm_runtime_put_sync(dev);
3218
3219	return 0;
3220	}
3221
3222	static int tegra_sor_runtime_resume(struct host1x_client *client)
3223	{
3224	struct tegra_sor *sor = host1x_client_to_sor(client);
3225	struct device *dev = client->dev;
3226	int err;
3227
3228	err = pm_runtime_resume_and_get(dev);
3229	if (err < 0) {
3230	dev_err(dev, "failed to get runtime PM: %d\n", err);
3231	return err;
3232	}
3233
3234	err = clk_prepare_enable(clk: sor->clk);
3235	if (err < 0) {
3236	dev_err(dev, "failed to enable clock: %d\n", err);
3237	goto put_rpm;
3238	}
3239
3240	usleep_range(min: 1000, max: 2000);
3241
3242	if (sor->rst) {
3243	err = reset_control_acquire(rstc: sor->rst);
3244	if (err < 0) {
3245	dev_err(dev, "failed to acquire reset: %d\n", err);
3246	goto disable_clk;
3247	}
3248
3249	err = reset_control_deassert(rstc: sor->rst);
3250	if (err < 0) {
3251	dev_err(dev, "failed to deassert reset: %d\n", err);
3252	goto release_reset;
3253	}
3254	}
3255
3256	return 0;
3257
3258	release_reset:
3259	reset_control_release(rstc: sor->rst);
3260	disable_clk:
3261	clk_disable_unprepare(clk: sor->clk);
3262	put_rpm:
3263	pm_runtime_put_sync(dev);
3264	return err;
3265	}
3266
3267	static const struct host1x_client_ops sor_client_ops = {
3268	.init = tegra_sor_init,
3269	.exit = tegra_sor_exit,
3270	.suspend = tegra_sor_runtime_suspend,
3271	.resume = tegra_sor_runtime_resume,
3272	};
3273
3274	static const u8 tegra124_sor_xbar_cfg[5] = {
3275	0, 1, 2, 3, 4
3276	};
3277
3278	static const struct tegra_sor_regs tegra124_sor_regs = {
3279	.head_state0 = 0x05,
3280	.head_state1 = 0x07,
3281	.head_state2 = 0x09,
3282	.head_state3 = 0x0b,
3283	.head_state4 = 0x0d,
3284	.head_state5 = 0x0f,
3285	.pll0 = 0x17,
3286	.pll1 = 0x18,
3287	.pll2 = 0x19,
3288	.pll3 = 0x1a,
3289	.dp_padctl0 = 0x5c,
3290	.dp_padctl2 = 0x73,
3291	};
3292
3293	/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3294	static const u8 tegra124_sor_lane_map[4] = {
3295	2, 1, 0, 3,
3296	};
3297
3298	static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3299	{
3300	{ 0x13, 0x19, 0x1e, 0x28 },
3301	{ 0x1e, 0x25, 0x2d, },
3302	{ 0x28, 0x32, },
3303	{ 0x3c, },
3304	}, {
3305	{ 0x12, 0x17, 0x1b, 0x25 },
3306	{ 0x1c, 0x23, 0x2a, },
3307	{ 0x25, 0x2f, },
3308	{ 0x39, }
3309	}, {
3310	{ 0x12, 0x16, 0x1a, 0x22 },
3311	{ 0x1b, 0x20, 0x27, },
3312	{ 0x24, 0x2d, },
3313	{ 0x36, },
3314	}, {
3315	{ 0x11, 0x14, 0x17, 0x1f },
3316	{ 0x19, 0x1e, 0x24, },
3317	{ 0x22, 0x2a, },
3318	{ 0x32, },
3319	},
3320	};
3321
3322	static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3323	{
3324	{ 0x00, 0x09, 0x13, 0x25 },
3325	{ 0x00, 0x0f, 0x1e, },
3326	{ 0x00, 0x14, },
3327	{ 0x00, },
3328	}, {
3329	{ 0x00, 0x0a, 0x14, 0x28 },
3330	{ 0x00, 0x0f, 0x1e, },
3331	{ 0x00, 0x14, },
3332	{ 0x00 },
3333	}, {
3334	{ 0x00, 0x0a, 0x14, 0x28 },
3335	{ 0x00, 0x0f, 0x1e, },
3336	{ 0x00, 0x14, },
3337	{ 0x00, },
3338	}, {
3339	{ 0x00, 0x0a, 0x14, 0x28 },
3340	{ 0x00, 0x0f, 0x1e, },
3341	{ 0x00, 0x14, },
3342	{ 0x00, },
3343	},
3344	};
3345
3346	static const u8 tegra124_sor_post_cursor[4][4][4] = {
3347	{
3348	{ 0x00, 0x00, 0x00, 0x00 },
3349	{ 0x00, 0x00, 0x00, },
3350	{ 0x00, 0x00, },
3351	{ 0x00, },
3352	}, {
3353	{ 0x02, 0x02, 0x04, 0x05 },
3354	{ 0x02, 0x04, 0x05, },
3355	{ 0x04, 0x05, },
3356	{ 0x05, },
3357	}, {
3358	{ 0x04, 0x05, 0x08, 0x0b },
3359	{ 0x05, 0x09, 0x0b, },
3360	{ 0x08, 0x0a, },
3361	{ 0x0b, },
3362	}, {
3363	{ 0x05, 0x09, 0x0b, 0x12 },
3364	{ 0x09, 0x0d, 0x12, },
3365	{ 0x0b, 0x0f, },
3366	{ 0x12, },
3367	},
3368	};
3369
3370	static const u8 tegra124_sor_tx_pu[4][4][4] = {
3371	{
3372	{ 0x20, 0x30, 0x40, 0x60 },
3373	{ 0x30, 0x40, 0x60, },
3374	{ 0x40, 0x60, },
3375	{ 0x60, },
3376	}, {
3377	{ 0x20, 0x20, 0x30, 0x50 },
3378	{ 0x30, 0x40, 0x50, },
3379	{ 0x40, 0x50, },
3380	{ 0x60, },
3381	}, {
3382	{ 0x20, 0x20, 0x30, 0x40, },
3383	{ 0x30, 0x30, 0x40, },
3384	{ 0x40, 0x50, },
3385	{ 0x60, },
3386	}, {
3387	{ 0x20, 0x20, 0x20, 0x40, },
3388	{ 0x30, 0x30, 0x40, },
3389	{ 0x40, 0x40, },
3390	{ 0x60, },
3391	},
3392	};
3393
3394	static const struct tegra_sor_soc tegra124_sor = {
3395	.supports_lvds = true,
3396	.supports_hdmi = false,
3397	.supports_dp = true,
3398	.supports_audio = false,
3399	.supports_hdcp = false,
3400	.regs = &tegra124_sor_regs,
3401	.has_nvdisplay = false,
3402	.xbar_cfg = tegra124_sor_xbar_cfg,
3403	.lane_map = tegra124_sor_lane_map,
3404	.voltage_swing = tegra124_sor_voltage_swing,
3405	.pre_emphasis = tegra124_sor_pre_emphasis,
3406	.post_cursor = tegra124_sor_post_cursor,
3407	.tx_pu = tegra124_sor_tx_pu,
3408	};
3409
3410	static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3411	{
3412	{ 0x00, 0x08, 0x12, 0x24 },
3413	{ 0x01, 0x0e, 0x1d, },
3414	{ 0x01, 0x13, },
3415	{ 0x00, },
3416	}, {
3417	{ 0x00, 0x08, 0x12, 0x24 },
3418	{ 0x00, 0x0e, 0x1d, },
3419	{ 0x00, 0x13, },
3420	{ 0x00 },
3421	}, {
3422	{ 0x00, 0x08, 0x12, 0x24 },
3423	{ 0x00, 0x0e, 0x1d, },
3424	{ 0x00, 0x13, },
3425	{ 0x00, },
3426	}, {
3427	{ 0x00, 0x08, 0x12, 0x24 },
3428	{ 0x00, 0x0e, 0x1d, },
3429	{ 0x00, 0x13, },
3430	{ 0x00, },
3431	},
3432	};
3433
3434	static const struct tegra_sor_soc tegra132_sor = {
3435	.supports_lvds = true,
3436	.supports_hdmi = false,
3437	.supports_dp = true,
3438	.supports_audio = false,
3439	.supports_hdcp = false,
3440	.regs = &tegra124_sor_regs,
3441	.has_nvdisplay = false,
3442	.xbar_cfg = tegra124_sor_xbar_cfg,
3443	.lane_map = tegra124_sor_lane_map,
3444	.voltage_swing = tegra124_sor_voltage_swing,
3445	.pre_emphasis = tegra132_sor_pre_emphasis,
3446	.post_cursor = tegra124_sor_post_cursor,
3447	.tx_pu = tegra124_sor_tx_pu,
3448	};
3449
3450	static const struct tegra_sor_regs tegra210_sor_regs = {
3451	.head_state0 = 0x05,
3452	.head_state1 = 0x07,
3453	.head_state2 = 0x09,
3454	.head_state3 = 0x0b,
3455	.head_state4 = 0x0d,
3456	.head_state5 = 0x0f,
3457	.pll0 = 0x17,
3458	.pll1 = 0x18,
3459	.pll2 = 0x19,
3460	.pll3 = 0x1a,
3461	.dp_padctl0 = 0x5c,
3462	.dp_padctl2 = 0x73,
3463	};
3464
3465	static const u8 tegra210_sor_xbar_cfg[5] = {
3466	2, 1, 0, 3, 4
3467	};
3468
3469	static const u8 tegra210_sor_lane_map[4] = {
3470	0, 1, 2, 3,
3471	};
3472
3473	static const struct tegra_sor_soc tegra210_sor = {
3474	.supports_lvds = false,
3475	.supports_hdmi = false,
3476	.supports_dp = true,
3477	.supports_audio = false,
3478	.supports_hdcp = false,
3479
3480	.regs = &tegra210_sor_regs,
3481	.has_nvdisplay = false,
3482
3483	.xbar_cfg = tegra210_sor_xbar_cfg,
3484	.lane_map = tegra210_sor_lane_map,
3485	.voltage_swing = tegra124_sor_voltage_swing,
3486	.pre_emphasis = tegra124_sor_pre_emphasis,
3487	.post_cursor = tegra124_sor_post_cursor,
3488	.tx_pu = tegra124_sor_tx_pu,
3489	};
3490
3491	static const struct tegra_sor_soc tegra210_sor1 = {
3492	.supports_lvds = false,
3493	.supports_hdmi = true,
3494	.supports_dp = true,
3495	.supports_audio = true,
3496	.supports_hdcp = true,
3497
3498	.regs = &tegra210_sor_regs,
3499	.has_nvdisplay = false,
3500
3501	.num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3502	.settings = tegra210_sor_hdmi_defaults,
3503	.xbar_cfg = tegra210_sor_xbar_cfg,
3504	.lane_map = tegra210_sor_lane_map,
3505	.voltage_swing = tegra124_sor_voltage_swing,
3506	.pre_emphasis = tegra124_sor_pre_emphasis,
3507	.post_cursor = tegra124_sor_post_cursor,
3508	.tx_pu = tegra124_sor_tx_pu,
3509	};
3510
3511	static const struct tegra_sor_regs tegra186_sor_regs = {
3512	.head_state0 = 0x151,
3513	.head_state1 = 0x154,
3514	.head_state2 = 0x157,
3515	.head_state3 = 0x15a,
3516	.head_state4 = 0x15d,
3517	.head_state5 = 0x160,
3518	.pll0 = 0x163,
3519	.pll1 = 0x164,
3520	.pll2 = 0x165,
3521	.pll3 = 0x166,
3522	.dp_padctl0 = 0x168,
3523	.dp_padctl2 = 0x16a,
3524	};
3525
3526	static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3527	{
3528	{ 0x13, 0x19, 0x1e, 0x28 },
3529	{ 0x1e, 0x25, 0x2d, },
3530	{ 0x28, 0x32, },
3531	{ 0x39, },
3532	}, {
3533	{ 0x12, 0x16, 0x1b, 0x25 },
3534	{ 0x1c, 0x23, 0x2a, },
3535	{ 0x25, 0x2f, },
3536	{ 0x37, }
3537	}, {
3538	{ 0x12, 0x16, 0x1a, 0x22 },
3539	{ 0x1b, 0x20, 0x27, },
3540	{ 0x24, 0x2d, },
3541	{ 0x35, },
3542	}, {
3543	{ 0x11, 0x14, 0x17, 0x1f },
3544	{ 0x19, 0x1e, 0x24, },
3545	{ 0x22, 0x2a, },
3546	{ 0x32, },
3547	},
3548	};
3549
3550	static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3551	{
3552	{ 0x00, 0x08, 0x12, 0x24 },
3553	{ 0x01, 0x0e, 0x1d, },
3554	{ 0x01, 0x13, },
3555	{ 0x00, },
3556	}, {
3557	{ 0x00, 0x08, 0x12, 0x24 },
3558	{ 0x00, 0x0e, 0x1d, },
3559	{ 0x00, 0x13, },
3560	{ 0x00 },
3561	}, {
3562	{ 0x00, 0x08, 0x14, 0x24 },
3563	{ 0x00, 0x0e, 0x1d, },
3564	{ 0x00, 0x13, },
3565	{ 0x00, },
3566	}, {
3567	{ 0x00, 0x08, 0x12, 0x24 },
3568	{ 0x00, 0x0e, 0x1d, },
3569	{ 0x00, 0x13, },
3570	{ 0x00, },
3571	},
3572	};
3573
3574	static const struct tegra_sor_soc tegra186_sor = {
3575	.supports_lvds = false,
3576	.supports_hdmi = true,
3577	.supports_dp = true,
3578	.supports_audio = true,
3579	.supports_hdcp = true,
3580
3581	.regs = &tegra186_sor_regs,
3582	.has_nvdisplay = true,
3583
3584	.num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3585	.settings = tegra186_sor_hdmi_defaults,
3586	.xbar_cfg = tegra124_sor_xbar_cfg,
3587	.lane_map = tegra124_sor_lane_map,
3588	.voltage_swing = tegra186_sor_voltage_swing,
3589	.pre_emphasis = tegra186_sor_pre_emphasis,
3590	.post_cursor = tegra124_sor_post_cursor,
3591	.tx_pu = tegra124_sor_tx_pu,
3592	};
3593
3594	static const struct tegra_sor_regs tegra194_sor_regs = {
3595	.head_state0 = 0x151,
3596	.head_state1 = 0x155,
3597	.head_state2 = 0x159,
3598	.head_state3 = 0x15d,
3599	.head_state4 = 0x161,
3600	.head_state5 = 0x165,
3601	.pll0 = 0x169,
3602	.pll1 = 0x16a,
3603	.pll2 = 0x16b,
3604	.pll3 = 0x16c,
3605	.dp_padctl0 = 0x16e,
3606	.dp_padctl2 = 0x16f,
3607	};
3608
3609	static const struct tegra_sor_soc tegra194_sor = {
3610	.supports_lvds = false,
3611	.supports_hdmi = true,
3612	.supports_dp = true,
3613	.supports_audio = true,
3614	.supports_hdcp = true,
3615
3616	.regs = &tegra194_sor_regs,
3617	.has_nvdisplay = true,
3618
3619	.num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3620	.settings = tegra194_sor_hdmi_defaults,
3621
3622	.xbar_cfg = tegra210_sor_xbar_cfg,
3623	.lane_map = tegra124_sor_lane_map,
3624	.voltage_swing = tegra186_sor_voltage_swing,
3625	.pre_emphasis = tegra186_sor_pre_emphasis,
3626	.post_cursor = tegra124_sor_post_cursor,
3627	.tx_pu = tegra124_sor_tx_pu,
3628	};
3629
3630	static const struct of_device_id tegra_sor_of_match[] = {
3631	{ .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3632	{ .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3633	{ .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3634	{ .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3635	{ .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3636	{ .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3637	{ },
3638	};
3639	MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3640
3641	static int tegra_sor_parse_dt(struct tegra_sor *sor)
3642	{
3643	struct device_node *np = sor->dev->of_node;
3644	u32 xbar_cfg[5];
3645	unsigned int i;
3646	u32 value;
3647	int err;
3648
3649	if (sor->soc->has_nvdisplay) {
3650	err = of_property_read_u32(np, propname: "nvidia,interface", out_value: &value);
3651	if (err < 0)
3652	return err;
3653
3654	sor->index = value;
3655
3656	/*
3657	* override the default that we already set for Tegra210 and
3658	* earlier
3659	*/
3660	sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3661	} else {
3662	if (!sor->soc->supports_audio)
3663	sor->index = 0;
3664	else
3665	sor->index = 1;
3666	}
3667
3668	err = of_property_read_u32_array(np, propname: "nvidia,xbar-cfg", out_values: xbar_cfg, sz: 5);
3669	if (err < 0) {
3670	/* fall back to default per-SoC XBAR configuration */
3671	for (i = 0; i < 5; i++)
3672	sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3673	} else {
3674	/* copy cells to SOR XBAR configuration */
3675	for (i = 0; i < 5; i++)
3676	sor->xbar_cfg[i] = xbar_cfg[i];
3677	}
3678
3679	return 0;
3680	}
3681
3682	static irqreturn_t tegra_sor_irq(int irq, void *data)
3683	{
3684	struct tegra_sor *sor = data;
3685	u32 value;
3686
3687	value = tegra_sor_readl(sor, SOR_INT_STATUS);
3688	tegra_sor_writel(sor, value, SOR_INT_STATUS);
3689
3690	if (value & SOR_INT_CODEC_SCRATCH0) {
3691	value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3692
3693	if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3694	unsigned int format;
3695
3696	format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3697
3698	tegra_hda_parse_format(format, fmt: &sor->format);
3699
3700	if (sor->ops->audio_enable)
3701	sor->ops->audio_enable(sor);
3702	} else {
3703	if (sor->ops->audio_disable)
3704	sor->ops->audio_disable(sor);
3705	}
3706	}
3707
3708	return IRQ_HANDLED;
3709	}
3710
3711	static int tegra_sor_probe(struct platform_device *pdev)
3712	{
3713	struct device_node *np;
3714	struct tegra_sor *sor;
3715	int err;
3716
3717	sor = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sor), GFP_KERNEL);
3718	if (!sor)
3719	return -ENOMEM;
3720
3721	sor->soc = of_device_get_match_data(dev: &pdev->dev);
3722	sor->output.dev = sor->dev = &pdev->dev;
3723
3724	sor->settings = devm_kmemdup(dev: &pdev->dev, src: sor->soc->settings,
3725	len: sor->soc->num_settings *
3726	sizeof(*sor->settings),
3727	GFP_KERNEL);
3728	if (!sor->settings)
3729	return -ENOMEM;
3730
3731	sor->num_settings = sor->soc->num_settings;
3732
3733	np = of_parse_phandle(np: pdev->dev.of_node, phandle_name: "nvidia,dpaux", index: 0);
3734	if (np) {
3735	sor->aux = drm_dp_aux_find_by_of_node(np);
3736	of_node_put(node: np);
3737
3738	if (!sor->aux)
3739	return -EPROBE_DEFER;
3740
3741	if (get_device(dev: sor->aux->dev))
3742	sor->output.ddc = &sor->aux->ddc;
3743	}
3744
3745	if (!sor->aux) {
3746	if (sor->soc->supports_hdmi) {
3747	sor->ops = &tegra_sor_hdmi_ops;
3748	sor->pad = TEGRA_IO_PAD_HDMI;
3749	} else if (sor->soc->supports_lvds) {
3750	dev_err(&pdev->dev, "LVDS not supported yet\n");
3751	return -ENODEV;
3752	} else {
3753	dev_err(&pdev->dev, "unknown (non-DP) support\n");
3754	return -ENODEV;
3755	}
3756	} else {
3757	np = of_parse_phandle(np: pdev->dev.of_node, phandle_name: "nvidia,panel", index: 0);
3758	/*
3759	* No need to keep this around since we only use it as a check
3760	* to see if a panel is connected (eDP) or not (DP).
3761	*/
3762	of_node_put(node: np);
3763
3764	sor->ops = &tegra_sor_dp_ops;
3765	sor->pad = TEGRA_IO_PAD_LVDS;
3766	}
3767
3768	err = tegra_sor_parse_dt(sor);
3769	if (err < 0)
3770	goto put_aux;
3771
3772	err = tegra_output_probe(output: &sor->output);
3773	if (err < 0) {
3774	dev_err_probe(dev: &pdev->dev, err, fmt: "failed to probe output\n");
3775	goto put_aux;
3776	}
3777
3778	if (sor->ops && sor->ops->probe) {
3779	err = sor->ops->probe(sor);
3780	if (err < 0) {
3781	dev_err(&pdev->dev, "failed to probe %s: %d\n",
3782	sor->ops->name, err);
3783	goto remove;
3784	}
3785	}
3786
3787	sor->regs = devm_platform_ioremap_resource(pdev, index: 0);
3788	if (IS_ERR(ptr: sor->regs)) {
3789	err = PTR_ERR(ptr: sor->regs);
3790	goto remove;
3791	}
3792
3793	err = platform_get_irq(pdev, 0);
3794	if (err < 0)
3795	goto remove;
3796
3797	sor->irq = err;
3798
3799	err = devm_request_irq(dev: sor->dev, irq: sor->irq, handler: tegra_sor_irq, irqflags: 0,
3800	devname: dev_name(dev: sor->dev), dev_id: sor);
3801	if (err < 0) {
3802	dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3803	goto remove;
3804	}
3805
3806	sor->rst = devm_reset_control_get_exclusive_released(dev: &pdev->dev, id: "sor");
3807	if (IS_ERR(ptr: sor->rst)) {
3808	err = PTR_ERR(ptr: sor->rst);
3809
3810	if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3811	dev_err(&pdev->dev, "failed to get reset control: %d\n",
3812	err);
3813	goto remove;
3814	}
3815
3816	/*
3817	* At this point, the reset control is most likely being used
3818	* by the generic power domain implementation. With any luck
3819	* the power domain will have taken care of resetting the SOR
3820	* and we don't have to do anything.
3821	*/
3822	sor->rst = NULL;
3823	}
3824
3825	sor->clk = devm_clk_get(dev: &pdev->dev, NULL);
3826	if (IS_ERR(ptr: sor->clk)) {
3827	err = PTR_ERR(ptr: sor->clk);
3828	dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3829	goto remove;
3830	}
3831
3832	if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3833	struct device_node *np = pdev->dev.of_node;
3834	const char *name;
3835
3836	/*
3837	* For backwards compatibility with Tegra210 device trees,
3838	* fall back to the old clock name "source" if the new "out"
3839	* clock is not available.
3840	*/
3841	if (of_property_match_string(np, propname: "clock-names", string: "out") < 0)
3842	name = "source";
3843	else
3844	name = "out";
3845
3846	sor->clk_out = devm_clk_get(dev: &pdev->dev, id: name);
3847	if (IS_ERR(ptr: sor->clk_out)) {
3848	err = PTR_ERR(ptr: sor->clk_out);
3849	dev_err(sor->dev, "failed to get %s clock: %d\n",
3850	name, err);
3851	goto remove;
3852	}
3853	} else {
3854	/* fall back to the module clock on SOR0 (eDP/LVDS only) */
3855	sor->clk_out = sor->clk;
3856	}
3857
3858	sor->clk_parent = devm_clk_get(dev: &pdev->dev, id: "parent");
3859	if (IS_ERR(ptr: sor->clk_parent)) {
3860	err = PTR_ERR(ptr: sor->clk_parent);
3861	dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3862	goto remove;
3863	}
3864
3865	sor->clk_safe = devm_clk_get(dev: &pdev->dev, id: "safe");
3866	if (IS_ERR(ptr: sor->clk_safe)) {
3867	err = PTR_ERR(ptr: sor->clk_safe);
3868	dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3869	goto remove;
3870	}
3871
3872	sor->clk_dp = devm_clk_get(dev: &pdev->dev, id: "dp");
3873	if (IS_ERR(ptr: sor->clk_dp)) {
3874	err = PTR_ERR(ptr: sor->clk_dp);
3875	dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3876	goto remove;
3877	}
3878
3879	/*
3880	* Starting with Tegra186, the BPMP provides an implementation for
3881	* the pad output clock, so we have to look it up from device tree.
3882	*/
3883	sor->clk_pad = devm_clk_get(dev: &pdev->dev, id: "pad");
3884	if (IS_ERR(ptr: sor->clk_pad)) {
3885	if (sor->clk_pad != ERR_PTR(error: -ENOENT)) {
3886	err = PTR_ERR(ptr: sor->clk_pad);
3887	goto remove;
3888	}
3889
3890	/*
3891	* If the pad output clock is not available, then we assume
3892	* we're on Tegra210 or earlier and have to provide our own
3893	* implementation.
3894	*/
3895	sor->clk_pad = NULL;
3896	}
3897
3898	/*
3899	* The bootloader may have set up the SOR such that it's module clock
3900	* is sourced by one of the display PLLs. However, that doesn't work
3901	* without properly having set up other bits of the SOR.
3902	*/
3903	err = clk_set_parent(clk: sor->clk_out, parent: sor->clk_safe);
3904	if (err < 0) {
3905	dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3906	goto remove;
3907	}
3908
3909	platform_set_drvdata(pdev, data: sor);
3910	pm_runtime_enable(dev: &pdev->dev);
3911
3912	host1x_client_init(&sor->client);
3913	sor->client.ops = &sor_client_ops;
3914	sor->client.dev = &pdev->dev;
3915
3916	/*
3917	* On Tegra210 and earlier, provide our own implementation for the
3918	* pad output clock.
3919	*/
3920	if (!sor->clk_pad) {
3921	char *name;
3922
3923	name = devm_kasprintf(dev: sor->dev, GFP_KERNEL, fmt: "sor%u_pad_clkout",
3924	sor->index);
3925	if (!name) {
3926	err = -ENOMEM;
3927	goto uninit;
3928	}
3929
3930	err = host1x_client_resume(client: &sor->client);
3931	if (err < 0) {
3932	dev_err(sor->dev, "failed to resume: %d\n", err);
3933	goto uninit;
3934	}
3935
3936	sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3937	host1x_client_suspend(client: &sor->client);
3938	}
3939
3940	if (IS_ERR(ptr: sor->clk_pad)) {
3941	err = PTR_ERR(ptr: sor->clk_pad);
3942	dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3943	err);
3944	goto uninit;
3945	}
3946
3947	err = __host1x_client_register(client: &sor->client);
3948	if (err < 0) {
3949	dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3950	err);
3951	goto uninit;
3952	}
3953
3954	return 0;
3955
3956	uninit:
3957	host1x_client_exit(client: &sor->client);
3958	pm_runtime_disable(dev: &pdev->dev);
3959	remove:
3960	if (sor->aux)
3961	sor->output.ddc = NULL;
3962
3963	tegra_output_remove(output: &sor->output);
3964	put_aux:
3965	if (sor->aux)
3966	put_device(dev: sor->aux->dev);
3967
3968	return err;
3969	}
3970
3971	static void tegra_sor_remove(struct platform_device *pdev)
3972	{
3973	struct tegra_sor *sor = platform_get_drvdata(pdev);
3974
3975	host1x_client_unregister(client: &sor->client);
3976
3977	pm_runtime_disable(dev: &pdev->dev);
3978
3979	if (sor->aux) {
3980	put_device(dev: sor->aux->dev);
3981	sor->output.ddc = NULL;
3982	}
3983
3984	tegra_output_remove(output: &sor->output);
3985	}
3986
3987	static int __maybe_unused tegra_sor_suspend(struct device *dev)
3988	{
3989	struct tegra_sor *sor = dev_get_drvdata(dev);
3990	int err;
3991
3992	err = tegra_output_suspend(output: &sor->output);
3993	if (err < 0) {
3994	dev_err(dev, "failed to suspend output: %d\n", err);
3995	return err;
3996	}
3997
3998	if (sor->hdmi_supply) {
3999	err = regulator_disable(regulator: sor->hdmi_supply);
4000	if (err < 0) {
4001	tegra_output_resume(output: &sor->output);
4002	return err;
4003	}
4004	}
4005
4006	return 0;
4007	}
4008
4009	static int __maybe_unused tegra_sor_resume(struct device *dev)
4010	{
4011	struct tegra_sor *sor = dev_get_drvdata(dev);
4012	int err;
4013
4014	if (sor->hdmi_supply) {
4015	err = regulator_enable(regulator: sor->hdmi_supply);
4016	if (err < 0)
4017	return err;
4018	}
4019
4020	err = tegra_output_resume(output: &sor->output);
4021	if (err < 0) {
4022	dev_err(dev, "failed to resume output: %d\n", err);
4023
4024	if (sor->hdmi_supply)
4025	regulator_disable(regulator: sor->hdmi_supply);
4026
4027	return err;
4028	}
4029
4030	return 0;
4031	}
4032
4033	static const struct dev_pm_ops tegra_sor_pm_ops = {
4034	SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4035	};
4036
4037	struct platform_driver tegra_sor_driver = {
4038	.driver = {
4039	.name = "tegra-sor",
4040	.of_match_table = tegra_sor_of_match,
4041	.pm = &tegra_sor_pm_ops,
4042	},
4043	.probe = tegra_sor_probe,
4044	.remove = tegra_sor_remove,
4045	};
4046