| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */ |
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| 3 | /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */ |
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| 4 | #ifndef __PANFROST_ISSUES_H__ |
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| 5 | #define __PANFROST_ISSUES_H__ |
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| 6 | |
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| 7 | #include <linux/bitops.h> |
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| 8 | |
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| 9 | #include "panfrost_device.h" |
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| 10 | |
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| 11 | /* |
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| 12 | * This is not a complete list of issues, but only the ones the driver needs |
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| 13 | * to care about. |
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| 14 | */ |
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| 15 | enum panfrost_hw_issue { |
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| 16 | /* Need way to guarantee that all previously-translated memory accesses |
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| 17 | * are committed */ |
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| 18 | HW_ISSUE_6367, |
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| 19 | |
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| 20 | /* On job complete with non-done the cache is not flushed */ |
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| 21 | HW_ISSUE_6787, |
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| 22 | |
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| 23 | /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a |
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| 24 | * instrumentation dump if PRFCNT_TILER_EN is enabled */ |
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| 25 | HW_ISSUE_8186, |
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| 26 | |
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| 27 | /* TIB: Reports faults from a vtile which has not yet been allocated */ |
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| 28 | HW_ISSUE_8245, |
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| 29 | |
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| 30 | /* uTLB deadlock could occur when writing to an invalid page at the |
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| 31 | * same time as access to a valid page in the same uTLB cache line ( == |
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| 32 | * 4 PTEs == 16K block of mapping) */ |
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| 33 | HW_ISSUE_8316, |
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| 34 | |
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| 35 | /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is |
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| 36 | * still executing */ |
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| 37 | HW_ISSUE_8394, |
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| 38 | |
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| 39 | /* CSE: Sends a TERMINATED response for a task that should not be |
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| 40 | * terminated */ |
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| 41 | HW_ISSUE_8401, |
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| 42 | |
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| 43 | /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader, |
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| 44 | * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */ |
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| 45 | HW_ISSUE_8408, |
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| 46 | |
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| 47 | /* Disable the Pause Buffer in the LS pipe. */ |
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| 48 | HW_ISSUE_8443, |
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| 49 | |
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| 50 | /* Change in RMUs in use causes problems related with the core's SDC */ |
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| 51 | HW_ISSUE_8987, |
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| 52 | |
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| 53 | /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop |
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| 54 | * won't complete until all 4 tasks have completed */ |
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| 55 | HW_ISSUE_9435, |
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| 56 | |
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| 57 | /* HT: Tiler returns TERMINATED for non-terminated command */ |
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| 58 | HW_ISSUE_9510, |
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| 59 | |
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| 60 | /* Occasionally the GPU will issue multiple page faults for the same |
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| 61 | * address before the MMU page table has been read by the GPU */ |
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| 62 | HW_ISSUE_9630, |
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| 63 | |
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| 64 | /* RA DCD load request to SDC returns invalid load ignore causing |
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| 65 | * colour buffer mismatch */ |
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| 66 | HW_ISSUE_10327, |
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| 67 | |
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| 68 | /* MMU TLB invalidation hazards */ |
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| 69 | HW_ISSUE_10649, |
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| 70 | |
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| 71 | /* Missing cache flush in multi core-group configuration */ |
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| 72 | HW_ISSUE_10676, |
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| 73 | |
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| 74 | /* Chicken bit on T72X for a hardware workaround in compiler */ |
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| 75 | HW_ISSUE_10797, |
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| 76 | |
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| 77 | /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */ |
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| 78 | HW_ISSUE_10817, |
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| 79 | |
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| 80 | /* Intermittent missing interrupt on job completion */ |
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| 81 | HW_ISSUE_10883, |
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| 82 | |
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| 83 | /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR |
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| 84 | * (similar to issue 10817) and can use #10817 workaround */ |
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| 85 | HW_ISSUE_10959, |
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| 86 | |
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| 87 | /* Soft-stopped fragment shader job can restart with out-of-bound |
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| 88 | * restart index */ |
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| 89 | HW_ISSUE_10969, |
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| 90 | |
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| 91 | /* Race condition can cause tile list corruption */ |
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| 92 | HW_ISSUE_11020, |
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| 93 | |
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| 94 | /* Write buffer can cause tile list corruption */ |
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| 95 | HW_ISSUE_11024, |
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| 96 | |
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| 97 | /* Pause buffer can cause a fragment job hang */ |
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| 98 | HW_ISSUE_11035, |
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| 99 | |
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| 100 | /* Dynamic Core Scaling not supported due to errata */ |
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| 101 | HW_ISSUE_11056, |
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| 102 | |
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| 103 | /* Clear encoder state for a hard stopped fragment job which is AFBC |
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| 104 | * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and |
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| 105 | * r0p1_50rel0 */ |
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| 106 | HW_ISSUE_T76X_3542, |
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| 107 | |
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| 108 | /* Keep tiler module clock on to prevent GPU stall */ |
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| 109 | HW_ISSUE_T76X_3953, |
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| 110 | |
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| 111 | /* Must ensure L2 is not transitioning when we reset. Workaround with a |
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| 112 | * busy wait until L2 completes transition; ensure there is a maximum |
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| 113 | * loop count as she may never complete her transition. (On chips |
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| 114 | * without this errata, it's totally okay if L2 transitions.) */ |
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| 115 | HW_ISSUE_TMIX_8463, |
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| 116 | |
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| 117 | /* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */ |
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| 118 | GPUCORE_1619, |
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| 119 | |
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| 120 | /* When a hard-stop follows close after a soft-stop, the completion |
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| 121 | * code for the terminated job may be incorrectly set to STOPPED */ |
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| 122 | HW_ISSUE_TMIX_8438, |
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| 123 | |
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| 124 | /* "Protected mode" is buggy on Mali-G31 some Bifrost chips, so the |
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| 125 | * kernel must fiddle with L2 caches to prevent data leakage */ |
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| 126 | HW_ISSUE_TGOX_R1_1234, |
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| 127 | |
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| 128 | /* Must set SC_VAR_ALGORITHM */ |
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| 129 | HW_ISSUE_TTRX_2968_TTRX_3162, |
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| 130 | |
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| 131 | /* Bus fault from occlusion query write may cause future fragment jobs |
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| 132 | * to hang */ |
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| 133 | HW_ISSUE_TTRX_3076, |
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| 134 | |
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| 135 | /* Must issue a dummy job before starting real work to prevent hangs */ |
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| 136 | HW_ISSUE_TTRX_3485, |
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| 137 | |
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| 138 | HW_ISSUE_END |
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| 139 | }; |
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| 140 | |
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| 141 | #define hw_issues_all (\ |
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| 142 | BIT_ULL(HW_ISSUE_9435)) |
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| 143 | |
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| 144 | #define hw_issues_t600 (\ |
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| 145 | BIT_ULL(HW_ISSUE_6367) | \ |
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| 146 | BIT_ULL(HW_ISSUE_6787) | \ |
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| 147 | BIT_ULL(HW_ISSUE_8408) | \ |
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| 148 | BIT_ULL(HW_ISSUE_9510) | \ |
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| 149 | BIT_ULL(HW_ISSUE_10649) | \ |
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| 150 | BIT_ULL(HW_ISSUE_10676) | \ |
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| 151 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 152 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 153 | BIT_ULL(HW_ISSUE_11035) | \ |
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| 154 | BIT_ULL(HW_ISSUE_11056) | \ |
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| 155 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 156 | |
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| 157 | #define hw_issues_t600_r0p0_15dev0 (\ |
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| 158 | BIT_ULL(HW_ISSUE_8186) | \ |
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| 159 | BIT_ULL(HW_ISSUE_8245) | \ |
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| 160 | BIT_ULL(HW_ISSUE_8316) | \ |
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| 161 | BIT_ULL(HW_ISSUE_8394) | \ |
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| 162 | BIT_ULL(HW_ISSUE_8401) | \ |
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| 163 | BIT_ULL(HW_ISSUE_8443) | \ |
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| 164 | BIT_ULL(HW_ISSUE_8987) | \ |
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| 165 | BIT_ULL(HW_ISSUE_9630) | \ |
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| 166 | BIT_ULL(HW_ISSUE_10969) | \ |
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| 167 | BIT_ULL(GPUCORE_1619)) |
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| 168 | |
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| 169 | #define hw_issues_t620 (\ |
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| 170 | BIT_ULL(HW_ISSUE_10649) | \ |
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| 171 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 172 | BIT_ULL(HW_ISSUE_10959) | \ |
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| 173 | BIT_ULL(HW_ISSUE_11056) | \ |
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| 174 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 175 | |
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| 176 | #define hw_issues_t620_r0p1 (\ |
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| 177 | BIT_ULL(HW_ISSUE_10327) | \ |
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| 178 | BIT_ULL(HW_ISSUE_10676) | \ |
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| 179 | BIT_ULL(HW_ISSUE_10817) | \ |
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| 180 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 181 | BIT_ULL(HW_ISSUE_11024) | \ |
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| 182 | BIT_ULL(HW_ISSUE_11035)) |
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| 183 | |
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| 184 | #define hw_issues_t620_r1p0 (\ |
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| 185 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 186 | BIT_ULL(HW_ISSUE_11024)) |
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| 187 | |
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| 188 | #define hw_issues_t720 (\ |
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| 189 | BIT_ULL(HW_ISSUE_10649) | \ |
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| 190 | BIT_ULL(HW_ISSUE_10797) | \ |
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| 191 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 192 | BIT_ULL(HW_ISSUE_11056) | \ |
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| 193 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 194 | |
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| 195 | #define hw_issues_t760 (\ |
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| 196 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 197 | BIT_ULL(HW_ISSUE_T76X_3953) | \ |
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| 198 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 199 | |
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| 200 | #define hw_issues_t760_r0p0 (\ |
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| 201 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 202 | BIT_ULL(HW_ISSUE_11024) | \ |
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| 203 | BIT_ULL(HW_ISSUE_T76X_3542)) |
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| 204 | |
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| 205 | #define hw_issues_t760_r0p1 (\ |
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| 206 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 207 | BIT_ULL(HW_ISSUE_11024) | \ |
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| 208 | BIT_ULL(HW_ISSUE_T76X_3542)) |
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| 209 | |
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| 210 | #define hw_issues_t760_r0p1_50rel0 (\ |
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| 211 | BIT_ULL(HW_ISSUE_T76X_3542)) |
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| 212 | |
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| 213 | #define hw_issues_t760_r0p2 (\ |
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| 214 | BIT_ULL(HW_ISSUE_11020) | \ |
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| 215 | BIT_ULL(HW_ISSUE_11024) | \ |
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| 216 | BIT_ULL(HW_ISSUE_T76X_3542)) |
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| 217 | |
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| 218 | #define hw_issues_t760_r0p3 (\ |
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| 219 | BIT_ULL(HW_ISSUE_T76X_3542)) |
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| 220 | |
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| 221 | #define hw_issues_t820 (\ |
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| 222 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 223 | BIT_ULL(HW_ISSUE_T76X_3953) | \ |
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| 224 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 225 | |
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| 226 | #define hw_issues_t830 (\ |
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| 227 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 228 | BIT_ULL(HW_ISSUE_T76X_3953) | \ |
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| 229 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 230 | |
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| 231 | #define hw_issues_t860 (\ |
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| 232 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 233 | BIT_ULL(HW_ISSUE_T76X_3953) | \ |
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| 234 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 235 | |
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| 236 | #define hw_issues_t880 (\ |
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| 237 | BIT_ULL(HW_ISSUE_10883) | \ |
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| 238 | BIT_ULL(HW_ISSUE_T76X_3953) | \ |
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| 239 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 240 | |
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| 241 | #define hw_issues_g31 0 |
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| 242 | |
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| 243 | #define hw_issues_g31_r1p0 (\ |
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| 244 | BIT_ULL(HW_ISSUE_TGOX_R1_1234)) |
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| 245 | |
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| 246 | #define hw_issues_g51 0 |
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| 247 | |
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| 248 | #define hw_issues_g52 0 |
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| 249 | |
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| 250 | #define hw_issues_g71 (\ |
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| 251 | BIT_ULL(HW_ISSUE_TMIX_8463) | \ |
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| 252 | BIT_ULL(HW_ISSUE_TMIX_8438)) |
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| 253 | |
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| 254 | #define hw_issues_g71_r0p0_05dev0 (\ |
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| 255 | BIT_ULL(HW_ISSUE_T76X_3953)) |
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| 256 | |
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| 257 | #define hw_issues_g72 0 |
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| 258 | |
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| 259 | #define hw_issues_g76 0 |
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| 260 | |
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| 261 | #define hw_issues_g57 (\ |
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| 262 | BIT_ULL(HW_ISSUE_TTRX_2968_TTRX_3162) | \ |
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| 263 | BIT_ULL(HW_ISSUE_TTRX_3076)) |
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| 264 | |
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| 265 | #define hw_issues_g57_r0p0 (\ |
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| 266 | BIT_ULL(HW_ISSUE_TTRX_3485)) |
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| 267 | |
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| 268 | static inline bool panfrost_has_hw_issue(const struct panfrost_device *pfdev, |
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| 269 | enum panfrost_hw_issue issue) |
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| 270 | { |
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| 271 | return test_bit(issue, pfdev->features.hw_issues); |
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| 272 | } |
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| 273 | |
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| 274 | #endif /* __PANFROST_ISSUES_H__ */ |
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| 275 | |
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