1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2/* Copyright (c) 2023 Imagination Technologies Ltd. */
3
4#ifndef PVR_ROGUE_META_H
5#define PVR_ROGUE_META_H
6
7/***** The META HW register definitions in the file are updated manually *****/
8
9#include <linux/bits.h>
10#include <linux/types.h>
11
12/*
13 ******************************************************************************
14 * META registers and MACROS
15 *****************************************************************************
16 */
17#define META_CR_CTRLREG_BASE(t) (0x04800000U + (0x1000U * (t)))
18
19#define META_CR_TXPRIVEXT (0x048000E8)
20#define META_CR_TXPRIVEXT_MINIM_EN BIT(7)
21
22#define META_CR_SYSC_JTAG_THREAD (0x04830030)
23#define META_CR_SYSC_JTAG_THREAD_PRIV_EN (0x00000004)
24
25#define META_CR_PERF_COUNT0 (0x0480FFE0)
26#define META_CR_PERF_COUNT1 (0x0480FFE8)
27#define META_CR_PERF_COUNT_CTRL_SHIFT (28)
28#define META_CR_PERF_COUNT_CTRL_MASK (0xF0000000)
29#define META_CR_PERF_COUNT_CTRL_DCACHEHITS (8 << META_CR_PERF_COUNT_CTRL_SHIFT)
30#define META_CR_PERF_COUNT_CTRL_ICACHEHITS (9 << META_CR_PERF_COUNT_CTRL_SHIFT)
31#define META_CR_PERF_COUNT_CTRL_ICACHEMISS \
32 (0xA << META_CR_PERF_COUNT_CTRL_SHIFT)
33#define META_CR_PERF_COUNT_CTRL_ICORE (0xD << META_CR_PERF_COUNT_CTRL_SHIFT)
34#define META_CR_PERF_COUNT_THR_SHIFT (24)
35#define META_CR_PERF_COUNT_THR_MASK (0x0F000000)
36#define META_CR_PERF_COUNT_THR_0 (0x1 << META_CR_PERF_COUNT_THR_SHIFT)
37#define META_CR_PERF_COUNT_THR_1 (0x2 << META_CR_PERF_COUNT_THR_1)
38
39#define META_CR_TxVECINT_BHALT (0x04820500)
40#define META_CR_PERF_ICORE0 (0x0480FFD0)
41#define META_CR_PERF_ICORE1 (0x0480FFD8)
42#define META_CR_PERF_ICORE_DCACHEMISS (0x8)
43
44#define META_CR_PERF_COUNT(ctrl, thr) \
45 ((META_CR_PERF_COUNT_CTRL_##ctrl << META_CR_PERF_COUNT_CTRL_SHIFT) | \
46 ((thr) << META_CR_PERF_COUNT_THR_SHIFT))
47
48#define META_CR_TXUXXRXDT_OFFSET (META_CR_CTRLREG_BASE(0U) + 0x0000FFF0U)
49#define META_CR_TXUXXRXRQ_OFFSET (META_CR_CTRLREG_BASE(0U) + 0x0000FFF8U)
50
51/* Poll for done. */
52#define META_CR_TXUXXRXRQ_DREADY_BIT (0x80000000U)
53/* Set for read. */
54#define META_CR_TXUXXRXRQ_RDnWR_BIT (0x00010000U)
55#define META_CR_TXUXXRXRQ_TX_S (12)
56#define META_CR_TXUXXRXRQ_RX_S (4)
57#define META_CR_TXUXXRXRQ_UXX_S (0)
58
59/* Internal ctrl regs. */
60#define META_CR_TXUIN_ID (0x0)
61/* Data unit regs. */
62#define META_CR_TXUD0_ID (0x1)
63/* Data unit regs. */
64#define META_CR_TXUD1_ID (0x2)
65/* Address unit regs. */
66#define META_CR_TXUA0_ID (0x3)
67/* Address unit regs. */
68#define META_CR_TXUA1_ID (0x4)
69/* PC registers. */
70#define META_CR_TXUPC_ID (0x5)
71
72/* Macros to calculate register access values. */
73#define META_CR_CORE_REG(thr, reg_num, unit) \
74 (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
75 ((u32)(reg_num) << META_CR_TXUXXRXRQ_RX_S) | \
76 ((u32)(unit) << META_CR_TXUXXRXRQ_UXX_S))
77
78#define META_CR_THR0_PC META_CR_CORE_REG(0, 0, META_CR_TXUPC_ID)
79#define META_CR_THR0_PCX META_CR_CORE_REG(0, 1, META_CR_TXUPC_ID)
80#define META_CR_THR0_SP META_CR_CORE_REG(0, 0, META_CR_TXUA0_ID)
81
82#define META_CR_THR1_PC META_CR_CORE_REG(1, 0, META_CR_TXUPC_ID)
83#define META_CR_THR1_PCX META_CR_CORE_REG(1, 1, META_CR_TXUPC_ID)
84#define META_CR_THR1_SP META_CR_CORE_REG(1, 0, META_CR_TXUA0_ID)
85
86#define SP_ACCESS(thread) META_CR_CORE_REG(thread, 0, META_CR_TXUA0_ID)
87#define PC_ACCESS(thread) META_CR_CORE_REG(thread, 0, META_CR_TXUPC_ID)
88
89#define META_CR_COREREG_ENABLE (0x0000000U)
90#define META_CR_COREREG_STATUS (0x0000010U)
91#define META_CR_COREREG_DEFR (0x00000A0U)
92#define META_CR_COREREG_PRIVEXT (0x00000E8U)
93
94#define META_CR_T0ENABLE_OFFSET \
95 (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_ENABLE)
96#define META_CR_T0STATUS_OFFSET \
97 (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_STATUS)
98#define META_CR_T0DEFR_OFFSET (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_DEFR)
99#define META_CR_T0PRIVEXT_OFFSET \
100 (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_PRIVEXT)
101
102#define META_CR_T1ENABLE_OFFSET \
103 (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_ENABLE)
104#define META_CR_T1STATUS_OFFSET \
105 (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_STATUS)
106#define META_CR_T1DEFR_OFFSET (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_DEFR)
107#define META_CR_T1PRIVEXT_OFFSET \
108 (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_PRIVEXT)
109
110#define META_CR_TXENABLE_ENABLE_BIT (0x00000001U) /* Set if running */
111#define META_CR_TXSTATUS_PRIV (0x00020000U)
112#define META_CR_TXPRIVEXT_MINIM (0x00000080U)
113
114#define META_MEM_GLOBAL_RANGE_BIT (0x80000000U)
115
116#define META_CR_TXCLKCTRL (0x048000B0)
117#define META_CR_TXCLKCTRL_ALL_ON (0x55111111)
118#define META_CR_TXCLKCTRL_ALL_AUTO (0xAA222222)
119
120#define META_CR_MMCU_LOCAL_EBCTRL (0x04830600)
121#define META_CR_MMCU_LOCAL_EBCTRL_ICWIN (0x3 << 14)
122#define META_CR_MMCU_LOCAL_EBCTRL_DCWIN (0x3 << 6)
123#define META_CR_SYSC_DCPART(n) (0x04830200 + (n) * 0x8)
124#define META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE (0x1 << 31)
125#define META_CR_SYSC_ICPART(n) (0x04830220 + (n) * 0x8)
126#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF (0x8 << 16)
127#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE (0xF)
128#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE (0x7)
129#define META_CR_MMCU_DCACHE_CTRL (0x04830018)
130#define META_CR_MMCU_ICACHE_CTRL (0x04830020)
131#define META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN (0x1)
132
133/*
134 ******************************************************************************
135 * META LDR Format
136 ******************************************************************************
137 */
138/* Block header structure. */
139struct rogue_meta_ldr_block_hdr {
140 u32 dev_id;
141 u32 sl_code;
142 u32 sl_data;
143 u16 pc_ctrl;
144 u16 crc;
145};
146
147/* High level data stream block structure. */
148struct rogue_meta_ldr_l1_data_blk {
149 u16 cmd;
150 u16 length;
151 u32 next;
152 u32 cmd_data[4];
153};
154
155/* High level data stream block structure. */
156struct rogue_meta_ldr_l2_data_blk {
157 u16 tag;
158 u16 length;
159 u32 block_data[4];
160};
161
162/* Config command structure. */
163struct rogue_meta_ldr_cfg_blk {
164 u32 type;
165 u32 block_data[4];
166};
167
168/* Block type definitions */
169#define ROGUE_META_LDR_COMMENT_TYPE_MASK (0x0010U)
170#define ROGUE_META_LDR_BLK_IS_COMMENT(x) (((x) & ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0U)
171
172/*
173 * Command definitions
174 * Value Name Description
175 * 0 LoadMem Load memory with binary data.
176 * 1 LoadCore Load a set of core registers.
177 * 2 LoadMMReg Load a set of memory mapped registers.
178 * 3 StartThreads Set each thread PC and SP, then enable threads.
179 * 4 ZeroMem Zeros a memory region.
180 * 5 Config Perform a configuration command.
181 */
182#define ROGUE_META_LDR_CMD_MASK (0x000FU)
183
184#define ROGUE_META_LDR_CMD_LOADMEM (0x0000U)
185#define ROGUE_META_LDR_CMD_LOADCORE (0x0001U)
186#define ROGUE_META_LDR_CMD_LOADMMREG (0x0002U)
187#define ROGUE_META_LDR_CMD_START_THREADS (0x0003U)
188#define ROGUE_META_LDR_CMD_ZEROMEM (0x0004U)
189#define ROGUE_META_LDR_CMD_CONFIG (0x0005U)
190
191/*
192 * Config Command definitions
193 * Value Name Description
194 * 0 Pause Pause for x times 100 instructions
195 * 1 Read Read a value from register - No value return needed.
196 * Utilises effects of issuing reads to certain registers
197 * 2 Write Write to mem location
198 * 3 MemSet Set mem to value
199 * 4 MemCheck check mem for specific value.
200 */
201#define ROGUE_META_LDR_CFG_PAUSE (0x0000)
202#define ROGUE_META_LDR_CFG_READ (0x0001)
203#define ROGUE_META_LDR_CFG_WRITE (0x0002)
204#define ROGUE_META_LDR_CFG_MEMSET (0x0003)
205#define ROGUE_META_LDR_CFG_MEMCHECK (0x0004)
206
207/*
208 ******************************************************************************
209 * ROGUE FW segmented MMU definitions
210 ******************************************************************************
211 */
212/* All threads can access the segment. */
213#define ROGUE_FW_SEGMMU_ALLTHRS (0xf << 8U)
214/* Writable. */
215#define ROGUE_FW_SEGMMU_WRITEABLE (0x1U << 1U)
216/* All threads can access and writable. */
217#define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \
218 (ROGUE_FW_SEGMMU_ALLTHRS | ROGUE_FW_SEGMMU_WRITEABLE)
219
220/* Direct map region 10 used for mapping GPU memory - max 8MB. */
221#define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10U)
222#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
223#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
224
225/* Segment IDs. */
226#define ROGUE_FW_SEGMMU_DATA_ID (1U)
227#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2U)
228#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)
229
230/*
231 * SLC caching strategy in S7 and volcanic is emitted through the segment MMU.
232 * All the segments configured through the macro ROGUE_FW_SEGMMU_OUTADDR_TOP are
233 * CACHED in the SLC.
234 * The interface has been kept the same to simplify the code changes.
235 * The bifdm argument is ignored (no longer relevant) in S7 and volcanic.
236 */
237#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
238 ((((u64)((pers) & 0x3)) << 52) | (((u64)((mmu_ctx) & 0xFF)) << 44) | \
239 (((u64)((slc_policy) & 0x1)) << 40))
240#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
241 ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
242#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
243 ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
244
245/*
246 * To configure the Page Catalog and BIF-DM fed into the BIF for Garten
247 * accesses through this segment.
248 */
249#define ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
250 (((u64)((u64)(pc) & 0xFU) << 44U) | ((u64)((u64)(bifdm) & 0xFU) << 40U))
251
252#define ROGUE_FW_SEGMMU_META_BIFDM_ID (0x7U)
253
254/* META segments have 4kB minimum size. */
255#define ROGUE_FW_SEGMMU_ALIGN (0x1000U)
256
257/* Segmented MMU registers (n = segment id). */
258#define META_CR_MMCU_SEGMENT_N_BASE(n) (0x04850000U + ((n) * 0x10U))
259#define META_CR_MMCU_SEGMENT_N_LIMIT(n) (0x04850004U + ((n) * 0x10U))
260#define META_CR_MMCU_SEGMENT_N_OUTA0(n) (0x04850008U + ((n) * 0x10U))
261#define META_CR_MMCU_SEGMENT_N_OUTA1(n) (0x0485000CU + ((n) * 0x10U))
262
263/*
264 * The following defines must be recalculated if the Meta MMU segments used
265 * to access Host-FW data are changed
266 * Current combinations are:
267 * - SLC uncached, META cached, FW base address 0x70000000
268 * - SLC uncached, META uncached, FW base address 0xF0000000
269 * - SLC cached, META cached, FW base address 0x10000000
270 * - SLC cached, META uncached, FW base address 0x90000000
271 */
272#define ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
273#define ROGUE_FW_SEGMMU_DATA_META_CACHED (0x0U)
274#define ROGUE_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
275#define ROGUE_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
276/*
277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
278 * the PTEs for the FW data, not in the Meta Segment MMU, which means these
279 * defines have no real effect in those cases.
280 */
281#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
282#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
283#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
284
285/*
286 ******************************************************************************
287 * ROGUE FW Bootloader defaults
288 ******************************************************************************
289 */
290#define ROGUE_FW_BOOTLDR_META_ADDR (0x40000000U)
291#define ROGUE_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
292#define ROGUE_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
293#define ROGUE_FW_BOOTLDR_DEVV_ADDR \
294 ((((u64)ROGUE_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
295 ROGUE_FW_BOOTLDR_DEVV_ADDR_0)
296#define ROGUE_FW_BOOTLDR_LIMIT (0x1FFFF000)
297#define ROGUE_FW_MAX_BOOTLDR_OFFSET (0x1000)
298
299/* Bootloader configuration offset is in dwords (512 bytes) */
300#define ROGUE_FW_BOOTLDR_CONF_OFFSET (0x80)
301
302/*
303 ******************************************************************************
304 * ROGUE META Stack
305 ******************************************************************************
306 */
307#define ROGUE_META_STACK_SIZE (0x1000U)
308
309/*
310 ******************************************************************************
311 * ROGUE META Core memory
312 ******************************************************************************
313 */
314/* Code and data both map to the same physical memory. */
315#define ROGUE_META_COREMEM_CODE_ADDR (0x80000000U)
316#define ROGUE_META_COREMEM_DATA_ADDR (0x82000000U)
317#define ROGUE_META_COREMEM_OFFSET_MASK (0x01ffffffU)
318
319#define ROGUE_META_IS_COREMEM_CODE(a, b) \
320 ({ \
321 u32 _a = (a), _b = (b); \
322 ((_a) >= ROGUE_META_COREMEM_CODE_ADDR) && \
323 ((_a) < (ROGUE_META_COREMEM_CODE_ADDR + (_b))); \
324 })
325#define ROGUE_META_IS_COREMEM_DATA(a, b) \
326 ({ \
327 u32 _a = (a), _b = (b); \
328 ((_a) >= ROGUE_META_COREMEM_DATA_ADDR) && \
329 ((_a) < (ROGUE_META_COREMEM_DATA_ADDR + (_b))); \
330 })
331/*
332 ******************************************************************************
333 * 2nd thread
334 ******************************************************************************
335 */
336#define ROGUE_FW_THR1_PC (0x18930000)
337#define ROGUE_FW_THR1_SP (0x78890000)
338
339/*
340 ******************************************************************************
341 * META compatibility
342 ******************************************************************************
343 */
344
345#define META_CR_CORE_ID (0x04831000)
346#define META_CR_CORE_ID_VER_SHIFT (16U)
347#define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
348
349#define ROGUE_CR_META_MTP218_CORE_ID_VALUE 0x19
350#define ROGUE_CR_META_MTP219_CORE_ID_VALUE 0x1E
351#define ROGUE_CR_META_LTP218_CORE_ID_VALUE 0x1C
352#define ROGUE_CR_META_LTP217_CORE_ID_VALUE 0x1F
353
354#define ROGUE_FW_PROCESSOR_META "META"
355
356#endif /* PVR_ROGUE_META_H */
357

source code of linux/drivers/gpu/drm/imagination/pvr_rogue_meta.h