1/*
2 * SPDX-License-Identifier: MIT
3 */
4
5#include <drm/drm_print.h>
6
7#include "display/intel_overlay.h"
8#include "gem/i915_gem_mman.h"
9#include "gt/intel_engine_user.h"
10#include "pxp/intel_pxp.h"
11
12#include "i915_cmd_parser.h"
13#include "i915_drv.h"
14#include "i915_getparam.h"
15#include "i915_perf.h"
16
17int i915_getparam_ioctl(struct drm_device *dev, void *data,
18 struct drm_file *file_priv)
19{
20 struct drm_i915_private *i915 = to_i915(dev);
21 struct intel_display *display = i915->display;
22 struct pci_dev *pdev = to_pci_dev(dev->dev);
23 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
24 drm_i915_getparam_t *param = data;
25 int value = 0;
26
27 switch (param->param) {
28 case I915_PARAM_IRQ_ACTIVE:
29 case I915_PARAM_ALLOW_BATCHBUFFER:
30 case I915_PARAM_LAST_DISPATCH:
31 case I915_PARAM_HAS_EXEC_CONSTANTS:
32 /* Reject all old ums/dri params. */
33 return -ENODEV;
34 case I915_PARAM_CHIPSET_ID:
35 value = pdev->device;
36 break;
37 case I915_PARAM_REVISION:
38 value = pdev->revision;
39 break;
40 case I915_PARAM_NUM_FENCES_AVAIL:
41 value = to_gt(i915)->ggtt->num_fences;
42 break;
43 case I915_PARAM_HAS_OVERLAY:
44 value = intel_overlay_available(display);
45 break;
46 case I915_PARAM_HAS_BSD:
47 value = !!intel_engine_lookup_user(i915,
48 class: I915_ENGINE_CLASS_VIDEO, instance: 0);
49 break;
50 case I915_PARAM_HAS_BLT:
51 value = !!intel_engine_lookup_user(i915,
52 class: I915_ENGINE_CLASS_COPY, instance: 0);
53 break;
54 case I915_PARAM_HAS_VEBOX:
55 value = !!intel_engine_lookup_user(i915,
56 class: I915_ENGINE_CLASS_VIDEO_ENHANCE, instance: 0);
57 break;
58 case I915_PARAM_HAS_BSD2:
59 value = !!intel_engine_lookup_user(i915,
60 class: I915_ENGINE_CLASS_VIDEO, instance: 1);
61 break;
62 case I915_PARAM_HAS_LLC:
63 value = HAS_LLC(i915);
64 break;
65 case I915_PARAM_HAS_WT:
66 value = HAS_WT(i915);
67 break;
68 case I915_PARAM_HAS_ALIASING_PPGTT:
69 value = INTEL_PPGTT(i915);
70 break;
71 case I915_PARAM_HAS_SEMAPHORES:
72 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
73 break;
74 case I915_PARAM_HAS_SECURE_BATCHES:
75 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
76 break;
77 case I915_PARAM_CMD_PARSER_VERSION:
78 value = i915_cmd_parser_get_version(dev_priv: i915);
79 break;
80 case I915_PARAM_SUBSLICE_TOTAL:
81 value = intel_sseu_subslice_total(sseu);
82 if (!value)
83 return -ENODEV;
84 break;
85 case I915_PARAM_EU_TOTAL:
86 value = sseu->eu_total;
87 if (!value)
88 return -ENODEV;
89 break;
90 case I915_PARAM_HAS_GPU_RESET:
91 value = i915->params.enable_hangcheck &&
92 intel_has_gpu_reset(gt: to_gt(i915));
93 if (value && intel_has_reset_engine(gt: to_gt(i915)))
94 value = 2;
95 break;
96 case I915_PARAM_HAS_RESOURCE_STREAMER:
97 value = 0;
98 break;
99 case I915_PARAM_HAS_POOLED_EU:
100 value = HAS_POOLED_EU(i915);
101 break;
102 case I915_PARAM_MIN_EU_IN_POOL:
103 value = sseu->min_eu_in_pool;
104 break;
105 case I915_PARAM_HUC_STATUS:
106 /* On platform with a media GT, the HuC is on that GT */
107 if (i915->media_gt)
108 value = intel_huc_check_status(huc: &i915->media_gt->uc.huc);
109 else
110 value = intel_huc_check_status(huc: &to_gt(i915)->uc.huc);
111 if (value < 0)
112 return value;
113 break;
114 case I915_PARAM_PXP_STATUS:
115 value = intel_pxp_get_readiness_status(pxp: i915->pxp, timeout_ms: 0);
116 if (value < 0)
117 return value;
118 break;
119 case I915_PARAM_MMAP_GTT_VERSION:
120 /* Though we've started our numbering from 1, and so class all
121 * earlier versions as 0, in effect their value is undefined as
122 * the ioctl will report EINVAL for the unknown param!
123 */
124 value = i915_gem_mmap_gtt_version();
125 break;
126 case I915_PARAM_HAS_SCHEDULER:
127 value = i915->caps.scheduler;
128 break;
129
130 case I915_PARAM_MMAP_VERSION:
131 /* Remember to bump this if the version changes! */
132 case I915_PARAM_HAS_GEM:
133 case I915_PARAM_HAS_PAGEFLIPPING:
134 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
135 case I915_PARAM_HAS_RELAXED_FENCING:
136 case I915_PARAM_HAS_COHERENT_RINGS:
137 case I915_PARAM_HAS_RELAXED_DELTA:
138 case I915_PARAM_HAS_GEN7_SOL_RESET:
139 case I915_PARAM_HAS_WAIT_TIMEOUT:
140 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
141 case I915_PARAM_HAS_PINNED_BATCHES:
142 case I915_PARAM_HAS_EXEC_NO_RELOC:
143 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
144 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
145 case I915_PARAM_HAS_EXEC_SOFTPIN:
146 case I915_PARAM_HAS_EXEC_ASYNC:
147 case I915_PARAM_HAS_EXEC_FENCE:
148 case I915_PARAM_HAS_EXEC_CAPTURE:
149 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
150 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
151 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
152 case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
153 case I915_PARAM_HAS_USERPTR_PROBE:
154 /* For the time being all of these are always true;
155 * if some supported hardware does not have one of these
156 * features this value needs to be provided from
157 * INTEL_INFO(), a feature macro, or similar.
158 */
159 value = 1;
160 break;
161 case I915_PARAM_HAS_CONTEXT_FREQ_HINT:
162 if (intel_uc_uses_guc_submission(uc: &to_gt(i915)->uc))
163 value = 1;
164 else
165 value = -EINVAL;
166 break;
167 case I915_PARAM_HAS_CONTEXT_ISOLATION:
168 value = intel_engines_has_context_isolation(i915);
169 break;
170 case I915_PARAM_SLICE_MASK:
171 /* Not supported from Xe_HP onward; use topology queries */
172 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
173 return -EINVAL;
174
175 value = sseu->slice_mask;
176 if (!value)
177 return -ENODEV;
178 break;
179 case I915_PARAM_SUBSLICE_MASK:
180 /* Not supported from Xe_HP onward; use topology queries */
181 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
182 return -EINVAL;
183
184 /* Only copy bits from the first slice */
185 value = intel_sseu_get_hsw_subslices(sseu, slice: 0);
186 if (!value)
187 return -ENODEV;
188 break;
189 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
190 value = to_gt(i915)->clock_frequency;
191 break;
192 case I915_PARAM_MMAP_GTT_COHERENT:
193 value = INTEL_INFO(i915)->has_coherent_ggtt;
194 break;
195 case I915_PARAM_PERF_REVISION:
196 value = i915_perf_ioctl_version(i915);
197 break;
198 case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
199 value = i915_perf_oa_timestamp_frequency(i915);
200 break;
201 default:
202 drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param);
203 return -EINVAL;
204 }
205
206 if (put_user(value, param->value))
207 return -EFAULT;
208
209 return 0;
210}
211

source code of linux/drivers/gpu/drm/i915/i915_getparam.c