| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2020 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __GEN6_ENGINE_CS_H__ |
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| 7 | #define __GEN6_ENGINE_CS_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #include "intel_gpu_commands.h" |
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| 12 | |
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| 13 | struct i915_request; |
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| 14 | struct intel_engine_cs; |
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| 15 | |
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| 16 | int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode); |
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| 17 | int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode); |
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| 18 | int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode); |
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| 19 | u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); |
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| 20 | u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); |
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| 21 | |
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| 22 | int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode); |
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| 23 | u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); |
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| 24 | u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); |
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| 25 | |
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| 26 | int gen6_emit_bb_start(struct i915_request *rq, |
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| 27 | u64 offset, u32 len, |
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| 28 | unsigned int dispatch_flags); |
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| 29 | int hsw_emit_bb_start(struct i915_request *rq, |
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| 30 | u64 offset, u32 len, |
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| 31 | unsigned int dispatch_flags); |
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| 32 | |
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| 33 | void gen6_irq_enable(struct intel_engine_cs *engine); |
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| 34 | void gen6_irq_disable(struct intel_engine_cs *engine); |
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| 35 | |
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| 36 | void hsw_irq_enable_vecs(struct intel_engine_cs *engine); |
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| 37 | void hsw_irq_disable_vecs(struct intel_engine_cs *engine); |
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| 38 | |
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| 39 | #endif /* __GEN6_ENGINE_CS_H__ */ |
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| 40 | |
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