1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26 */
27
28#include <linux/iopoll.h>
29#include <linux/kernel.h>
30#include <linux/string_helpers.h>
31
32#include <drm/drm_print.h>
33
34#include "intel_de.h"
35#include "intel_display_types.h"
36#include "intel_dsi.h"
37#include "vlv_dsi_pll.h"
38#include "vlv_dsi_pll_regs.h"
39#include "vlv_sideband.h"
40
41static const u16 lfsr_converts[] = {
42 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
43 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
44 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
45 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
46};
47
48/* Get DSI clock from pixel clock */
49static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
50 int lane_count)
51{
52 u32 dsi_clk_khz;
53 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
54
55 /* DSI data rate = pixel clock * bits per pixel / lane count
56 pixel clock is converted from KHz to Hz */
57 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
58
59 return dsi_clk_khz;
60}
61
62static int dsi_calc_mnp(struct intel_display *display,
63 struct intel_crtc_state *config,
64 int target_dsi_clk)
65{
66 unsigned int m_min, m_max, p_min = 2, p_max = 6;
67 unsigned int m, n, p;
68 unsigned int calc_m, calc_p;
69 int delta, ref_clk;
70
71 /* target_dsi_clk is expected in kHz */
72 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
73 drm_err(display->drm, "DSI CLK Out of Range\n");
74 return -ECHRNG;
75 }
76
77 if (display->platform.cherryview) {
78 ref_clk = 100000;
79 n = 4;
80 m_min = 70;
81 m_max = 96;
82 } else {
83 ref_clk = 25000;
84 n = 1;
85 m_min = 62;
86 m_max = 92;
87 }
88
89 calc_p = p_min;
90 calc_m = m_min;
91 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
92
93 for (m = m_min; m <= m_max && delta; m++) {
94 for (p = p_min; p <= p_max && delta; p++) {
95 /*
96 * Find the optimal m and p divisors with minimal delta
97 * +/- the required clock
98 */
99 int calc_dsi_clk = (m * ref_clk) / (p * n);
100 int d = abs(target_dsi_clk - calc_dsi_clk);
101 if (d < delta) {
102 delta = d;
103 calc_m = m;
104 calc_p = p;
105 }
106 }
107 }
108
109 /* register has log2(N1), this works fine for powers of two */
110 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
111 config->dsi_pll.div =
112 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
113 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
114
115 return 0;
116}
117
118static int vlv_dsi_pclk(struct intel_encoder *encoder,
119 struct intel_crtc_state *config)
120{
121 struct intel_display *display = to_intel_display(encoder);
122 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
123 int bpp = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
124 u32 dsi_clock;
125 u32 pll_ctl, pll_div;
126 u32 m = 0, p = 0, n;
127 int refclk = display->platform.cherryview ? 100000 : 25000;
128 int i;
129
130 pll_ctl = config->dsi_pll.ctrl;
131 pll_div = config->dsi_pll.div;
132
133 /* mask out other bits and extract the P1 divisor */
134 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
135 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
136
137 /* N1 divisor */
138 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
139 n = 1 << n; /* register has log2(N1) */
140
141 /* mask out the other bits and extract the M1 divisor */
142 pll_div &= DSI_PLL_M1_DIV_MASK;
143 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
144
145 p = fls(x: pll_ctl);
146 if (p)
147 p--;
148
149 if (!p) {
150 drm_err(display->drm, "wrong P1 divisor\n");
151 return 0;
152 }
153
154 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
155 if (lfsr_converts[i] == pll_div)
156 break;
157 }
158
159 if (i == ARRAY_SIZE(lfsr_converts)) {
160 drm_err(display->drm, "wrong m_seed programmed\n");
161 return 0;
162 }
163
164 m = i + 62;
165
166 dsi_clock = (m * refclk) / (p * n);
167
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
169}
170
171/*
172 * XXX: The muxing and gating is hard coded for now. Need to add support for
173 * sharing PLLs with two DSI outputs.
174 */
175int vlv_dsi_pll_compute(struct intel_encoder *encoder,
176 struct intel_crtc_state *config)
177{
178 struct intel_display *display = to_intel_display(encoder);
179 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
180 int pclk, dsi_clk, ret;
181
182 dsi_clk = dsi_clk_from_pclk(pclk: intel_dsi->pclk, fmt: intel_dsi->pixel_format,
183 lane_count: intel_dsi->lane_count);
184
185 ret = dsi_calc_mnp(display, config, target_dsi_clk: dsi_clk);
186 if (ret) {
187 drm_dbg_kms(display->drm, "dsi_calc_mnp failed\n");
188 return ret;
189 }
190
191 if (intel_dsi->ports & (1 << PORT_A))
192 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
193
194 if (intel_dsi->ports & (1 << PORT_C))
195 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
196
197 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
198
199 drm_dbg_kms(display->drm, "dsi pll div %08x, ctrl %08x\n",
200 config->dsi_pll.div, config->dsi_pll.ctrl);
201
202 pclk = vlv_dsi_pclk(encoder, config);
203 config->port_clock = pclk;
204
205 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
206 config->hw.adjusted_mode.crtc_clock = pclk;
207 if (intel_dsi->dual_link)
208 config->hw.adjusted_mode.crtc_clock *= 2;
209
210 return 0;
211}
212
213void vlv_dsi_pll_enable(struct intel_encoder *encoder,
214 const struct intel_crtc_state *config)
215{
216 struct intel_display *display = to_intel_display(encoder);
217 u32 val;
218 int ret;
219
220 drm_dbg_kms(display->drm, "\n");
221
222 vlv_cck_get(drm: display->drm);
223
224 vlv_cck_write(drm: display->drm, CCK_REG_DSI_PLL_CONTROL, val: 0);
225 vlv_cck_write(drm: display->drm, CCK_REG_DSI_PLL_DIVIDER, val: config->dsi_pll.div);
226 vlv_cck_write(drm: display->drm, CCK_REG_DSI_PLL_CONTROL,
227 val: config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
228
229 /* wait at least 0.5 us after ungating before enabling VCO,
230 * allow hrtimer subsystem optimization by relaxing timing
231 */
232 usleep_range(min: 10, max: 50);
233
234 vlv_cck_write(drm: display->drm, CCK_REG_DSI_PLL_CONTROL, val: config->dsi_pll.ctrl);
235
236 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),
237 val & DSI_PLL_LOCK,
238 500, 20 * 1000, false);
239 if (ret) {
240 vlv_cck_put(drm: display->drm);
241 drm_err(display->drm, "DSI PLL lock failed\n");
242 return;
243 }
244 vlv_cck_put(drm: display->drm);
245
246 drm_dbg_kms(display->drm, "DSI PLL locked\n");
247}
248
249void vlv_dsi_pll_disable(struct intel_encoder *encoder)
250{
251 struct intel_display *display = to_intel_display(encoder);
252 u32 tmp;
253
254 drm_dbg_kms(display->drm, "\n");
255
256 vlv_cck_get(drm: display->drm);
257
258 tmp = vlv_cck_read(drm: display->drm, CCK_REG_DSI_PLL_CONTROL);
259 tmp &= ~DSI_PLL_VCO_EN;
260 tmp |= DSI_PLL_LDO_GATE;
261 vlv_cck_write(drm: display->drm, CCK_REG_DSI_PLL_CONTROL, val: tmp);
262
263 vlv_cck_put(drm: display->drm);
264}
265
266static bool has_dsic_clock(struct intel_display *display)
267{
268 return display->platform.broxton;
269}
270
271bool bxt_dsi_pll_is_enabled(struct intel_display *display)
272{
273 bool enabled;
274 u32 val;
275 u32 mask;
276
277 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
278 val = intel_de_read(display, BXT_DSI_PLL_ENABLE);
279 enabled = (val & mask) == mask;
280
281 if (!enabled)
282 return false;
283
284 /*
285 * Dividers must be programmed with valid values. As per BSEPC, for
286 * GEMINLAKE only PORT A divider values are checked while for BXT
287 * both divider values are validated. Check this here for
288 * paranoia, since BIOS is known to misconfigure PLLs in this way at
289 * times, and since accessing DSI registers with invalid dividers
290 * causes a system hang.
291 */
292 val = intel_de_read(display, BXT_DSI_PLL_CTL);
293 if (!has_dsic_clock(display)) {
294 if (!(val & BXT_DSIA_16X_MASK)) {
295 drm_dbg_kms(display->drm,
296 "Invalid PLL divider (%08x)\n", val);
297 enabled = false;
298 }
299 } else {
300 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
301 drm_dbg_kms(display->drm,
302 "Invalid PLL divider (%08x)\n", val);
303 enabled = false;
304 }
305 }
306
307 return enabled;
308}
309
310void bxt_dsi_pll_disable(struct intel_encoder *encoder)
311{
312 struct intel_display *display = to_intel_display(encoder);
313
314 drm_dbg_kms(display->drm, "\n");
315
316 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, set: 0);
317
318 /*
319 * PLL lock should deassert within 200us.
320 * Wait up to 1ms before timing out.
321 */
322 if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,
323 BXT_DSI_PLL_LOCKED, timeout_ms: 1))
324 drm_err(display->drm,
325 "Timeout waiting for PLL lock deassertion\n");
326}
327
328u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
329 struct intel_crtc_state *config)
330{
331 struct intel_display *display = to_intel_display(encoder);
332 u32 pll_ctl, pll_div;
333
334 drm_dbg_kms(display->drm, "\n");
335
336 vlv_cck_get(drm: display->drm);
337 pll_ctl = vlv_cck_read(drm: display->drm, CCK_REG_DSI_PLL_CONTROL);
338 pll_div = vlv_cck_read(drm: display->drm, CCK_REG_DSI_PLL_DIVIDER);
339 vlv_cck_put(drm: display->drm);
340
341 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
342 config->dsi_pll.div = pll_div;
343
344 return vlv_dsi_pclk(encoder, config);
345}
346
347static int bxt_dsi_pclk(struct intel_encoder *encoder,
348 const struct intel_crtc_state *config)
349{
350 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
351 int bpp = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
352 u32 dsi_ratio, dsi_clk;
353
354 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
355 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
356
357 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
358}
359
360u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
361 struct intel_crtc_state *config)
362{
363 struct intel_display *display = to_intel_display(encoder);
364 u32 pclk;
365
366 config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
367 if (!has_dsic_clock(display))
368 config->dsi_pll.ctrl &= ~BXT_DSIC_16X_MASK;
369
370 pclk = bxt_dsi_pclk(encoder, config);
371
372 drm_dbg_kms(display->drm, "Calculated pclk=%u\n", pclk);
373 return pclk;
374}
375
376void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
377{
378 struct intel_display *display = to_intel_display(encoder);
379 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
380 u32 temp;
381
382 temp = intel_de_read(display, MIPI_CTRL(display, port));
383 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
384 intel_de_write(display, MIPI_CTRL(display, port),
385 val: temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);
386}
387
388static void glk_dsi_program_esc_clock(struct intel_display *display,
389 const struct intel_crtc_state *config)
390{
391 u32 dsi_rate = 0;
392 u32 pll_ratio = 0;
393 u32 ddr_clk = 0;
394 u32 div1_value = 0;
395 u32 div2_value = 0;
396 u32 txesc1_div = 0;
397 u32 txesc2_div = 0;
398
399 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
400
401 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
402
403 ddr_clk = dsi_rate / 2;
404
405 /* Variable divider value */
406 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
407
408 /* Calculate TXESC1 divider */
409 if (div1_value <= 10)
410 txesc1_div = div1_value;
411 else if ((div1_value > 10) && (div1_value <= 20))
412 txesc1_div = DIV_ROUND_UP(div1_value, 2);
413 else if ((div1_value > 20) && (div1_value <= 30))
414 txesc1_div = DIV_ROUND_UP(div1_value, 4);
415 else if ((div1_value > 30) && (div1_value <= 40))
416 txesc1_div = DIV_ROUND_UP(div1_value, 6);
417 else if ((div1_value > 40) && (div1_value <= 50))
418 txesc1_div = DIV_ROUND_UP(div1_value, 8);
419 else
420 txesc1_div = 10;
421
422 /* Calculate TXESC2 divider */
423 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
424
425 txesc2_div = min_t(u32, div2_value, 10);
426
427 intel_de_write(display, MIPIO_TXESC_CLK_DIV1,
428 val: (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
429 intel_de_write(display, MIPIO_TXESC_CLK_DIV2,
430 val: (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
431}
432
433/* Program BXT Mipi clocks and dividers */
434static void bxt_dsi_program_clocks(struct intel_display *display, enum port port,
435 const struct intel_crtc_state *config)
436{
437 u32 tmp;
438 u32 dsi_rate = 0;
439 u32 pll_ratio = 0;
440 u32 rx_div;
441 u32 tx_div;
442 u32 rx_div_upper;
443 u32 rx_div_lower;
444 u32 mipi_8by3_divider;
445
446 /* Clear old configurations */
447 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
448 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
449 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
450 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
451 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
452
453 /* Get the current DSI rate(actual) */
454 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
455 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
456
457 /*
458 * tx clock should be <= 20MHz and the div value must be
459 * subtracted by 1 as per bspec
460 */
461 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
462 /*
463 * rx clock should be <= 150MHz and the div value must be
464 * subtracted by 1 as per bspec
465 */
466 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
467
468 /*
469 * rx divider value needs to be updated in the
470 * two different bit fields in the register hence splitting the
471 * rx divider value accordingly
472 */
473 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
474 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
475
476 mipi_8by3_divider = 0x2;
477
478 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
479 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
480 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
481 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
482
483 intel_de_write(display, BXT_MIPI_CLOCK_CTL, val: tmp);
484}
485
486int bxt_dsi_pll_compute(struct intel_encoder *encoder,
487 struct intel_crtc_state *config)
488{
489 struct intel_display *display = to_intel_display(encoder);
490 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
491 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
492 u32 dsi_clk;
493 int pclk;
494
495 dsi_clk = dsi_clk_from_pclk(pclk: intel_dsi->pclk, fmt: intel_dsi->pixel_format,
496 lane_count: intel_dsi->lane_count);
497
498 /*
499 * From clock diagram, to get PLL ratio divider, divide double of DSI
500 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
501 * round 'up' the result
502 */
503 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
504
505 if (display->platform.broxton) {
506 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
507 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
508 } else {
509 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
510 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
511 }
512
513 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
514 drm_err(display->drm,
515 "Can't get a suitable ratio from DSI PLL ratios\n");
516 return -ECHRNG;
517 } else
518 drm_dbg_kms(display->drm, "DSI PLL calculation is Done!!\n");
519
520 /*
521 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
522 * Spec says both have to be programmed, even if one is not getting
523 * used. Configure MIPI_CLOCK_CTL dividers in modeset
524 */
525 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2;
526 if (has_dsic_clock(display))
527 config->dsi_pll.ctrl |= BXT_DSIC_16X_BY2;
528
529 /* As per recommendation from hardware team,
530 * Prog PVD ratio =1 if dsi ratio <= 50
531 */
532 if (display->platform.broxton && dsi_ratio <= 50)
533 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
534
535 pclk = bxt_dsi_pclk(encoder, config);
536 config->port_clock = pclk;
537
538 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
539 config->hw.adjusted_mode.crtc_clock = pclk;
540 if (intel_dsi->dual_link)
541 config->hw.adjusted_mode.crtc_clock *= 2;
542
543 return 0;
544}
545
546void bxt_dsi_pll_enable(struct intel_encoder *encoder,
547 const struct intel_crtc_state *config)
548{
549 struct intel_display *display = to_intel_display(encoder);
550 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
551 enum port port;
552
553 drm_dbg_kms(display->drm, "\n");
554
555 /* Configure PLL vales */
556 intel_de_write(display, BXT_DSI_PLL_CTL, val: config->dsi_pll.ctrl);
557 intel_de_posting_read(display, BXT_DSI_PLL_CTL);
558
559 /* Program TX, RX, Dphy clocks */
560 if (display->platform.broxton) {
561 for_each_dsi_port(port, intel_dsi->ports)
562 bxt_dsi_program_clocks(display, port, config);
563 } else {
564 glk_dsi_program_esc_clock(display, config);
565 }
566
567 /* Enable DSI PLL */
568 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, clear: 0, BXT_DSI_PLL_DO_ENABLE);
569
570 /* Timeout and fail if PLL not locked */
571 if (intel_de_wait_for_set_ms(display, BXT_DSI_PLL_ENABLE,
572 BXT_DSI_PLL_LOCKED, timeout_ms: 1)) {
573 drm_err(display->drm,
574 "Timed out waiting for DSI PLL to lock\n");
575 return;
576 }
577
578 drm_dbg_kms(display->drm, "DSI PLL locked\n");
579}
580
581void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
582{
583 struct intel_display *display = to_intel_display(encoder);
584 u32 tmp;
585
586 /* Clear old configurations */
587 if (display->platform.broxton) {
588 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);
589 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
590 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
591 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
592 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
593 intel_de_write(display, BXT_MIPI_CLOCK_CTL, val: tmp);
594 } else {
595 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, set: 0);
596
597 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, set: 0);
598 }
599 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
600}
601
602static void assert_dsi_pll(struct intel_display *display, bool state)
603{
604 bool cur_state;
605
606 vlv_cck_get(drm: display->drm);
607 cur_state = vlv_cck_read(drm: display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
608 vlv_cck_put(drm: display->drm);
609
610 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
611 "DSI PLL state assertion failure (expected %s, current %s)\n",
612 str_on_off(state), str_on_off(cur_state));
613}
614
615void assert_dsi_pll_enabled(struct intel_display *display)
616{
617 assert_dsi_pll(display, state: true);
618}
619
620void assert_dsi_pll_disabled(struct intel_display *display)
621{
622 assert_dsi_pll(display, state: false);
623}
624

source code of linux/drivers/gpu/drm/i915/display/vlv_dsi_pll.c