| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __SKL_WATERMARK_REGS_H__ |
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| 7 | #define __SKL_WATERMARK_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _PIPEA_MBUS_DBOX_CTL 0x7003C |
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| 12 | #define _PIPEB_MBUS_DBOX_CTL 0x7103C |
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| 13 | #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ |
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| 14 | _PIPEB_MBUS_DBOX_CTL) |
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| 15 | #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ |
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| 16 | #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) |
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| 17 | #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ |
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| 18 | #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) |
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| 19 | #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ |
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| 20 | #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) |
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| 21 | #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) |
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| 22 | #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) |
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| 23 | #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) |
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| 24 | #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) |
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| 25 | #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) |
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| 26 | #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) |
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| 27 | #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) |
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| 28 | #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) |
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| 29 | #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) |
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| 30 | |
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| 31 | #define MBUS_UBOX_CTL _MMIO(0x4503C) |
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| 32 | #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) |
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| 33 | #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) |
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| 34 | |
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| 35 | #define MBUS_CTL _MMIO(0x4438C) |
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| 36 | #define MBUS_JOIN REG_BIT(31) |
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| 37 | #define MBUS_HASHING_MODE_MASK REG_BIT(30) |
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| 38 | #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) |
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| 39 | #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) |
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| 40 | #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) |
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| 41 | #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) |
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| 42 | #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) |
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| 43 | #define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13) |
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| 44 | #define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) |
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| 45 | #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) |
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| 46 | #define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) |
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| 47 | |
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| 48 | /* |
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| 49 | * The below are numbered starting from "S1" on gen11/gen12, but starting |
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| 50 | * with display 13, the bspec switches to a 0-based numbering scheme |
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| 51 | * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). |
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| 52 | * We'll just use the 0-based numbering here for all platforms since it's the |
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| 53 | * way things will be named by the hardware team going forward, plus it's more |
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| 54 | * consistent with how most of the rest of our registers are named. |
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| 55 | */ |
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| 56 | #define _DBUF_CTL_S0 0x45008 |
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| 57 | #define _DBUF_CTL_S1 0x44FE8 |
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| 58 | #define _DBUF_CTL_S2 0x44300 |
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| 59 | #define _DBUF_CTL_S3 0x44304 |
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| 60 | #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ |
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| 61 | _DBUF_CTL_S0, \ |
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| 62 | _DBUF_CTL_S1, \ |
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| 63 | _DBUF_CTL_S2, \ |
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| 64 | _DBUF_CTL_S3)) |
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| 65 | #define DBUF_POWER_REQUEST REG_BIT(31) |
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| 66 | #define DBUF_POWER_STATE REG_BIT(30) |
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| 67 | #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) |
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| 68 | #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) |
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| 69 | #define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20, 16) |
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| 70 | #define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) |
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| 71 | #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ |
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| 72 | #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ |
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| 73 | |
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| 74 | #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) |
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| 75 | #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) |
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| 76 | #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) |
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| 77 | #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) |
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| 78 | #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) |
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| 79 | |
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| 80 | #define MTL_LATENCY_SAGV _MMIO(0x4578c) |
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| 81 | #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) |
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| 82 | |
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| 83 | #define LNL_PKG_C_LATENCY _MMIO(0x46460) |
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| 84 | #define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16) |
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| 85 | #define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0) |
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| 86 | |
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| 87 | #endif /* __SKL_WATERMARK_REGS_H__ */ |
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| 88 | |
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