1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include <drm/drm_print.h>
7
8#include "intel_casf.h"
9#include "intel_casf_regs.h"
10#include "intel_de.h"
11#include "intel_display_regs.h"
12#include "intel_display_trace.h"
13#include "intel_display_types.h"
14#include "intel_display_utils.h"
15#include "intel_display_wa.h"
16#include "intel_fb.h"
17#include "skl_scaler.h"
18#include "skl_universal_plane.h"
19
20/*
21 * The hardware phase 0.0 refers to the center of the pixel.
22 * We want to start from the top/left edge which is phase
23 * -0.5. That matches how the hardware calculates the scaling
24 * factors (from top-left of the first pixel to bottom-right
25 * of the last pixel, as opposed to the pixel centers).
26 *
27 * For 4:2:0 subsampled chroma planes we obviously have to
28 * adjust that so that the chroma sample position lands in
29 * the right spot.
30 *
31 * Note that for packed YCbCr 4:2:2 formats there is no way to
32 * control chroma siting. The hardware simply replicates the
33 * chroma samples for both of the luma samples, and thus we don't
34 * actually get the expected MPEG2 chroma siting convention :(
35 * The same behaviour is observed on pre-SKL platforms as well.
36 *
37 * Theory behind the formula (note that we ignore sub-pixel
38 * source coordinates):
39 * s = source sample position
40 * d = destination sample position
41 *
42 * Downscaling 4:1:
43 * -0.5
44 * | 0.0
45 * | | 1.5 (initial phase)
46 * | | |
47 * v v v
48 * | s | s | s | s |
49 * | d |
50 *
51 * Upscaling 1:4:
52 * -0.5
53 * | -0.375 (initial phase)
54 * | | 0.0
55 * | | |
56 * v v v
57 * | s |
58 * | d | d | d | d |
59 */
60static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
61{
62 int phase = -0x8000;
63 u16 trip = 0;
64
65 if (chroma_cosited)
66 phase += (sub - 1) * 0x8000 / sub;
67
68 phase += scale / (2 * sub);
69
70 /*
71 * Hardware initial phase limited to [-0.5:1.5].
72 * Since the max hardware scale factor is 3.0, we
73 * should never actually exceed 1.0 here.
74 */
75 WARN_ON(phase < -0x8000 || phase > 0x18000);
76
77 if (phase < 0)
78 phase = 0x10000 + phase;
79 else
80 trip = PS_PHASE_TRIP;
81
82 return ((phase >> 2) & PS_PHASE_MASK) | trip;
83}
84
85static void skl_scaler_min_src_size(const struct drm_format_info *format,
86 u64 modifier, int *min_w, int *min_h)
87{
88 if (format && intel_format_info_is_yuv_semiplanar(info: format, modifier)) {
89 *min_w = 16;
90 *min_h = 16;
91 } else {
92 *min_w = 8;
93 *min_h = 8;
94 }
95}
96
97static void skl_scaler_max_src_size(struct intel_display *display,
98 int *max_w, int *max_h)
99{
100 if (DISPLAY_VER(display) >= 14) {
101 *max_w = 4096;
102 *max_h = 8192;
103 } else if (DISPLAY_VER(display) >= 12) {
104 *max_w = 5120;
105 *max_h = 8192;
106 } else if (DISPLAY_VER(display) == 11) {
107 *max_w = 5120;
108 *max_h = 4096;
109 } else {
110 *max_w = 4096;
111 *max_h = 4096;
112 }
113}
114
115static void skl_scaler_min_dst_size(int *min_w, int *min_h)
116{
117 *min_w = 8;
118 *min_h = 8;
119}
120
121static void skl_scaler_max_dst_size(struct intel_crtc *crtc,
122 int *max_w, int *max_h)
123{
124 struct intel_display *display = to_intel_display(crtc);
125
126 if (DISPLAY_VER(display) >= 12) {
127 *max_w = 8192;
128 *max_h = 8192;
129 } else if (DISPLAY_VER(display) == 11) {
130 *max_w = 5120;
131 *max_h = 4096;
132 } else {
133 *max_w = 4096;
134 *max_h = 4096;
135 }
136}
137
138enum drm_mode_status
139skl_scaler_mode_valid(struct intel_display *display,
140 const struct drm_display_mode *mode,
141 enum intel_output_format output_format,
142 int num_joined_pipes)
143{
144 int max_h, max_w;
145
146 if (num_joined_pipes < 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
147 skl_scaler_max_src_size(display, max_w: &max_w, max_h: &max_h);
148 if (mode->hdisplay > max_h)
149 return MODE_NO_420;
150 }
151
152 return MODE_OK;
153}
154
155static int
156skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
157 unsigned int scaler_user, int *scaler_id,
158 int src_w, int src_h, int dst_w, int dst_h,
159 const struct drm_format_info *format,
160 u64 modifier, bool need_scaler)
161{
162 struct intel_display *display = to_intel_display(crtc_state);
163 struct intel_crtc_scaler_state *scaler_state =
164 &crtc_state->scaler_state;
165 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
166 const struct drm_display_mode *adjusted_mode =
167 &crtc_state->hw.adjusted_mode;
168 int pipe_src_w = drm_rect_width(r: &crtc_state->pipe_src);
169 int pipe_src_h = drm_rect_height(r: &crtc_state->pipe_src);
170 int min_src_w, min_src_h, min_dst_w, min_dst_h;
171 int max_src_w, max_src_h, max_dst_w, max_dst_h;
172
173 /*
174 * Src coordinates are already rotated by 270 degrees for
175 * the 90/270 degree plane rotation cases (to match the
176 * GTT mapping), hence no need to account for rotation here.
177 */
178 if (src_w != dst_w || src_h != dst_h)
179 need_scaler = true;
180
181 /*
182 * Scaling/fitting not supported in IF-ID mode in GEN9+
183 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
184 * Once NV12 is enabled, handle it here while allocating scaler
185 * for NV12.
186 */
187 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&
188 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
189 drm_dbg_kms(display->drm,
190 "[CRTC:%d:%s] scaling not supported with IF-ID mode\n",
191 crtc->base.base.id, crtc->base.name);
192 return -EINVAL;
193 }
194
195 /*
196 * if plane is being disabled or scaler is no more required or force detach
197 * - free scaler binded to this plane/crtc
198 * - in order to do this, update crtc->scaler_usage
199 *
200 * Here scaler state in crtc_state is set free so that
201 * scaler can be assigned to other user. Actual register
202 * update to free the scaler is done in plane/panel-fit programming.
203 * For this purpose crtc/plane_state->scaler_id isn't reset here.
204 */
205 if (force_detach || !need_scaler) {
206 if (*scaler_id >= 0) {
207 scaler_state->scaler_users &= ~(1 << scaler_user);
208 scaler_state->scalers[*scaler_id].in_use = false;
209
210 drm_dbg_kms(display->drm,
211 "[CRTC:%d:%s] scaler_user index %u.%u: "
212 "Staged freeing scaler id %d scaler_users = 0x%x\n",
213 crtc->base.base.id, crtc->base.name,
214 crtc->pipe, scaler_user, *scaler_id,
215 scaler_state->scaler_users);
216 *scaler_id = -1;
217 }
218 return 0;
219 }
220
221 skl_scaler_min_src_size(format, modifier, min_w: &min_src_w, min_h: &min_src_h);
222 skl_scaler_max_src_size(display, max_w: &max_src_w, max_h: &max_src_h);
223
224 skl_scaler_min_dst_size(min_w: &min_dst_w, min_h: &min_dst_h);
225 skl_scaler_max_dst_size(crtc, max_w: &max_dst_w, max_h: &max_dst_h);
226
227 /* range checks */
228 if (src_w < min_src_w || src_h < min_src_h ||
229 dst_w < min_dst_w || dst_h < min_dst_h ||
230 src_w > max_src_w || src_h > max_src_h ||
231 dst_w > max_dst_w || dst_h > max_dst_h) {
232 drm_dbg_kms(display->drm,
233 "[CRTC:%d:%s] scaler_user index %u.%u: src %ux%u dst %ux%u "
234 "size is out of scaler range\n",
235 crtc->base.base.id, crtc->base.name,
236 crtc->pipe, scaler_user, src_w, src_h,
237 dst_w, dst_h);
238 return -EINVAL;
239 }
240
241 /*
242 * The pipe scaler does not use all the bits of PIPESRC, at least
243 * on the earlier platforms. So even when we're scaling a plane
244 * the *pipe* source size must not be too large. For simplicity
245 * we assume the limits match the scaler destination size limits.
246 * Might not be 100% accurate on all platforms, but good enough for
247 * now.
248 */
249 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) {
250 drm_dbg_kms(display->drm,
251 "[CRTC:%d:%s] scaler_user index %u.%u: pipe src size %ux%u "
252 "is out of scaler range\n",
253 crtc->base.base.id, crtc->base.name,
254 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
255 return -EINVAL;
256 }
257
258 /* mark this plane as a scaler user in crtc_state */
259 scaler_state->scaler_users |= (1 << scaler_user);
260 drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: "
261 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
262 crtc->base.base.id, crtc->base.name,
263 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
264 scaler_state->scaler_users);
265
266 return 0;
267}
268
269int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
270{
271 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
272 int width, height;
273
274 if (crtc_state->pch_pfit.enabled) {
275 width = drm_rect_width(r: &crtc_state->pch_pfit.dst);
276 height = drm_rect_height(r: &crtc_state->pch_pfit.dst);
277 } else {
278 width = pipe_mode->crtc_hdisplay;
279 height = pipe_mode->crtc_vdisplay;
280 }
281 return skl_update_scaler(crtc_state, force_detach: !crtc_state->hw.active,
282 SKL_CRTC_INDEX,
283 scaler_id: &crtc_state->scaler_state.scaler_id,
284 src_w: drm_rect_width(r: &crtc_state->pipe_src),
285 src_h: drm_rect_height(r: &crtc_state->pipe_src),
286 dst_w: width, dst_h: height, NULL, modifier: 0,
287 need_scaler: crtc_state->pch_pfit.enabled ||
288 intel_casf_needs_scaler(crtc_state));
289}
290
291/**
292 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
293 * @crtc_state: crtc's scaler state
294 * @plane_state: atomic plane state to update
295 *
296 * Return
297 * 0 - scaler_usage updated successfully
298 * error - requested scaling cannot be supported or other error condition
299 */
300int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
301 struct intel_plane_state *plane_state)
302{
303 struct intel_display *display = to_intel_display(plane_state);
304 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
305 struct drm_framebuffer *fb = plane_state->hw.fb;
306 bool force_detach = !fb || !plane_state->uapi.visible;
307 bool need_scaler = false;
308
309 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
310 if (!icl_is_hdr_plane(display, plane_id: plane->id) &&
311 fb && intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier))
312 need_scaler = true;
313
314 return skl_update_scaler(crtc_state, force_detach,
315 scaler_user: drm_plane_index(plane: &plane->base),
316 scaler_id: &plane_state->scaler_id,
317 src_w: drm_rect_width(r: &plane_state->uapi.src) >> 16,
318 src_h: drm_rect_height(r: &plane_state->uapi.src) >> 16,
319 dst_w: drm_rect_width(r: &plane_state->uapi.dst),
320 dst_h: drm_rect_height(r: &plane_state->uapi.dst),
321 format: fb ? fb->format : NULL,
322 modifier: fb ? fb->modifier : 0,
323 need_scaler);
324}
325
326static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state,
327 struct intel_crtc *crtc,
328 struct intel_plane_state *plane_state,
329 bool casf_scaler)
330{
331 int i;
332
333 for (i = 0; i < crtc->num_scalers; i++) {
334 if (scaler_state->scalers[i].in_use)
335 continue;
336
337 /* CASF needs second scaler */
338 if (!plane_state && casf_scaler && i != 1)
339 continue;
340
341 scaler_state->scalers[i].in_use = true;
342
343 return i;
344 }
345
346 return -1;
347}
348
349static void
350calculate_max_scale(struct intel_crtc *crtc,
351 bool is_yuv_semiplanar,
352 int scaler_id,
353 int *max_hscale, int *max_vscale)
354{
355 struct intel_display *display = to_intel_display(crtc);
356
357 /*
358 * FIXME: When two scalers are needed, but only one of
359 * them needs to downscale, we should make sure that
360 * the one that needs downscaling support is assigned
361 * as the first scaler, so we don't reject downscaling
362 * unnecessarily.
363 */
364
365 if (DISPLAY_VER(display) >= 14) {
366 /*
367 * On versions 14 and up, only the first
368 * scaler supports a vertical scaling factor
369 * of more than 1.0, while a horizontal
370 * scaling factor of 3.0 is supported.
371 */
372 *max_hscale = 0x30000 - 1;
373
374 if (scaler_id == 0)
375 *max_vscale = 0x30000 - 1;
376 else
377 *max_vscale = 0x10000;
378 } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) {
379 *max_hscale = 0x30000 - 1;
380 *max_vscale = 0x30000 - 1;
381 } else {
382 *max_hscale = 0x20000 - 1;
383 *max_vscale = 0x20000 - 1;
384 }
385}
386
387static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
388 int num_scalers_need, struct intel_crtc *crtc,
389 const char *name, int idx,
390 struct intel_plane_state *plane_state,
391 int *scaler_id, bool casf_scaler)
392{
393 struct intel_display *display = to_intel_display(crtc);
394 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
395 u32 mode;
396 int hscale = 0;
397 int vscale = 0;
398
399 if (*scaler_id < 0)
400 *scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler);
401
402 if (drm_WARN(display->drm, *scaler_id < 0,
403 "Cannot find scaler for %s:%d\n", name, idx))
404 return -EINVAL;
405
406 /* set scaler mode */
407 if (plane_state && plane_state->hw.fb &&
408 plane_state->hw.fb->format->is_yuv &&
409 plane_state->hw.fb->format->num_planes > 1) {
410 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
411
412 if (DISPLAY_VER(display) == 9) {
413 mode = SKL_PS_SCALER_MODE_NV12;
414 } else if (icl_is_hdr_plane(display, plane_id: plane->id)) {
415 /*
416 * On gen11+'s HDR planes we only use the scaler for
417 * scaling. They have a dedicated chroma upsampler, so
418 * we don't need the scaler to upsample the UV plane.
419 */
420 mode = PS_SCALER_MODE_NORMAL;
421 } else {
422 struct intel_plane *linked =
423 plane_state->planar_linked_plane;
424
425 mode = PS_SCALER_MODE_PLANAR;
426
427 if (linked)
428 mode |= PS_BINDING_Y_PLANE(linked->id);
429 }
430 } else if (DISPLAY_VER(display) >= 10) {
431 mode = PS_SCALER_MODE_NORMAL;
432 } else if (num_scalers_need == 1 && crtc->num_scalers > 1) {
433 /*
434 * when only 1 scaler is in use on a pipe with 2 scalers
435 * scaler 0 operates in high quality (HQ) mode.
436 * In this case use scaler 0 to take advantage of HQ mode
437 */
438 scaler_state->scalers[*scaler_id].in_use = false;
439 *scaler_id = 0;
440 scaler_state->scalers[0].in_use = true;
441 mode = SKL_PS_SCALER_MODE_HQ;
442 } else {
443 mode = SKL_PS_SCALER_MODE_DYN;
444 }
445
446 if (plane_state && plane_state->hw.fb) {
447 const struct drm_framebuffer *fb = plane_state->hw.fb;
448 const struct drm_rect *src = &plane_state->uapi.src;
449 const struct drm_rect *dst = &plane_state->uapi.dst;
450 int max_hscale, max_vscale;
451
452 calculate_max_scale(crtc,
453 is_yuv_semiplanar: intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier),
454 scaler_id: *scaler_id, max_hscale: &max_hscale, max_vscale: &max_vscale);
455
456 /*
457 * FIXME: We should change the if-else block above to
458 * support HQ vs dynamic scaler properly.
459 */
460
461 /* Check if required scaling is within limits */
462 hscale = drm_rect_calc_hscale(src, dst, min_hscale: 1, max_hscale);
463 vscale = drm_rect_calc_vscale(src, dst, min_vscale: 1, max_vscale);
464
465 if (hscale < 0 || vscale < 0) {
466 drm_dbg_kms(display->drm,
467 "[CRTC:%d:%s] scaler %d doesn't support required plane scaling\n",
468 crtc->base.base.id, crtc->base.name, *scaler_id);
469 drm_rect_debug_print(prefix: "src: ", r: src, fixed_point: true);
470 drm_rect_debug_print(prefix: "dst: ", r: dst, fixed_point: false);
471
472 return -EINVAL;
473 }
474 }
475
476 if (crtc_state->pch_pfit.enabled) {
477 struct drm_rect src;
478 int max_hscale, max_vscale;
479
480 drm_rect_init(r: &src, x: 0, y: 0,
481 width: drm_rect_width(r: &crtc_state->pipe_src) << 16,
482 height: drm_rect_height(r: &crtc_state->pipe_src) << 16);
483
484 calculate_max_scale(crtc, is_yuv_semiplanar: 0, scaler_id: *scaler_id,
485 max_hscale: &max_hscale, max_vscale: &max_vscale);
486
487 /*
488 * When configured for Pipe YUV 420 encoding for port output,
489 * limit downscaling to less than 1.5 (source/destination) in
490 * the horizontal direction and 1.0 in the vertical direction.
491 */
492 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
493 max_hscale = 0x18000 - 1;
494 max_vscale = 0x10000;
495 }
496
497 hscale = drm_rect_calc_hscale(src: &src, dst: &crtc_state->pch_pfit.dst,
498 min_hscale: 0, max_hscale);
499 vscale = drm_rect_calc_vscale(src: &src, dst: &crtc_state->pch_pfit.dst,
500 min_vscale: 0, max_vscale);
501
502 if (hscale < 0 || vscale < 0) {
503 drm_dbg_kms(display->drm,
504 "Scaler %d doesn't support required pipe scaling\n",
505 *scaler_id);
506 drm_rect_debug_print(prefix: "src: ", r: &src, fixed_point: true);
507 drm_rect_debug_print(prefix: "dst: ", r: &crtc_state->pch_pfit.dst, fixed_point: false);
508
509 return -EINVAL;
510 }
511 }
512
513 scaler_state->scalers[*scaler_id].hscale = hscale;
514 scaler_state->scalers[*scaler_id].vscale = vscale;
515
516 drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n",
517 crtc->base.base.id, crtc->base.name,
518 crtc->pipe, *scaler_id, name, idx);
519 scaler_state->scalers[*scaler_id].mode = mode;
520
521 return 0;
522}
523
524static int setup_crtc_scaler(struct intel_atomic_state *state,
525 struct intel_crtc *crtc)
526{
527 struct intel_crtc_state *crtc_state =
528 intel_atomic_get_new_crtc_state(state, crtc);
529 struct intel_crtc_scaler_state *scaler_state =
530 &crtc_state->scaler_state;
531
532 if (intel_casf_needs_scaler(crtc_state) && crtc_state->pch_pfit.enabled)
533 return -EINVAL;
534
535 return intel_atomic_setup_scaler(crtc_state,
536 hweight32(scaler_state->scaler_users),
537 crtc, name: "CRTC", idx: crtc->base.base.id,
538 NULL, scaler_id: &scaler_state->scaler_id,
539 casf_scaler: intel_casf_needs_scaler(crtc_state));
540}
541
542static int setup_plane_scaler(struct intel_atomic_state *state,
543 struct intel_crtc *crtc,
544 struct intel_plane *plane)
545{
546 struct intel_display *display = to_intel_display(state);
547 struct intel_crtc_state *crtc_state =
548 intel_atomic_get_new_crtc_state(state, crtc);
549 struct intel_crtc_scaler_state *scaler_state =
550 &crtc_state->scaler_state;
551 struct intel_plane_state *plane_state;
552
553 /* plane on different crtc cannot be a scaler user of this crtc */
554 if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))
555 return 0;
556
557 plane_state = intel_atomic_get_new_plane_state(state, plane);
558
559 /*
560 * GLK+ scalers don't have a HQ mode so it
561 * isn't necessary to change between HQ and dyn mode
562 * on those platforms.
563 */
564 if (!plane_state && DISPLAY_VER(display) >= 10)
565 return 0;
566
567 plane_state = intel_atomic_get_plane_state(state, plane);
568 if (IS_ERR(ptr: plane_state))
569 return PTR_ERR(ptr: plane_state);
570
571 return intel_atomic_setup_scaler(crtc_state,
572 hweight32(scaler_state->scaler_users),
573 crtc, name: "PLANE", idx: plane->base.base.id,
574 plane_state, scaler_id: &plane_state->scaler_id,
575 casf_scaler: false);
576}
577
578/**
579 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
580 * @state: atomic state
581 * @crtc: crtc
582 *
583 * This function sets up scalers based on staged scaling requests for
584 * a @crtc and its planes. It is called from crtc level check path. If request
585 * is a supportable request, it attaches scalers to requested planes and crtc.
586 *
587 * This function takes into account the current scaler(s) in use by any planes
588 * not being part of this atomic state
589 *
590 * Returns:
591 * 0 - scalers were setup successfully
592 * error code - otherwise
593 */
594int intel_atomic_setup_scalers(struct intel_atomic_state *state,
595 struct intel_crtc *crtc)
596{
597 struct intel_display *display = to_intel_display(crtc);
598 struct intel_crtc_state *crtc_state =
599 intel_atomic_get_new_crtc_state(state, crtc);
600 struct intel_crtc_scaler_state *scaler_state =
601 &crtc_state->scaler_state;
602 int num_scalers_need;
603 int i;
604
605 num_scalers_need = hweight32(scaler_state->scaler_users);
606
607 /*
608 * High level flow:
609 * - staged scaler requests are already in scaler_state->scaler_users
610 * - check whether staged scaling requests can be supported
611 * - add planes using scalers that aren't in current transaction
612 * - assign scalers to requested users
613 * - as part of plane commit, scalers will be committed
614 * (i.e., either attached or detached) to respective planes in hw
615 * - as part of crtc_commit, scaler will be either attached or detached
616 * to crtc in hw
617 */
618
619 /* fail if required scalers > available scalers */
620 if (num_scalers_need > crtc->num_scalers) {
621 drm_dbg_kms(display->drm,
622 "[CRTC:%d:%s] too many scaling requests %d > %d\n",
623 crtc->base.base.id, crtc->base.name,
624 num_scalers_need, crtc->num_scalers);
625 return -EINVAL;
626 }
627
628 /* walkthrough scaler_users bits and start assigning scalers */
629 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
630 int ret;
631
632 /* skip if scaler not required */
633 if (!(scaler_state->scaler_users & (1 << i)))
634 continue;
635
636 if (i == SKL_CRTC_INDEX) {
637 ret = setup_crtc_scaler(state, crtc);
638 if (ret)
639 return ret;
640 } else {
641 struct intel_plane *plane =
642 to_intel_plane(drm_plane_from_index(display->drm, i));
643
644 ret = setup_plane_scaler(state, crtc, plane);
645 if (ret)
646 return ret;
647 }
648 }
649
650 return 0;
651}
652
653static int glk_coef_tap(int i)
654{
655 return i % 7;
656}
657
658static u16 glk_nearest_filter_coef(int t)
659{
660 return t == 3 ? 0x0800 : 0x3000;
661}
662
663/*
664 * Theory behind setting nearest-neighbor integer scaling:
665 *
666 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
667 * The letter represents the filter tap (D is the center tap) and the number
668 * represents the coefficient set for a phase (0-16).
669 *
670 * +------------+--------------------------+--------------------------+
671 * |Index value | Data value coefficient 1 | Data value coefficient 2 |
672 * +------------+--------------------------+--------------------------+
673 * | 00h | B0 | A0 |
674 * +------------+--------------------------+--------------------------+
675 * | 01h | D0 | C0 |
676 * +------------+--------------------------+--------------------------+
677 * | 02h | F0 | E0 |
678 * +------------+--------------------------+--------------------------+
679 * | 03h | A1 | G0 |
680 * +------------+--------------------------+--------------------------+
681 * | 04h | C1 | B1 |
682 * +------------+--------------------------+--------------------------+
683 * | ... | ... | ... |
684 * +------------+--------------------------+--------------------------+
685 * | 38h | B16 | A16 |
686 * +------------+--------------------------+--------------------------+
687 * | 39h | D16 | C16 |
688 * +------------+--------------------------+--------------------------+
689 * | 3Ah | F16 | C16 |
690 * +------------+--------------------------+--------------------------+
691 * | 3Bh | Reserved | G16 |
692 * +------------+--------------------------+--------------------------+
693 *
694 * To enable nearest-neighbor scaling: program scaler coefficients with
695 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
696 * SCALER_COEFFICIENT_FORMAT
697 *
698 */
699
700static void glk_program_nearest_filter_coefs(struct intel_display *display,
701 struct intel_dsb *dsb,
702 enum pipe pipe, int id, int set)
703{
704 int i;
705
706 intel_de_write_dsb(display, dsb,
707 GLK_PS_COEF_INDEX_SET(pipe, id, set),
708 PS_COEF_INDEX_AUTO_INC);
709
710 for (i = 0; i < 17 * 7; i += 2) {
711 u32 tmp;
712 int t;
713
714 t = glk_coef_tap(i);
715 tmp = glk_nearest_filter_coef(t);
716
717 t = glk_coef_tap(i: i + 1);
718 tmp |= glk_nearest_filter_coef(t) << 16;
719
720 intel_de_write_dsb(display, dsb,
721 GLK_PS_COEF_DATA_SET(pipe, id, set), val: tmp);
722 }
723
724 intel_de_write_dsb(display, dsb,
725 GLK_PS_COEF_INDEX_SET(pipe, id, set), val: 0);
726}
727
728static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter)
729{
730 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR)
731 return (PS_FILTER_PROGRAMMED |
732 PS_Y_VERT_FILTER_SELECT(0) |
733 PS_Y_HORZ_FILTER_SELECT(0) |
734 PS_UV_VERT_FILTER_SELECT(0) |
735 PS_UV_HORZ_FILTER_SELECT(0));
736
737 return PS_FILTER_MEDIUM;
738}
739
740static void skl_scaler_setup_filter(struct intel_display *display,
741 struct intel_dsb *dsb, enum pipe pipe,
742 int id, int set, enum drm_scaling_filter filter)
743{
744 switch (filter) {
745 case DRM_SCALING_FILTER_DEFAULT:
746 break;
747 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
748 glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);
749 break;
750 default:
751 MISSING_CASE(filter);
752 }
753}
754
755#define CASF_SCALER_FILTER_SELECT \
756 (PS_FILTER_PROGRAMMED | \
757 PS_Y_VERT_FILTER_SELECT(0) | \
758 PS_Y_HORZ_FILTER_SELECT(0) | \
759 PS_UV_VERT_FILTER_SELECT(0) | \
760 PS_UV_HORZ_FILTER_SELECT(0))
761
762void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state)
763{
764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
765 struct intel_display *display = to_intel_display(crtc);
766 struct drm_display_mode *adjusted_mode =
767 &crtc_state->hw.adjusted_mode;
768 struct intel_crtc_scaler_state *scaler_state =
769 &crtc_state->scaler_state;
770 struct drm_rect src, dest;
771 int id, width, height;
772 int x = 0, y = 0;
773 enum pipe pipe = crtc->pipe;
774 u32 ps_ctrl;
775
776 width = adjusted_mode->crtc_hdisplay;
777 height = adjusted_mode->crtc_vdisplay;
778
779 drm_rect_init(r: &dest, x, y, width, height);
780
781 width = drm_rect_width(r: &dest);
782 height = drm_rect_height(r: &dest);
783 id = scaler_state->scaler_id;
784
785 drm_rect_init(r: &src, x: 0, y: 0,
786 width: drm_rect_width(r: &crtc_state->pipe_src) << 16,
787 height: drm_rect_height(r: &crtc_state->pipe_src) << 16);
788
789 trace_intel_pipe_scaler_update_arm(crtc, scaler_id: id, x, y, w: width, h: height);
790
791 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
792 CASF_SCALER_FILTER_SELECT;
793
794 intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), val: ps_ctrl);
795 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),
796 PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
797 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),
798 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
799}
800
801void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
802{
803 struct intel_display *display = to_intel_display(crtc_state);
804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
805 const struct intel_crtc_scaler_state *scaler_state =
806 &crtc_state->scaler_state;
807 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
808 u16 uv_rgb_hphase, uv_rgb_vphase;
809 enum pipe pipe = crtc->pipe;
810 int width = drm_rect_width(r: dst);
811 int height = drm_rect_height(r: dst);
812 int x = dst->x1;
813 int y = dst->y1;
814 int hscale, vscale;
815 struct drm_rect src;
816 int id;
817 u32 ps_ctrl;
818
819 if (!crtc_state->pch_pfit.enabled)
820 return;
821
822 if (drm_WARN_ON(display->drm,
823 crtc_state->scaler_state.scaler_id < 0))
824 return;
825
826 if (intel_display_wa(display, 14011503117))
827 adl_scaler_ecc_mask(crtc_state);
828
829 drm_rect_init(r: &src, x: 0, y: 0,
830 width: drm_rect_width(r: &crtc_state->pipe_src) << 16,
831 height: drm_rect_height(r: &crtc_state->pipe_src) << 16);
832
833 hscale = drm_rect_calc_hscale(src: &src, dst, min_hscale: 0, INT_MAX);
834 vscale = drm_rect_calc_vscale(src: &src, dst, min_vscale: 0, INT_MAX);
835
836 uv_rgb_hphase = skl_scaler_calc_phase(sub: 1, scale: hscale, chroma_cosited: false);
837 uv_rgb_vphase = skl_scaler_calc_phase(sub: 1, scale: vscale, chroma_cosited: false);
838
839 id = scaler_state->scaler_id;
840
841 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
842 skl_scaler_get_filter_select(filter: crtc_state->hw.scaling_filter);
843
844 trace_intel_pipe_scaler_update_arm(crtc, scaler_id: id, x, y, w: width, h: height);
845
846 skl_scaler_setup_filter(display, NULL, pipe, id, set: 0,
847 filter: crtc_state->hw.scaling_filter);
848
849 intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), val: ps_ctrl);
850
851 intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),
852 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
853 intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),
854 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
855 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),
856 PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
857 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),
858 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
859}
860
861void
862skl_program_plane_scaler(struct intel_dsb *dsb,
863 struct intel_plane *plane,
864 const struct intel_crtc_state *crtc_state,
865 const struct intel_plane_state *plane_state)
866{
867 struct intel_display *display = to_intel_display(plane);
868 const struct drm_framebuffer *fb = plane_state->hw.fb;
869 enum pipe pipe = plane->pipe;
870 int scaler_id = plane_state->scaler_id;
871 const struct intel_scaler *scaler =
872 &crtc_state->scaler_state.scalers[scaler_id];
873 int crtc_x = plane_state->uapi.dst.x1;
874 int crtc_y = plane_state->uapi.dst.y1;
875 u32 crtc_w = drm_rect_width(r: &plane_state->uapi.dst);
876 u32 crtc_h = drm_rect_height(r: &plane_state->uapi.dst);
877 u16 y_hphase, uv_rgb_hphase;
878 u16 y_vphase, uv_rgb_vphase;
879 int hscale, vscale;
880 u32 ps_ctrl;
881
882 hscale = drm_rect_calc_hscale(src: &plane_state->uapi.src,
883 dst: &plane_state->uapi.dst,
884 min_hscale: 0, INT_MAX);
885 vscale = drm_rect_calc_vscale(src: &plane_state->uapi.src,
886 dst: &plane_state->uapi.dst,
887 min_vscale: 0, INT_MAX);
888
889 /* TODO: handle sub-pixel coordinates */
890 if (intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier) &&
891 !icl_is_hdr_plane(display, plane_id: plane->id)) {
892 y_hphase = skl_scaler_calc_phase(sub: 1, scale: hscale, chroma_cosited: false);
893 y_vphase = skl_scaler_calc_phase(sub: 1, scale: vscale, chroma_cosited: false);
894
895 /* MPEG2 chroma siting convention */
896 uv_rgb_hphase = skl_scaler_calc_phase(sub: 2, scale: hscale, chroma_cosited: true);
897 uv_rgb_vphase = skl_scaler_calc_phase(sub: 2, scale: vscale, chroma_cosited: false);
898 } else {
899 /* not used */
900 y_hphase = 0;
901 y_vphase = 0;
902
903 uv_rgb_hphase = skl_scaler_calc_phase(sub: 1, scale: hscale, chroma_cosited: false);
904 uv_rgb_vphase = skl_scaler_calc_phase(sub: 1, scale: vscale, chroma_cosited: false);
905 }
906
907 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
908 skl_scaler_get_filter_select(filter: plane_state->hw.scaling_filter);
909
910 trace_intel_plane_scaler_update_arm(plane, scaler_id,
911 x: crtc_x, y: crtc_y, w: crtc_w, h: crtc_h);
912
913 skl_scaler_setup_filter(display, dsb, pipe, id: scaler_id, set: 0,
914 filter: plane_state->hw.scaling_filter);
915
916 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),
917 val: ps_ctrl);
918 intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),
919 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
920 intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),
921 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
922 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),
923 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
924 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),
925 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
926}
927
928static void skl_detach_scaler(struct intel_dsb *dsb,
929 struct intel_crtc *crtc, int id)
930{
931 struct intel_display *display = to_intel_display(crtc);
932
933 trace_intel_scaler_disable_arm(crtc, scaler_id: id);
934
935 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), val: 0);
936 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), val: 0);
937 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), val: 0);
938}
939
940/*
941 * This function detaches (aka. unbinds) unused scalers in hardware
942 */
943void skl_detach_scalers(struct intel_dsb *dsb,
944 const struct intel_crtc_state *crtc_state)
945{
946 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
947 const struct intel_crtc_scaler_state *scaler_state =
948 &crtc_state->scaler_state;
949 int i;
950
951 /* loop through and disable scalers that aren't in use */
952 for (i = 0; i < crtc->num_scalers; i++) {
953 if (!scaler_state->scalers[i].in_use)
954 skl_detach_scaler(dsb, crtc, id: i);
955 }
956}
957
958void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
959{
960 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
961 int i;
962
963 for (i = 0; i < crtc->num_scalers; i++)
964 skl_detach_scaler(NULL, crtc, id: i);
965}
966
967void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
968{
969 struct intel_display *display = to_intel_display(crtc_state);
970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
971 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
972 int id = -1;
973 int i;
974
975 /* find scaler attached to this pipe */
976 for (i = 0; i < crtc->num_scalers; i++) {
977 u32 ctl, pos, size;
978
979 ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));
980 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
981 continue;
982
983 id = i;
984
985 /* Read CASF regs for second scaler */
986 if (HAS_CASF(display) && id == 1)
987 intel_casf_sharpness_get_config(crtc_state);
988
989 if (!crtc_state->hw.casf_params.casf_enable)
990 crtc_state->pch_pfit.enabled = true;
991
992 pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));
993 size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));
994
995 if (!crtc_state->hw.casf_params.casf_enable)
996 drm_rect_init(r: &crtc_state->pch_pfit.dst,
997 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
998 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
999 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
1000 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
1001
1002 scaler_state->scalers[i].in_use = true;
1003 break;
1004 }
1005
1006 scaler_state->scaler_id = id;
1007 if (id >= 0)
1008 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
1009 else
1010 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
1011}
1012
1013void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)
1014{
1015 struct intel_display *display = to_intel_display(crtc_state);
1016
1017 if (!crtc_state->pch_pfit.enabled)
1018 return;
1019
1020 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, val: ~0);
1021}
1022
1023void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
1024{
1025 struct intel_display *display = to_intel_display(crtc_state);
1026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1027 const struct intel_crtc_scaler_state *scaler_state =
1028 &crtc_state->scaler_state;
1029
1030 if (scaler_state->scaler_id < 0)
1031 return;
1032
1033 intel_de_write_fw(display,
1034 SKL_PS_ECC_STAT(crtc->pipe, scaler_state->scaler_id),
1035 val: 1);
1036 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, val: 0);
1037}
1038
1039unsigned int skl_scaler_1st_prefill_adjustment(const struct intel_crtc_state *crtc_state)
1040{
1041 /*
1042 * FIXME don't have scalers assigned yet
1043 * so can't look up the scale factors
1044 */
1045 return 0x10000;
1046}
1047
1048unsigned int skl_scaler_2nd_prefill_adjustment(const struct intel_crtc_state *crtc_state)
1049{
1050 /*
1051 * FIXME don't have scalers assigned yet
1052 * so can't look up the scale factors
1053 */
1054 return 0x10000;
1055}
1056
1057unsigned int skl_scaler_1st_prefill_lines(const struct intel_crtc_state *crtc_state)
1058{
1059 const struct intel_crtc_scaler_state *scaler_state =
1060 &crtc_state->scaler_state;
1061 int num_scalers = hweight32(scaler_state->scaler_users);
1062
1063 if (num_scalers > 0)
1064 return 4 << 16;
1065
1066 return 0;
1067}
1068
1069unsigned int skl_scaler_2nd_prefill_lines(const struct intel_crtc_state *crtc_state)
1070{
1071 const struct intel_crtc_scaler_state *scaler_state =
1072 &crtc_state->scaler_state;
1073 int num_scalers = hweight32(scaler_state->scaler_users);
1074
1075 if (num_scalers > 1 && crtc_state->pch_pfit.enabled)
1076 return 4 << 16;
1077
1078 return 0;
1079}
1080
1081static unsigned int _skl_scaler_max_scale(const struct intel_crtc_state *crtc_state,
1082 unsigned int max_scale)
1083{
1084 struct intel_display *display = to_intel_display(crtc_state);
1085
1086 /*
1087 * Downscaling requires increasing cdclk, so max scale
1088 * factor is limited to the max_dotclock/dotclock ratio.
1089 *
1090 * FIXME find out the max downscale factors properly
1091 */
1092 return min(max_scale, DIV_ROUND_UP_ULL((u64)display->cdclk.max_dotclk_freq << 16,
1093 crtc_state->hw.pipe_mode.crtc_clock));
1094}
1095
1096unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)
1097{
1098 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1099 unsigned int max_scale;
1100
1101 if (crtc->num_scalers < 1)
1102 return 0x10000;
1103
1104 /* FIXME find out the max downscale factors properly */
1105 max_scale = 9 << 16;
1106 if (crtc->num_scalers > 1)
1107 max_scale *= 9;
1108
1109 return _skl_scaler_max_scale(crtc_state, max_scale);
1110}
1111
1112unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)
1113{
1114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1115 unsigned int max_scale;
1116
1117 if (crtc->num_scalers < 1)
1118 return 0x10000;
1119
1120 /* FIXME find out the max downscale factors properly */
1121 max_scale = 3 << 16;
1122
1123 return _skl_scaler_max_scale(crtc_state, max_scale);
1124}
1125
1126unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
1127{
1128 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1129 unsigned int max_scale;
1130
1131 if (crtc->num_scalers < 1)
1132 return 0x10000;
1133
1134 /* FIXME find out the max downscale factors properly */
1135 max_scale = 9 << 16;
1136
1137 return _skl_scaler_max_scale(crtc_state, max_scale);
1138}
1139
1140unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
1141{
1142 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1143
1144 if (crtc->num_scalers > 0)
1145 return skl_scaler_max_scale(crtc_state);
1146 else
1147 return 0x10000;
1148}
1149
1150unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
1151{
1152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1153
1154 if (crtc->num_scalers > 1)
1155 return skl_scaler_max_scale(crtc_state);
1156 else
1157 return 0x10000;
1158}
1159
1160unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
1161{
1162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1163
1164 if (crtc->num_scalers > 0)
1165 return 4 << 16;
1166 else
1167 return 0;
1168}
1169
1170unsigned int skl_scaler_2nd_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
1171{
1172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1173
1174 if (crtc->num_scalers > 1)
1175 return 4 << 16;
1176 else
1177 return 0;
1178}
1179

source code of linux/drivers/gpu/drm/i915/display/skl_scaler.c