1	/*
2	* Copyright © 2014 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.
22	*/
23
24	/**
25	* DOC: atomic plane helpers
26	*
27	* The functions here are used by the atomic plane helper functions to
28	* implement legacy plane updates (i.e., drm_plane->update_plane() and
29	* drm_plane->disable_plane()). This allows plane updates to use the
30	* atomic state infrastructure and perform plane updates as separate
31	* prepare/check/commit/cleanup steps.
32	*/
33
34	#include <linux/dma-fence-chain.h>
35	#include <linux/dma-resv.h>
36	#include <linux/iosys-map.h>
37
38	#include <drm/drm_atomic_helper.h>
39	#include <drm/drm_blend.h>
40	#include <drm/drm_cache.h>
41	#include <drm/drm_damage_helper.h>
42	#include <drm/drm_fourcc.h>
43	#include <drm/drm_gem.h>
44	#include <drm/drm_gem_atomic_helper.h>
45	#include <drm/drm_panic.h>
46	#include <drm/drm_print.h>
47
48	#include "gem/i915_gem_object.h"
49	#include "i9xx_plane_regs.h"
50	#include "intel_cdclk.h"
51	#include "intel_cursor.h"
52	#include "intel_colorop.h"
53	#include "intel_display_rps.h"
54	#include "intel_display_trace.h"
55	#include "intel_display_types.h"
56	#include "intel_fb.h"
57	#include "intel_fb_pin.h"
58	#include "intel_fbdev.h"
59	#include "intel_panic.h"
60	#include "intel_plane.h"
61	#include "intel_psr.h"
62	#include "skl_scaler.h"
63	#include "skl_universal_plane.h"
64	#include "skl_watermark.h"
65
66	static void intel_plane_state_reset(struct intel_plane_state *plane_state,
67	struct intel_plane *plane)
68	{
69	memset(plane_state, 0, sizeof(*plane_state));
70
71	__drm_atomic_helper_plane_state_reset(state: &plane_state->uapi, plane: &plane->base);
72
73	plane_state->scaler_id = -1;
74	}
75
76	struct intel_plane *intel_plane_alloc(void)
77	{
78	struct intel_plane_state *plane_state;
79	struct intel_plane *plane;
80
81	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
82	if (!plane)
83	return ERR_PTR(error: -ENOMEM);
84
85	plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
86	if (!plane_state) {
87	kfree(objp: plane);
88	return ERR_PTR(error: -ENOMEM);
89	}
90
91	intel_plane_state_reset(plane_state, plane);
92
93	plane->base.state = &plane_state->uapi;
94
95	return plane;
96	}
97
98	void intel_plane_free(struct intel_plane *plane)
99	{
100	intel_plane_destroy_state(plane: &plane->base, state: plane->base.state);
101	kfree(objp: plane);
102	}
103
104	/**
105	* intel_plane_destroy - destroy a plane
106	* @plane: plane to destroy
107	*
108	* Common destruction function for all types of planes (primary, cursor,
109	* sprite).
110	*/
111	void intel_plane_destroy(struct drm_plane *plane)
112	{
113	drm_plane_cleanup(plane);
114	kfree(to_intel_plane(plane));
115	}
116
117	/**
118	* intel_plane_duplicate_state - duplicate plane state
119	* @plane: drm plane
120	*
121	* Allocates and returns a copy of the plane state (both common and
122	* Intel-specific) for the specified plane.
123	*
124	* Returns: The newly allocated plane state, or NULL on failure.
125	*/
126	struct drm_plane_state *
127	intel_plane_duplicate_state(struct drm_plane *plane)
128	{
129	struct intel_plane_state *intel_state;
130
131	intel_state = to_intel_plane_state(plane->state);
132	intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
133
134	if (!intel_state)
135	return NULL;
136
137	__drm_atomic_helper_plane_duplicate_state(plane, state: &intel_state->uapi);
138
139	intel_state->ggtt_vma = NULL;
140	intel_state->dpt_vma = NULL;
141	intel_state->flags = 0;
142	intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
143
144	/* add reference to fb */
145	if (intel_state->hw.fb)
146	drm_framebuffer_get(fb: intel_state->hw.fb);
147
148	return &intel_state->uapi;
149	}
150
151	/**
152	* intel_plane_destroy_state - destroy plane state
153	* @plane: drm plane
154	* @state: state object to destroy
155	*
156	* Destroys the plane state (both common and Intel-specific) for the
157	* specified plane.
158	*/
159	void
160	intel_plane_destroy_state(struct drm_plane *plane,
161	struct drm_plane_state *state)
162	{
163	struct intel_plane_state *plane_state = to_intel_plane_state(state);
164
165	drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
166	drm_WARN_ON(plane->dev, plane_state->dpt_vma);
167
168	__drm_atomic_helper_plane_destroy_state(state: &plane_state->uapi);
169	if (plane_state->hw.fb)
170	drm_framebuffer_put(fb: plane_state->hw.fb);
171	kfree(objp: plane_state);
172	}
173
174	bool intel_plane_needs_physical(struct intel_plane *plane)
175	{
176	struct intel_display *display = to_intel_display(plane);
177
178	return plane->id == PLANE_CURSOR &&
179	DISPLAY_INFO(display)->cursor_needs_physical;
180	}
181
182	bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
183	u64 modifier)
184	{
185	if (intel_format_info_is_yuv_semiplanar(info: drm_format_info(format), modifier) ||
186	format == DRM_FORMAT_C8)
187	return false;
188
189	return plane->can_async_flip && plane->can_async_flip(modifier);
190	}
191
192	bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
193	u32 format,
194	u64 modifier)
195	{
196	if (!plane->funcs->format_mod_supported(plane, format, modifier))
197	return false;
198
199	return intel_plane_can_async_flip(to_intel_plane(plane),
200	format, modifier);
201	}
202
203	unsigned int intel_adjusted_rate(const struct drm_rect *src,
204	const struct drm_rect *dst,
205	unsigned int rate)
206	{
207	unsigned int src_w, src_h, dst_w, dst_h;
208
209	src_w = drm_rect_width(r: src) >> 16;
210	src_h = drm_rect_height(r: src) >> 16;
211	dst_w = drm_rect_width(r: dst);
212	dst_h = drm_rect_height(r: dst);
213
214	/* Downscaling limits the maximum pixel rate */
215	dst_w = min(src_w, dst_w);
216	dst_h = min(src_h, dst_h);
217
218	return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
219	dst_w * dst_h);
220	}
221
222	unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
223	const struct intel_plane_state *plane_state)
224	{
225	/*
226	* Note we don't check for plane visibility here as
227	* we want to use this when calculating the cursor
228	* watermarks even if the cursor is fully offscreen.
229	* That depends on the src/dst rectangles being
230	* correctly populated whenever the watermark code
231	* considers the cursor to be visible, whether or not
232	* it is actually visible.
233	*
234	* See: intel_wm_plane_visible() and intel_check_cursor()
235	*/
236
237	return intel_adjusted_rate(src: &plane_state->uapi.src,
238	dst: &plane_state->uapi.dst,
239	rate: crtc_state->pixel_rate);
240	}
241
242	unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
243	const struct intel_plane_state *plane_state,
244	int color_plane)
245	{
246	const struct drm_framebuffer *fb = plane_state->hw.fb;
247
248	if (!plane_state->uapi.visible)
249	return 0;
250
251	return intel_plane_pixel_rate(crtc_state, plane_state) *
252	fb->format->cpp[color_plane];
253	}
254
255	static unsigned int
256	intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
257	const struct intel_plane_state *plane_state,
258	int color_plane)
259	{
260	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
261	const struct drm_framebuffer *fb = plane_state->hw.fb;
262	unsigned int rel_data_rate;
263	int width, height;
264
265	if (plane->id == PLANE_CURSOR)
266	return 0;
267
268	if (!plane_state->uapi.visible)
269	return 0;
270
271	/*
272	* Src coordinates are already rotated by 270 degrees for
273	* the 90/270 degree plane rotation cases (to match the
274	* GTT mapping), hence no need to account for rotation here.
275	*/
276	width = drm_rect_width(r: &plane_state->uapi.src) >> 16;
277	height = drm_rect_height(r: &plane_state->uapi.src) >> 16;
278
279	/* UV plane does 1/2 pixel sub-sampling */
280	if (color_plane == 1) {
281	width /= 2;
282	height /= 2;
283	}
284
285	rel_data_rate =
286	skl_plane_relative_data_rate(crtc_state, plane, width, height,
287	cpp: fb->format->cpp[color_plane]);
288	if (!rel_data_rate)
289	return 0;
290
291	return intel_adjusted_rate(src: &plane_state->uapi.src,
292	dst: &plane_state->uapi.dst,
293	rate: rel_data_rate);
294	}
295
296	static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
297	struct intel_plane *plane)
298	{
299	const struct intel_plane_state *plane_state =
300	intel_atomic_get_new_plane_state(state, plane);
301	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
302	struct intel_crtc_state *new_crtc_state;
303
304	if (!plane_state->uapi.visible || !plane->min_cdclk)
305	return;
306
307	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
308
309	new_crtc_state->plane_min_cdclk[plane->id] =
310	plane->min_cdclk(new_crtc_state, plane_state);
311	}
312
313	static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
314	{
315	if (plane_state->hw.fb)
316	drm_framebuffer_put(fb: plane_state->hw.fb);
317
318	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
319	}
320
321	static void
322	intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
323	const struct intel_plane_state *old_uapi_plane_state,
324	const struct intel_plane_state *new_uapi_plane_state)
325	{
326	struct intel_display *display = to_intel_display(new_plane_state);
327	struct drm_rect *damage = &new_plane_state->damage;
328
329	/* damage property tracking enabled from display version 12 onwards */
330	if (DISPLAY_VER(display) < 12)
331	return;
332
333	if (!drm_atomic_helper_damage_merged(old_state: &old_uapi_plane_state->uapi,
334	state: &new_uapi_plane_state->uapi,
335	rect: damage))
336	/* Incase helper fails, mark whole plane region as damage */
337	*damage = drm_plane_state_src(state: &new_uapi_plane_state->uapi);
338	}
339
340	static bool
341	intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
342	struct intel_colorop *intel_colorop,
343	struct drm_property_blob *blob)
344	{
345	if (intel_colorop->id == INTEL_PLANE_CB_CSC)
346	return drm_property_replace_blob(blob: &plane_state->hw.ctm, new_blob: blob);
347	else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
348	return drm_property_replace_blob(blob: &plane_state->hw.degamma_lut, new_blob: blob);
349	else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
350	return drm_property_replace_blob(blob: &plane_state->hw.gamma_lut, new_blob: blob);
351	else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
352	return drm_property_replace_blob(blob: &plane_state->hw.lut_3d, new_blob: blob);
353
354	return false;
355	}
356
357	static void
358	intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
359	const struct intel_plane_state *from_plane_state,
360	struct intel_crtc *crtc)
361	{
362	struct drm_colorop *iter_colorop, *colorop;
363	struct drm_colorop_state *new_colorop_state;
364	struct drm_atomic_state *state = plane_state->uapi.state;
365	struct intel_colorop *intel_colorop;
366	struct drm_property_blob *blob;
367	struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state);
368	struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
369	intel_atomic_get_new_crtc_state(state: intel_atomic_state, crtc) : NULL;
370	bool changed = false;
371	int i = 0;
372
373	iter_colorop = plane_state->uapi.color_pipeline;
374
375	while (iter_colorop) {
376	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
377	if (new_colorop_state->colorop == iter_colorop) {
378	blob = new_colorop_state->bypass ? NULL : new_colorop_state->data;
379	intel_colorop = to_intel_colorop(colorop);
380	changed |= intel_plane_colorop_replace_blob(plane_state,
381	intel_colorop,
382	blob);
383	}
384	}
385	iter_colorop = iter_colorop->next;
386	}
387
388	if (new_crtc_state && changed)
389	new_crtc_state->plane_color_changed = true;
390	}
391
392	void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
393	const struct intel_plane_state *from_plane_state,
394	struct intel_crtc *crtc)
395	{
396	intel_plane_clear_hw_state(plane_state);
397
398	/*
399	* For the joiner secondary uapi.crtc will point at
400	* the primary crtc. So we explicitly assign the right
401	* secondary crtc to hw.crtc. uapi.crtc!=NULL simply
402	* indicates the plane is logically enabled on the uapi level.
403	*/
404	plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
405
406	plane_state->hw.fb = from_plane_state->uapi.fb;
407	if (plane_state->hw.fb)
408	drm_framebuffer_get(fb: plane_state->hw.fb);
409
410	plane_state->hw.alpha = from_plane_state->uapi.alpha;
411	plane_state->hw.pixel_blend_mode =
412	from_plane_state->uapi.pixel_blend_mode;
413	plane_state->hw.rotation = from_plane_state->uapi.rotation;
414	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
415	plane_state->hw.color_range = from_plane_state->uapi.color_range;
416	plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
417
418	plane_state->uapi.src = drm_plane_state_src(state: &from_plane_state->uapi);
419	plane_state->uapi.dst = drm_plane_state_dest(state: &from_plane_state->uapi);
420
421	intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);
422	}
423
424	void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
425	const struct intel_plane_state *from_plane_state)
426	{
427	intel_plane_clear_hw_state(plane_state);
428
429	memcpy(&plane_state->hw, &from_plane_state->hw,
430	sizeof(plane_state->hw));
431
432	if (plane_state->hw.fb)
433	drm_framebuffer_get(fb: plane_state->hw.fb);
434	}
435
436	void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
437	struct intel_plane_state *plane_state)
438	{
439	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
440
441	crtc_state->active_planes &= ~BIT(plane->id);
442	crtc_state->scaled_planes &= ~BIT(plane->id);
443	crtc_state->nv12_planes &= ~BIT(plane->id);
444	crtc_state->c8_planes &= ~BIT(plane->id);
445	crtc_state->async_flip_planes &= ~BIT(plane->id);
446	crtc_state->data_rate[plane->id] = 0;
447	crtc_state->data_rate_y[plane->id] = 0;
448	crtc_state->rel_data_rate[plane->id] = 0;
449	crtc_state->rel_data_rate_y[plane->id] = 0;
450	crtc_state->plane_min_cdclk[plane->id] = 0;
451
452	plane_state->uapi.visible = false;
453	}
454
455	static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
456	{
457	int src_w = drm_rect_width(r: &plane_state->uapi.src) >> 16;
458	int src_h = drm_rect_height(r: &plane_state->uapi.src) >> 16;
459	int dst_w = drm_rect_width(r: &plane_state->uapi.dst);
460	int dst_h = drm_rect_height(r: &plane_state->uapi.dst);
461
462	return src_w != dst_w || src_h != dst_h;
463	}
464
465	static bool intel_plane_do_async_flip(struct intel_plane *plane,
466	const struct intel_crtc_state *old_crtc_state,
467	const struct intel_crtc_state *new_crtc_state)
468	{
469	struct intel_display *display = to_intel_display(plane);
470
471	if (!plane->async_flip)
472	return false;
473
474	if (!new_crtc_state->uapi.async_flip)
475	return false;
476
477	/*
478	* In platforms after DISPLAY13, we might need to override
479	* first async flip in order to change watermark levels
480	* as part of optimization.
481	*
482	* And let's do this for all skl+ so that we can eg. change the
483	* modifier as well.
484	*
485	* TODO: For older platforms there is less reason to do this as
486	* only X-tile is supported with async flips, though we could
487	* extend this so other scanout parameters (stride/etc) could
488	* be changed as well...
489	*/
490	return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;
491	}
492
493	static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
494	const struct intel_plane_state *old_plane_state,
495	const struct intel_plane_state *new_plane_state)
496	{
497	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
498	bool old_visible = old_plane_state->uapi.visible;
499	bool new_visible = new_plane_state->uapi.visible;
500	u32 old_ctl = old_plane_state->ctl;
501	u32 new_ctl = new_plane_state->ctl;
502	bool modeset, turn_on, turn_off;
503
504	if (plane->id == PLANE_CURSOR)
505	return false;
506
507	modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
508	turn_off = old_visible && (!new_visible || modeset);
509	turn_on = new_visible && (!old_visible || modeset);
510
511	/* Must disable CxSR around plane enable/disable */
512	if (turn_on || turn_off)
513	return true;
514
515	if (!old_visible || !new_visible)
516	return false;
517
518	/*
519	* Most plane control register updates are blocked while in CxSR.
520	*
521	* Tiling mode is one exception where the primary plane can
522	* apparently handle it, whereas the sprites can not (the
523	* sprite issue being only relevant on VLV/CHV where CxSR
524	* is actually possible with a sprite enabled).
525	*/
526	if (plane->id == PLANE_PRIMARY) {
527	old_ctl &= ~DISP_TILED;
528	new_ctl &= ~DISP_TILED;
529	}
530
531	return old_ctl != new_ctl;
532	}
533
534	static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
535	const struct intel_plane_state *old_plane_state,
536	const struct intel_plane_state *new_plane_state)
537	{
538	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
539	bool old_visible = old_plane_state->uapi.visible;
540	bool new_visible = new_plane_state->uapi.visible;
541	bool modeset, turn_on;
542
543	if (plane->id == PLANE_CURSOR)
544	return false;
545
546	modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
547	turn_on = new_visible && (!old_visible || modeset);
548
549	/*
550	* ILK/SNB DVSACNTR/Sprite Enable
551	* IVB SPR_CTL/Sprite Enable
552	* "When in Self Refresh Big FIFO mode, a write to enable the
553	* plane will be internally buffered and delayed while Big FIFO
554	* mode is exiting."
555	*
556	* Which means that enabling the sprite can take an extra frame
557	* when we start in big FIFO mode (LP1+). Thus we need to drop
558	* down to LP0 and wait for vblank in order to make sure the
559	* sprite gets enabled on the next vblank after the register write.
560	* Doing otherwise would risk enabling the sprite one frame after
561	* we've already signalled flip completion. We can resume LP1+
562	* once the sprite has been enabled.
563	*
564	* With experimental results seems this is needed also for primary
565	* plane, not only sprite plane.
566	*/
567	if (turn_on)
568	return true;
569
570	/*
571	* WaCxSRDisabledForSpriteScaling:ivb
572	* IVB SPR_SCALE/Scaling Enable
573	* "Low Power watermarks must be disabled for at least one
574	* frame before enabling sprite scaling, and kept disabled
575	* until sprite scaling is disabled."
576	*
577	* ILK/SNB DVSASCALE/Scaling Enable
578	* "When in Self Refresh Big FIFO mode, scaling enable will be
579	* masked off while Big FIFO mode is exiting."
580	*
581	* Despite the w/a only being listed for IVB we assume that
582	* the ILK/SNB note has similar ramifications, hence we apply
583	* the w/a on all three platforms.
584	*/
585	return !intel_plane_is_scaled(plane_state: old_plane_state) &&
586	intel_plane_is_scaled(plane_state: new_plane_state);
587	}
588
589	static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
590	struct intel_crtc_state *new_crtc_state,
591	const struct intel_plane_state *old_plane_state,
592	struct intel_plane_state *new_plane_state)
593	{
594	struct intel_display *display = to_intel_display(new_crtc_state);
595	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
596	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
597	bool mode_changed = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
598	bool was_crtc_enabled = old_crtc_state->hw.active;
599	bool is_crtc_enabled = new_crtc_state->hw.active;
600	bool turn_off, turn_on, visible, was_visible;
601	int ret;
602
603	if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {
604	ret = skl_update_scaler_plane(crtc_state: new_crtc_state, plane_state: new_plane_state);
605	if (ret)
606	return ret;
607	}
608
609	was_visible = old_plane_state->uapi.visible;
610	visible = new_plane_state->uapi.visible;
611
612	if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))
613	was_visible = false;
614
615	/*
616	* Visibility is calculated as if the crtc was on, but
617	* after scaler setup everything depends on it being off
618	* when the crtc isn't active.
619	*
620	* FIXME this is wrong for watermarks. Watermarks should also
621	* be computed as if the pipe would be active. Perhaps move
622	* per-plane wm computation to the .check_plane() hook, and
623	* only combine the results from all planes in the current place?
624	*/
625	if (!is_crtc_enabled) {
626	intel_plane_set_invisible(crtc_state: new_crtc_state, plane_state: new_plane_state);
627	visible = false;
628	}
629
630	if (!was_visible && !visible)
631	return 0;
632
633	turn_off = was_visible && (!visible || mode_changed);
634	turn_on = visible && (!was_visible || mode_changed);
635
636	drm_dbg_atomic(display->drm,
637	"[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
638	crtc->base.base.id, crtc->base.name,
639	plane->base.base.id, plane->base.name,
640	was_visible, visible,
641	turn_off, turn_on, mode_changed);
642
643	if (visible || was_visible)
644	new_crtc_state->fb_bits |= plane->frontbuffer_bit;
645
646	if (HAS_GMCH(display) &&
647	i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
648	new_crtc_state->disable_cxsr = true;
649
650	if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&
651	ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
652	new_crtc_state->disable_cxsr = true;
653
654	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
655	new_crtc_state->do_async_flip = true;
656	new_crtc_state->async_flip_planes |= BIT(plane->id);
657	} else if (plane->need_async_flip_toggle_wa &&
658	new_crtc_state->uapi.async_flip) {
659	/*
660	* On platforms with double buffered async flip bit we
661	* set the bit already one frame early during the sync
662	* flip (see {i9xx,skl}_plane_update_arm()). The
663	* hardware will therefore be ready to perform a real
664	* async flip during the next commit, without having
665	* to wait yet another frame for the bit to latch.
666	*/
667	new_crtc_state->async_flip_planes |= BIT(plane->id);
668	}
669
670	return 0;
671	}
672
673	int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
674	struct intel_crtc_state *new_crtc_state,
675	const struct intel_plane_state *old_plane_state,
676	struct intel_plane_state *new_plane_state)
677	{
678	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
679	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
680	int ret;
681
682	intel_plane_set_invisible(crtc_state: new_crtc_state, plane_state: new_plane_state);
683	new_crtc_state->enabled_planes &= ~BIT(plane->id);
684
685	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
686	return 0;
687
688	ret = plane->check_plane(new_crtc_state, new_plane_state);
689	if (ret)
690	return ret;
691
692	if (fb)
693	new_crtc_state->enabled_planes |= BIT(plane->id);
694
695	/* FIXME pre-g4x don't work like this */
696	if (new_plane_state->uapi.visible)
697	new_crtc_state->active_planes |= BIT(plane->id);
698
699	if (new_plane_state->uapi.visible &&
700	intel_plane_is_scaled(plane_state: new_plane_state))
701	new_crtc_state->scaled_planes |= BIT(plane->id);
702
703	if (new_plane_state->uapi.visible &&
704	intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier))
705	new_crtc_state->nv12_planes |= BIT(plane->id);
706
707	if (new_plane_state->uapi.visible &&
708	fb->format->format == DRM_FORMAT_C8)
709	new_crtc_state->c8_planes |= BIT(plane->id);
710
711	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
712	new_crtc_state->update_planes |= BIT(plane->id);
713
714	if (new_plane_state->uapi.visible &&
715	intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier)) {
716	new_crtc_state->data_rate_y[plane->id] =
717	intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 0);
718	new_crtc_state->data_rate[plane->id] =
719	intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 1);
720
721	new_crtc_state->rel_data_rate_y[plane->id] =
722	intel_plane_relative_data_rate(crtc_state: new_crtc_state,
723	plane_state: new_plane_state, color_plane: 0);
724	new_crtc_state->rel_data_rate[plane->id] =
725	intel_plane_relative_data_rate(crtc_state: new_crtc_state,
726	plane_state: new_plane_state, color_plane: 1);
727	} else if (new_plane_state->uapi.visible) {
728	new_crtc_state->data_rate[plane->id] =
729	intel_plane_data_rate(crtc_state: new_crtc_state, plane_state: new_plane_state, color_plane: 0);
730
731	new_crtc_state->rel_data_rate[plane->id] =
732	intel_plane_relative_data_rate(crtc_state: new_crtc_state,
733	plane_state: new_plane_state, color_plane: 0);
734	}
735
736	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
737	old_plane_state, new_plane_state);
738	}
739
740	struct intel_plane *
741	intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
742	{
743	struct intel_display *display = to_intel_display(crtc);
744	struct intel_plane *plane;
745
746	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
747	if (plane->id == plane_id)
748	return plane;
749	}
750
751	return NULL;
752	}
753
754	static int plane_atomic_check(struct intel_atomic_state *state,
755	struct intel_plane *plane)
756	{
757	struct intel_display *display = to_intel_display(state);
758	struct intel_plane_state *new_plane_state =
759	intel_atomic_get_new_plane_state(state, plane);
760	const struct intel_plane_state *old_plane_state =
761	intel_atomic_get_old_plane_state(state, plane);
762	const struct intel_plane_state *new_primary_crtc_plane_state;
763	const struct intel_plane_state *old_primary_crtc_plane_state;
764	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe: plane->pipe);
765	const struct intel_crtc_state *old_crtc_state =
766	intel_atomic_get_old_crtc_state(state, crtc);
767	struct intel_crtc_state *new_crtc_state =
768	intel_atomic_get_new_crtc_state(state, crtc);
769
770	if (new_crtc_state && intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state)) {
771	struct intel_crtc *primary_crtc =
772	intel_primary_crtc(crtc_state: new_crtc_state);
773	struct intel_plane *primary_crtc_plane =
774	intel_crtc_get_plane(crtc: primary_crtc, plane_id: plane->id);
775
776	new_primary_crtc_plane_state =
777	intel_atomic_get_new_plane_state(state, plane: primary_crtc_plane);
778	old_primary_crtc_plane_state =
779	intel_atomic_get_old_plane_state(state, plane: primary_crtc_plane);
780	} else {
781	new_primary_crtc_plane_state = new_plane_state;
782	old_primary_crtc_plane_state = old_plane_state;
783	}
784
785	intel_plane_copy_uapi_plane_damage(new_plane_state,
786	old_uapi_plane_state: old_primary_crtc_plane_state,
787	new_uapi_plane_state: new_primary_crtc_plane_state);
788
789	intel_plane_copy_uapi_to_hw_state(plane_state: new_plane_state,
790	from_plane_state: new_primary_crtc_plane_state,
791	crtc);
792
793	new_plane_state->uapi.visible = false;
794	if (!new_crtc_state)
795	return 0;
796
797	return intel_plane_atomic_check_with_state(old_crtc_state,
798	new_crtc_state,
799	old_plane_state,
800	new_plane_state);
801	}
802
803	static struct intel_plane *
804	skl_next_plane_to_commit(struct intel_atomic_state *state,
805	struct intel_crtc *crtc,
806	struct skl_ddb_entry ddb[I915_MAX_PLANES],
807	struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
808	unsigned int *update_mask)
809	{
810	struct intel_crtc_state *crtc_state =
811	intel_atomic_get_new_crtc_state(state, crtc);
812	struct intel_plane_state __maybe_unused *plane_state;
813	struct intel_plane *plane;
814	int i;
815
816	if (*update_mask == 0)
817	return NULL;
818
819	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
820	enum plane_id plane_id = plane->id;
821
822	if (crtc->pipe != plane->pipe ||
823	!(*update_mask & BIT(plane_id)))
824	continue;
825
826	if (skl_ddb_allocation_overlaps(ddb: &crtc_state->wm.skl.plane_ddb[plane_id],
827	entries: ddb, num_entries: I915_MAX_PLANES, ignore_idx: plane_id) ||
828	skl_ddb_allocation_overlaps(ddb: &crtc_state->wm.skl.plane_ddb_y[plane_id],
829	entries: ddb_y, num_entries: I915_MAX_PLANES, ignore_idx: plane_id))
830	continue;
831
832	*update_mask &= ~BIT(plane_id);
833	ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
834	ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
835
836	return plane;
837	}
838
839	/* should never happen */
840	drm_WARN_ON(state->base.dev, 1);
841
842	return NULL;
843	}
844
845	void intel_plane_update_noarm(struct intel_dsb *dsb,
846	struct intel_plane *plane,
847	const struct intel_crtc_state *crtc_state,
848	const struct intel_plane_state *plane_state)
849	{
850	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
851
852	trace_intel_plane_update_noarm(plane_state, crtc);
853
854	if (plane->fbc)
855	intel_fbc_dirty_rect_update_noarm(dsb, plane);
856
857	if (plane->update_noarm)
858	plane->update_noarm(dsb, plane, crtc_state, plane_state);
859	}
860
861	void intel_plane_async_flip(struct intel_dsb *dsb,
862	struct intel_plane *plane,
863	const struct intel_crtc_state *crtc_state,
864	const struct intel_plane_state *plane_state,
865	bool async_flip)
866	{
867	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
868
869	trace_intel_plane_async_flip(plane, crtc, async_flip);
870	plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
871	}
872
873	void intel_plane_update_arm(struct intel_dsb *dsb,
874	struct intel_plane *plane,
875	const struct intel_crtc_state *crtc_state,
876	const struct intel_plane_state *plane_state)
877	{
878	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
879
880	if (crtc_state->do_async_flip && plane->async_flip) {
881	intel_plane_async_flip(dsb, plane, crtc_state, plane_state, async_flip: true);
882	return;
883	}
884
885	trace_intel_plane_update_arm(plane_state, crtc);
886	plane->update_arm(dsb, plane, crtc_state, plane_state);
887	}
888
889	void intel_plane_disable_arm(struct intel_dsb *dsb,
890	struct intel_plane *plane,
891	const struct intel_crtc_state *crtc_state)
892	{
893	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
894
895	trace_intel_plane_disable_arm(plane, crtc);
896	plane->disable_arm(dsb, plane, crtc_state);
897	}
898
899	void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
900	struct intel_atomic_state *state,
901	struct intel_crtc *crtc)
902	{
903	struct intel_crtc_state *new_crtc_state =
904	intel_atomic_get_new_crtc_state(state, crtc);
905	u32 update_mask = new_crtc_state->update_planes;
906	struct intel_plane_state *new_plane_state;
907	struct intel_plane *plane;
908	int i;
909
910	if (new_crtc_state->do_async_flip)
911	return;
912
913	/*
914	* Since we only write non-arming registers here,
915	* the order does not matter even for skl+.
916	*/
917	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
918	if (crtc->pipe != plane->pipe ||
919	!(update_mask & BIT(plane->id)))
920	continue;
921
922	/* TODO: for mailbox updates this should be skipped */
923	if (new_plane_state->uapi.visible ||
924	new_plane_state->is_y_plane)
925	intel_plane_update_noarm(dsb, plane,
926	crtc_state: new_crtc_state, plane_state: new_plane_state);
927	}
928	}
929
930	static void skl_crtc_planes_update_arm(struct intel_dsb *dsb,
931	struct intel_atomic_state *state,
932	struct intel_crtc *crtc)
933	{
934	struct intel_crtc_state *old_crtc_state =
935	intel_atomic_get_old_crtc_state(state, crtc);
936	struct intel_crtc_state *new_crtc_state =
937	intel_atomic_get_new_crtc_state(state, crtc);
938	struct skl_ddb_entry ddb[I915_MAX_PLANES];
939	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
940	u32 update_mask = new_crtc_state->update_planes;
941	struct intel_plane *plane;
942
943	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
944	sizeof(old_crtc_state->wm.skl.plane_ddb));
945	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
946	sizeof(old_crtc_state->wm.skl.plane_ddb_y));
947
948	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, update_mask: &update_mask))) {
949	struct intel_plane_state *new_plane_state =
950	intel_atomic_get_new_plane_state(state, plane);
951
952	/*
953	* TODO: for mailbox updates intel_plane_update_noarm()
954	* would have to be called here as well.
955	*/
956	if (new_plane_state->uapi.visible ||
957	new_plane_state->is_y_plane)
958	intel_plane_update_arm(dsb, plane, crtc_state: new_crtc_state, plane_state: new_plane_state);
959	else
960	intel_plane_disable_arm(dsb, plane, crtc_state: new_crtc_state);
961	}
962	}
963
964	static void i9xx_crtc_planes_update_arm(struct intel_dsb *dsb,
965	struct intel_atomic_state *state,
966	struct intel_crtc *crtc)
967	{
968	struct intel_crtc_state *new_crtc_state =
969	intel_atomic_get_new_crtc_state(state, crtc);
970	u32 update_mask = new_crtc_state->update_planes;
971	struct intel_plane_state *new_plane_state;
972	struct intel_plane *plane;
973	int i;
974
975	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
976	if (crtc->pipe != plane->pipe ||
977	!(update_mask & BIT(plane->id)))
978	continue;
979
980	/*
981	* TODO: for mailbox updates intel_plane_update_noarm()
982	* would have to be called here as well.
983	*/
984	if (new_plane_state->uapi.visible)
985	intel_plane_update_arm(dsb, plane, crtc_state: new_crtc_state, plane_state: new_plane_state);
986	else
987	intel_plane_disable_arm(dsb, plane, crtc_state: new_crtc_state);
988	}
989	}
990
991	void intel_crtc_planes_update_arm(struct intel_dsb *dsb,
992	struct intel_atomic_state *state,
993	struct intel_crtc *crtc)
994	{
995	struct intel_display *display = to_intel_display(state);
996
997	if (DISPLAY_VER(display) >= 9)
998	skl_crtc_planes_update_arm(dsb, state, crtc);
999	else
1000	i9xx_crtc_planes_update_arm(dsb, state, crtc);
1001	}
1002
1003	int intel_plane_check_clipping(struct intel_plane_state *plane_state,
1004	struct intel_crtc_state *crtc_state,
1005	int min_scale, int max_scale,
1006	bool can_position)
1007	{
1008	struct intel_display *display = to_intel_display(plane_state);
1009	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1010	struct drm_framebuffer *fb = plane_state->hw.fb;
1011	struct drm_rect *src = &plane_state->uapi.src;
1012	struct drm_rect *dst = &plane_state->uapi.dst;
1013	const struct drm_rect *clip = &crtc_state->pipe_src;
1014	unsigned int rotation = plane_state->hw.rotation;
1015	int hscale, vscale;
1016
1017	if (!fb) {
1018	plane_state->uapi.visible = false;
1019	return 0;
1020	}
1021
1022	drm_rect_rotate(r: src, width: fb->width << 16, height: fb->height << 16, rotation);
1023
1024	/* Check scaling */
1025	hscale = drm_rect_calc_hscale(src, dst, min_hscale: min_scale, max_hscale: max_scale);
1026	vscale = drm_rect_calc_vscale(src, dst, min_vscale: min_scale, max_vscale: max_scale);
1027	if (hscale < 0 || vscale < 0) {
1028	drm_dbg_kms(display->drm,
1029	"[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n",
1030	plane->base.base.id, plane->base.name,
1031	DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst));
1032	return -ERANGE;
1033	}
1034
1035	/*
1036	* FIXME: This might need further adjustment for seamless scaling
1037	* with phase information, for the 2p2 and 2p1 scenarios.
1038	*/
1039	plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
1040
1041	drm_rect_rotate_inv(r: src, width: fb->width << 16, height: fb->height << 16, rotation);
1042
1043	if (!can_position && plane_state->uapi.visible &&
1044	!drm_rect_equals(r1: dst, r2: clip)) {
1045	drm_dbg_kms(display->drm,
1046	"[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n",
1047	plane->base.base.id, plane->base.name,
1048	DRM_RECT_ARG(dst), DRM_RECT_ARG(clip));
1049	return -EINVAL;
1050	}
1051
1052	/* final plane coordinates will be relative to the plane's pipe */
1053	drm_rect_translate(r: dst, dx: -clip->x1, dy: -clip->y1);
1054
1055	return 0;
1056	}
1057
1058	int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
1059	{
1060	struct intel_display *display = to_intel_display(plane_state);
1061	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1062	const struct drm_framebuffer *fb = plane_state->hw.fb;
1063	struct drm_rect *src = &plane_state->uapi.src;
1064	u32 src_x, src_y, src_w, src_h, hsub, vsub;
1065	bool rotated = drm_rotation_90_or_270(rotation: plane_state->hw.rotation);
1066
1067	/*
1068	* FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
1069	* abuses hsub/vsub so we can't use them here. But as they
1070	* are limited to 32bpp RGB formats we don't actually need
1071	* to check anything.
1072	*/
1073	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1074	fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
1075	return 0;
1076
1077	/*
1078	* Hardware doesn't handle subpixel coordinates.
1079	* Adjust to (macro)pixel boundary, but be careful not to
1080	* increase the source viewport size, because that could
1081	* push the downscaling factor out of bounds.
1082	*/
1083	src_x = src->x1 >> 16;
1084	src_w = drm_rect_width(r: src) >> 16;
1085	src_y = src->y1 >> 16;
1086	src_h = drm_rect_height(r: src) >> 16;
1087
1088	drm_rect_init(r: src, x: src_x << 16, y: src_y << 16,
1089	width: src_w << 16, height: src_h << 16);
1090
1091	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
1092	hsub = 2;
1093	vsub = 2;
1094	} else if (DISPLAY_VER(display) >= 20 &&
1095	intel_format_info_is_yuv_semiplanar(info: fb->format, modifier: fb->modifier)) {
1096	/*
1097	* This allows NV12 and P0xx formats to have odd size and/or odd
1098	* source coordinates on DISPLAY_VER(display) >= 20
1099	*/
1100	hsub = 1;
1101	vsub = 1;
1102
1103	/* Wa_16023981245 */
1104	if ((DISPLAY_VERx100(display) == 2000 ||
1105	DISPLAY_VERx100(display) == 3000 ||
1106	DISPLAY_VERx100(display) == 3002) &&
1107	src_x % 2 != 0)
1108	hsub = 2;
1109
1110	if (DISPLAY_VER(display) == 35)
1111	vsub = 2;
1112	} else {
1113	hsub = fb->format->hsub;
1114	vsub = fb->format->vsub;
1115	}
1116
1117	if (rotated)
1118	hsub = vsub = max(hsub, vsub);
1119
1120	if (src_x % hsub || src_w % hsub) {
1121	drm_dbg_kms(display->drm,
1122	"[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
1123	plane->base.base.id, plane->base.name,
1124	src_x, src_w, hsub, str_yes_no(rotated));
1125	return -EINVAL;
1126	}
1127
1128	if (src_y % vsub || src_h % vsub) {
1129	drm_dbg_kms(display->drm,
1130	"[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
1131	plane->base.base.id, plane->base.name,
1132	src_y, src_h, vsub, str_yes_no(rotated));
1133	return -EINVAL;
1134	}
1135
1136	return 0;
1137	}
1138
1139	static int add_dma_resv_fences(struct dma_resv *resv,
1140	struct drm_plane_state *new_plane_state)
1141	{
1142	struct dma_fence *fence = dma_fence_get(fence: new_plane_state->fence);
1143	struct dma_fence *new;
1144	int ret;
1145
1146	ret = dma_resv_get_singleton(obj: resv, usage: dma_resv_usage_rw(write: false), fence: &new);
1147	if (ret)
1148	goto error;
1149
1150	if (new && fence) {
1151	struct dma_fence_chain *chain = dma_fence_chain_alloc();
1152
1153	if (!chain) {
1154	ret = -ENOMEM;
1155	goto error;
1156	}
1157
1158	dma_fence_chain_init(chain, prev: fence, fence: new, seqno: 1);
1159	fence = &chain->base;
1160
1161	} else if (new) {
1162	fence = new;
1163	}
1164
1165	dma_fence_put(fence: new_plane_state->fence);
1166	new_plane_state->fence = fence;
1167	return 0;
1168
1169	error:
1170	dma_fence_put(fence);
1171	return ret;
1172	}
1173
1174	/**
1175	* intel_prepare_plane_fb - Prepare fb for usage on plane
1176	* @_plane: drm plane to prepare for
1177	* @_new_plane_state: the plane state being prepared
1178	*
1179	* Prepares a framebuffer for usage on a display plane. Generally this
1180	* involves pinning the underlying object and updating the frontbuffer tracking
1181	* bits. Some older platforms need special physical address handling for
1182	* cursor planes.
1183	*
1184	* Returns 0 on success, negative error code on failure.
1185	*/
1186	static int
1187	intel_prepare_plane_fb(struct drm_plane *_plane,
1188	struct drm_plane_state *_new_plane_state)
1189	{
1190	struct intel_plane *plane = to_intel_plane(_plane);
1191	struct intel_display *display = to_intel_display(plane);
1192	struct intel_plane_state *new_plane_state =
1193	to_intel_plane_state(_new_plane_state);
1194	struct intel_atomic_state *state =
1195	to_intel_atomic_state(new_plane_state->uapi.state);
1196	struct intel_plane_state *old_plane_state =
1197	intel_atomic_get_old_plane_state(state, plane);
1198	struct drm_gem_object *obj = intel_fb_bo(fb: new_plane_state->hw.fb);
1199	struct drm_gem_object *old_obj = intel_fb_bo(fb: old_plane_state->hw.fb);
1200	int ret;
1201
1202	if (old_obj) {
1203	const struct intel_crtc_state *new_crtc_state =
1204	intel_atomic_get_new_crtc_state(state,
1205	to_intel_crtc(old_plane_state->hw.crtc));
1206
1207	/* Big Hammer, we also need to ensure that any pending
1208	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
1209	* current scanout is retired before unpinning the old
1210	* framebuffer. Note that we rely on userspace rendering
1211	* into the buffer attached to the pipe they are waiting
1212	* on. If not, userspace generates a GPU hang with IPEHR
1213	* point to the MI_WAIT_FOR_EVENT.
1214	*
1215	* This should only fail upon a hung GPU, in which case we
1216	* can safely continue.
1217	*/
1218	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
1219	ret = add_dma_resv_fences(resv: old_obj->resv,
1220	new_plane_state: &new_plane_state->uapi);
1221	if (ret < 0)
1222	return ret;
1223	}
1224	}
1225
1226	if (!obj)
1227	return 0;
1228
1229	ret = intel_plane_pin_fb(new_plane_state, old_plane_state);
1230	if (ret)
1231	return ret;
1232
1233	ret = drm_gem_plane_helper_prepare_fb(plane: &plane->base, state: &new_plane_state->uapi);
1234	if (ret < 0)
1235	goto unpin_fb;
1236
1237	if (new_plane_state->uapi.fence) {
1238	i915_gem_fence_wait_priority_display(fence: new_plane_state->uapi.fence);
1239
1240	intel_display_rps_boost_after_vblank(crtc: new_plane_state->hw.crtc,
1241	fence: new_plane_state->uapi.fence);
1242	}
1243
1244	/*
1245	* We declare pageflips to be interactive and so merit a small bias
1246	* towards upclocking to deliver the frame on time. By only changing
1247	* the RPS thresholds to sample more regularly and aim for higher
1248	* clocks we can hopefully deliver low power workloads (like kodi)
1249	* that are not quite steady state without resorting to forcing
1250	* maximum clocks following a vblank miss (see do_rps_boost()).
1251	*/
1252	intel_display_rps_mark_interactive(display, state, interactive: true);
1253
1254	return 0;
1255
1256	unpin_fb:
1257	intel_plane_unpin_fb(old_plane_state: new_plane_state);
1258
1259	return ret;
1260	}
1261
1262	/**
1263	* intel_cleanup_plane_fb - Cleans up an fb after plane use
1264	* @plane: drm plane to clean up for
1265	* @_old_plane_state: the state from the previous modeset
1266	*
1267	* Cleans up a framebuffer that has just been removed from a plane.
1268	*/
1269	static void
1270	intel_cleanup_plane_fb(struct drm_plane *plane,
1271	struct drm_plane_state *_old_plane_state)
1272	{
1273	struct intel_display *display = to_intel_display(plane->dev);
1274	struct intel_plane_state *old_plane_state =
1275	to_intel_plane_state(_old_plane_state);
1276	struct intel_atomic_state *state =
1277	to_intel_atomic_state(old_plane_state->uapi.state);
1278	struct drm_gem_object *obj = intel_fb_bo(fb: old_plane_state->hw.fb);
1279
1280	if (!obj)
1281	return;
1282
1283	intel_display_rps_mark_interactive(display, state, interactive: false);
1284
1285	intel_plane_unpin_fb(old_plane_state);
1286	}
1287
1288	/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is easier)
1289	* All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32x32
1290	* pixels for 32bits pixels.
1291	*/
1292	#define YTILE_WIDTH 32
1293	#define YTILE_HEIGHT 32
1294	#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4)
1295
1296	static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1297	{
1298	u32 offset;
1299	unsigned int swizzle;
1300	unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1301
1302	/* Block offset */
1303	offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1304
1305	x = x % YTILE_WIDTH;
1306	y = y % YTILE_HEIGHT;
1307
1308	/* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */
1309	swizzle = (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5);
1310	offset += swizzle * 4;
1311	return offset;
1312	}
1313
1314	static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1315	{
1316	u32 offset;
1317	unsigned int swizzle;
1318	unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1319
1320	/* Block offset */
1321	offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1322
1323	x = x % YTILE_WIDTH;
1324	y = y % YTILE_HEIGHT;
1325
1326	/* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */
1327	swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 |
1328	((x & 0x10) << 3) | ((y & 0x18) << 5);
1329	offset += swizzle * 4;
1330	return offset;
1331	}
1332
1333	static void intel_panic_flush(struct drm_plane *plane)
1334	{
1335	struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
1336	struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);
1337	struct intel_plane *iplane = to_intel_plane(plane);
1338	struct intel_display *display = to_intel_display(iplane);
1339	struct drm_framebuffer *fb = plane_state->hw.fb;
1340	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1341
1342	intel_panic_finish(panic: intel_fb->panic);
1343
1344	if (crtc_state->enable_psr2_sel_fetch) {
1345	/* Force a full update for psr2 */
1346	intel_psr2_panic_force_full_update(display, crtc_state);
1347	}
1348
1349	/* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/
1350	if (intel_fb == intel_fbdev_framebuffer(fbdev: display->fbdev.fbdev)) {
1351	struct iosys_map map;
1352
1353	intel_fbdev_get_map(fbdev: display->fbdev.fbdev, map: &map);
1354	drm_clflush_virt_range(addr: map.vaddr, length: fb->pitches[0] * fb->height);
1355	return;
1356	}
1357
1358	if (fb->modifier && iplane->disable_tiling)
1359	iplane->disable_tiling(iplane);
1360	}
1361
1362	static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width,
1363	unsigned int x,
1364	unsigned int y)
1365	{
1366	switch (fb_modifier) {
1367	case I915_FORMAT_MOD_Y_TILED:
1368	case I915_FORMAT_MOD_Y_TILED_CCS:
1369	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1370	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1371	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1372	return intel_ytile_get_offset;
1373	case I915_FORMAT_MOD_4_TILED:
1374	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
1375	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
1376	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
1377	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
1378	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
1379	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
1380	case I915_FORMAT_MOD_4_TILED_BMG_CCS:
1381	case I915_FORMAT_MOD_4_TILED_LNL_CCS:
1382	return intel_4tile_get_offset;
1383	case I915_FORMAT_MOD_X_TILED:
1384	case I915_FORMAT_MOD_Yf_TILED:
1385	case I915_FORMAT_MOD_Yf_TILED_CCS:
1386	default:
1387	/* Not supported yet */
1388	return NULL;
1389	}
1390	}
1391
1392	static int intel_get_scanout_buffer(struct drm_plane *plane,
1393	struct drm_scanout_buffer *sb)
1394	{
1395	struct intel_plane_state *plane_state;
1396	struct drm_gem_object *obj;
1397	struct drm_framebuffer *fb;
1398	struct intel_framebuffer *intel_fb;
1399	struct intel_display *display = to_intel_display(plane->dev);
1400
1401	if (!plane->state || !plane->state->fb || !plane->state->visible)
1402	return -ENODEV;
1403
1404	plane_state = to_intel_plane_state(plane->state);
1405	fb = plane_state->hw.fb;
1406	intel_fb = to_intel_framebuffer(fb);
1407
1408	obj = intel_fb_bo(fb);
1409	if (!obj)
1410	return -ENODEV;
1411
1412	if (intel_fb == intel_fbdev_framebuffer(fbdev: display->fbdev.fbdev)) {
1413	intel_fbdev_get_map(fbdev: display->fbdev.fbdev, map: &sb->map[0]);
1414	} else {
1415	int ret;
1416	/* Can't disable tiling if DPT is in use */
1417	if (intel_fb_uses_dpt(fb)) {
1418	if (fb->format->cpp[0] != 4)
1419	return -EOPNOTSUPP;
1420	intel_fb->panic_tiling = intel_get_tiling_func(fb_modifier: fb->modifier);
1421	if (!intel_fb->panic_tiling)
1422	return -EOPNOTSUPP;
1423	}
1424	sb->private = intel_fb;
1425	ret = intel_panic_setup(panic: intel_fb->panic, sb);
1426	if (ret)
1427	return ret;
1428	}
1429	sb->width = fb->width;
1430	sb->height = fb->height;
1431	/* Use the generic linear format, because tiling, RC, CCS, CC
1432	* will be disabled in disable_tiling()
1433	*/
1434	sb->format = drm_format_info(format: fb->format->format);
1435	sb->pitch[0] = fb->pitches[0];
1436
1437	return 0;
1438	}
1439
1440	static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1441	.prepare_fb = intel_prepare_plane_fb,
1442	.cleanup_fb = intel_cleanup_plane_fb,
1443	};
1444
1445	static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = {
1446	.prepare_fb = intel_prepare_plane_fb,
1447	.cleanup_fb = intel_cleanup_plane_fb,
1448	.get_scanout_buffer = intel_get_scanout_buffer,
1449	.panic_flush = intel_panic_flush,
1450	};
1451
1452	void intel_plane_helper_add(struct intel_plane *plane)
1453	{
1454	if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1455	drm_plane_helper_add(plane: &plane->base, funcs: &intel_primary_plane_helper_funcs);
1456	else
1457	drm_plane_helper_add(plane: &plane->base, funcs: &intel_plane_helper_funcs);
1458	}
1459
1460	void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
1461	struct intel_plane_state *new_plane_state)
1462	{
1463	if (!old_plane_state->ggtt_vma ||
1464	old_plane_state->ggtt_vma == new_plane_state->ggtt_vma)
1465	return;
1466
1467	drm_vblank_work_init(work: &old_plane_state->unpin_work, crtc: old_plane_state->uapi.crtc,
1468	func: intel_cursor_unpin_work);
1469	}
1470
1471	static void link_nv12_planes(struct intel_crtc_state *crtc_state,
1472	struct intel_plane_state *uv_plane_state,
1473	struct intel_plane_state *y_plane_state)
1474	{
1475	struct intel_display *display = to_intel_display(uv_plane_state);
1476	struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);
1477	struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);
1478
1479	drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",
1480	uv_plane->base.base.id, uv_plane->base.name,
1481	y_plane->base.base.id, y_plane->base.name);
1482
1483	uv_plane_state->planar_linked_plane = y_plane;
1484
1485	y_plane_state->is_y_plane = true;
1486	y_plane_state->planar_linked_plane = uv_plane;
1487
1488	crtc_state->enabled_planes |= BIT(y_plane->id);
1489	crtc_state->active_planes |= BIT(y_plane->id);
1490	crtc_state->update_planes |= BIT(y_plane->id);
1491
1492	crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];
1493	crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];
1494
1495	/* Copy parameters to Y plane */
1496	intel_plane_copy_hw_state(plane_state: y_plane_state, from_plane_state: uv_plane_state);
1497	y_plane_state->uapi.src = uv_plane_state->uapi.src;
1498	y_plane_state->uapi.dst = uv_plane_state->uapi.dst;
1499
1500	y_plane_state->ctl = uv_plane_state->ctl;
1501	y_plane_state->color_ctl = uv_plane_state->color_ctl;
1502	y_plane_state->view = uv_plane_state->view;
1503	y_plane_state->decrypt = uv_plane_state->decrypt;
1504
1505	icl_link_nv12_planes(uv_plane_state, y_plane_state);
1506	}
1507
1508	static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
1509	struct intel_plane_state *plane_state)
1510	{
1511	struct intel_display *display = to_intel_display(plane_state);
1512	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1513
1514	plane_state->planar_linked_plane = NULL;
1515
1516	if (!plane_state->is_y_plane)
1517	return;
1518
1519	drm_WARN_ON(display->drm, plane_state->uapi.visible);
1520
1521	plane_state->is_y_plane = false;
1522
1523	crtc_state->enabled_planes &= ~BIT(plane->id);
1524	crtc_state->active_planes &= ~BIT(plane->id);
1525	crtc_state->update_planes |= BIT(plane->id);
1526	crtc_state->data_rate[plane->id] = 0;
1527	crtc_state->rel_data_rate[plane->id] = 0;
1528	}
1529
1530	static int icl_check_nv12_planes(struct intel_atomic_state *state,
1531	struct intel_crtc *crtc)
1532	{
1533	struct intel_display *display = to_intel_display(state);
1534	struct intel_crtc_state *crtc_state =
1535	intel_atomic_get_new_crtc_state(state, crtc);
1536	struct intel_plane_state *plane_state;
1537	struct intel_plane *plane;
1538	int i;
1539
1540	if (DISPLAY_VER(display) < 11)
1541	return 0;
1542
1543	/*
1544	* Destroy all old plane links and make the Y plane invisible
1545	* in the crtc_state->active_planes mask.
1546	*/
1547	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1548	if (plane->pipe != crtc->pipe)
1549	continue;
1550
1551	if (plane_state->planar_linked_plane)
1552	unlink_nv12_plane(crtc_state, plane_state);
1553	}
1554
1555	if (!crtc_state->nv12_planes)
1556	return 0;
1557
1558	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1559	struct intel_plane_state *y_plane_state = NULL;
1560	struct intel_plane *y_plane;
1561
1562	if (plane->pipe != crtc->pipe)
1563	continue;
1564
1565	if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
1566	continue;
1567
1568	for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {
1569	if (!icl_is_nv12_y_plane(display, plane_id: y_plane->id))
1570	continue;
1571
1572	if (crtc_state->active_planes & BIT(y_plane->id))
1573	continue;
1574
1575	y_plane_state = intel_atomic_get_plane_state(state, plane: y_plane);
1576	if (IS_ERR(ptr: y_plane_state))
1577	return PTR_ERR(ptr: y_plane_state);
1578
1579	break;
1580	}
1581
1582	if (!y_plane_state) {
1583	drm_dbg_kms(display->drm,
1584	"[CRTC:%d:%s] need %d free Y planes for planar YUV\n",
1585	crtc->base.base.id, crtc->base.name,
1586	hweight8(crtc_state->nv12_planes));
1587	return -EINVAL;
1588	}
1589
1590	link_nv12_planes(crtc_state, uv_plane_state: plane_state, y_plane_state);
1591	}
1592
1593	return 0;
1594	}
1595
1596	static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
1597	struct intel_crtc *crtc,
1598	u8 plane_ids_mask)
1599	{
1600	struct intel_display *display = to_intel_display(state);
1601	struct intel_plane *plane;
1602
1603	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
1604	struct intel_plane_state *plane_state;
1605
1606	if ((plane_ids_mask & BIT(plane->id)) == 0)
1607	continue;
1608
1609	plane_state = intel_atomic_get_plane_state(state, plane);
1610	if (IS_ERR(ptr: plane_state))
1611	return PTR_ERR(ptr: plane_state);
1612	}
1613
1614	return 0;
1615	}
1616
1617	int intel_plane_add_affected(struct intel_atomic_state *state,
1618	struct intel_crtc *crtc)
1619	{
1620	const struct intel_crtc_state *old_crtc_state =
1621	intel_atomic_get_old_crtc_state(state, crtc);
1622	const struct intel_crtc_state *new_crtc_state =
1623	intel_atomic_get_new_crtc_state(state, crtc);
1624
1625	return intel_crtc_add_planes_to_state(state, crtc,
1626	plane_ids_mask: old_crtc_state->enabled_planes |
1627	new_crtc_state->enabled_planes);
1628	}
1629
1630	static bool active_planes_affects_min_cdclk(struct intel_display *display)
1631	{
1632	/* See {hsw,vlv,ivb}_plane_ratio() */
1633	return display->platform.broadwell || display->platform.haswell ||
1634	display->platform.cherryview || display->platform.valleyview ||
1635	display->platform.ivybridge;
1636	}
1637
1638	static u8 intel_joiner_affected_planes(struct intel_atomic_state *state,
1639	u8 joined_pipes)
1640	{
1641	const struct intel_plane_state *plane_state;
1642	struct intel_plane *plane;
1643	u8 affected_planes = 0;
1644	int i;
1645
1646	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1647	struct intel_plane *linked = plane_state->planar_linked_plane;
1648
1649	if ((joined_pipes & BIT(plane->pipe)) == 0)
1650	continue;
1651
1652	affected_planes |= BIT(plane->id);
1653	if (linked)
1654	affected_planes |= BIT(linked->id);
1655	}
1656
1657	return affected_planes;
1658	}
1659
1660	static int intel_joiner_add_affected_planes(struct intel_atomic_state *state,
1661	u8 joined_pipes)
1662	{
1663	u8 prev_affected_planes, affected_planes = 0;
1664
1665	/*
1666	* We want all the joined pipes to have the same
1667	* set of planes in the atomic state, to make sure
1668	* state copying always works correctly, and the
1669	* UV<->Y plane linkage is always up to date.
1670	* Keep pulling planes in until we've determined
1671	* the full set of affected planes. A bit complicated
1672	* on account of each pipe being capable of selecting
1673	* their own Y planes independently of the other pipes,
1674	* and the selection being done from the set of
1675	* inactive planes.
1676	*/
1677	do {
1678	struct intel_crtc *crtc;
1679
1680	for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) {
1681	int ret;
1682
1683	ret = intel_crtc_add_planes_to_state(state, crtc, plane_ids_mask: affected_planes);
1684	if (ret)
1685	return ret;
1686	}
1687
1688	prev_affected_planes = affected_planes;
1689	affected_planes = intel_joiner_affected_planes(state, joined_pipes);
1690	} while (affected_planes != prev_affected_planes);
1691
1692	return 0;
1693	}
1694
1695	static int intel_add_affected_planes(struct intel_atomic_state *state)
1696	{
1697	const struct intel_crtc_state *crtc_state;
1698	struct intel_crtc *crtc;
1699	int i;
1700
1701	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1702	int ret;
1703
1704	ret = intel_joiner_add_affected_planes(state, joined_pipes: intel_crtc_joined_pipe_mask(crtc_state));
1705	if (ret)
1706	return ret;
1707	}
1708
1709	return 0;
1710	}
1711
1712	int intel_plane_atomic_check(struct intel_atomic_state *state)
1713	{
1714	struct intel_display *display = to_intel_display(state);
1715	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
1716	struct intel_plane_state __maybe_unused *plane_state;
1717	struct intel_plane *plane;
1718	struct intel_crtc *crtc;
1719	int i, ret;
1720
1721	ret = intel_add_affected_planes(state);
1722	if (ret)
1723	return ret;
1724
1725	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1726	ret = plane_atomic_check(state, plane);
1727	if (ret) {
1728	drm_dbg_atomic(display->drm,
1729	"[PLANE:%d:%s] atomic driver check failed\n",
1730	plane->base.base.id, plane->base.name);
1731	return ret;
1732	}
1733	}
1734
1735	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1736	new_crtc_state, i) {
1737	u8 old_active_planes, new_active_planes;
1738
1739	ret = icl_check_nv12_planes(state, crtc);
1740	if (ret)
1741	return ret;
1742
1743	/*
1744	* On some platforms the number of active planes affects
1745	* the planes' minimum cdclk calculation. Add such planes
1746	* to the state before we compute the minimum cdclk.
1747	*/
1748	if (!active_planes_affects_min_cdclk(display))
1749	continue;
1750
1751	old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1752	new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1753
1754	if (hweight8(old_active_planes) == hweight8(new_active_planes))
1755	continue;
1756
1757	ret = intel_crtc_add_planes_to_state(state, crtc, plane_ids_mask: new_active_planes);
1758	if (ret)
1759	return ret;
1760	}
1761
1762	for_each_new_intel_plane_in_state(state, plane, plane_state, i)
1763	intel_plane_calc_min_cdclk(state, plane);
1764
1765	return 0;
1766	}
1767