1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 *
5 * Read out the current hardware modeset state, and sanitize it to the current
6 * state.
7 */
8
9#include <drm/drm_atomic_state_helper.h>
10#include <drm/drm_atomic_uapi.h>
11#include <drm/drm_print.h>
12#include <drm/drm_vblank.h>
13
14#include "i915_reg.h"
15#include "i9xx_wm.h"
16#include "intel_atomic.h"
17#include "intel_bw.h"
18#include "intel_cmtg.h"
19#include "intel_color.h"
20#include "intel_crtc.h"
21#include "intel_crtc_state_dump.h"
22#include "intel_dbuf_bw.h"
23#include "intel_ddi.h"
24#include "intel_de.h"
25#include "intel_display.h"
26#include "intel_display_power.h"
27#include "intel_display_regs.h"
28#include "intel_display_types.h"
29#include "intel_dmc.h"
30#include "intel_fifo_underrun.h"
31#include "intel_modeset_setup.h"
32#include "intel_pch_display.h"
33#include "intel_pmdemand.h"
34#include "intel_tc.h"
35#include "intel_vblank.h"
36#include "intel_vga.h"
37#include "intel_wm.h"
38#include "skl_watermark.h"
39
40static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
41 struct drm_modeset_acquire_ctx *ctx)
42{
43 struct intel_display *display = to_intel_display(crtc);
44 struct intel_crtc_state *crtc_state =
45 to_intel_crtc_state(crtc->base.state);
46 struct intel_plane *plane;
47 struct drm_atomic_state *state;
48 struct intel_crtc *temp_crtc;
49 enum pipe pipe = crtc->pipe;
50
51 if (!crtc_state->hw.active)
52 return;
53
54 for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
55 const struct intel_plane_state *plane_state =
56 to_intel_plane_state(plane->base.state);
57
58 if (plane_state->uapi.visible)
59 intel_plane_disable_noatomic(crtc, plane);
60 }
61
62 state = drm_atomic_state_alloc(dev: display->drm);
63 if (!state) {
64 drm_dbg_kms(display->drm,
65 "failed to disable [CRTC:%d:%s], out of memory",
66 crtc->base.base.id, crtc->base.name);
67 return;
68 }
69
70 state->acquire_ctx = ctx;
71 to_intel_atomic_state(state)->internal = true;
72
73 /* Everything's already locked, -EDEADLK can't happen. */
74 for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,
75 BIT(pipe) |
76 intel_crtc_joiner_secondary_pipes(crtc_state)) {
77 struct intel_crtc_state *temp_crtc_state =
78 intel_atomic_get_crtc_state(state, crtc: temp_crtc);
79 int ret;
80
81 ret = drm_atomic_add_affected_connectors(state, crtc: &temp_crtc->base);
82
83 drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret);
84 }
85
86 display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
87
88 drm_atomic_state_put(state);
89
90 drm_dbg_kms(display->drm,
91 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
92 crtc->base.base.id, crtc->base.name);
93
94 crtc->active = false;
95 crtc->base.enabled = false;
96
97 if (crtc_state->intel_dpll)
98 intel_dpll_crtc_put(crtc,
99 pll: crtc_state->intel_dpll,
100 shared_dpll_state: &crtc_state->intel_dpll->state);
101}
102
103static void set_encoder_for_connector(struct intel_connector *connector,
104 struct intel_encoder *encoder)
105{
106 struct drm_connector_state *conn_state = connector->base.state;
107
108 if (conn_state->crtc)
109 drm_connector_put(connector: &connector->base);
110
111 if (encoder) {
112 conn_state->best_encoder = &encoder->base;
113 conn_state->crtc = encoder->base.crtc;
114 drm_connector_get(connector: &connector->base);
115 } else {
116 conn_state->best_encoder = NULL;
117 conn_state->crtc = NULL;
118 }
119}
120
121static void reset_encoder_connector_state(struct intel_encoder *encoder)
122{
123 struct intel_display *display = to_intel_display(encoder);
124 struct intel_pmdemand_state *pmdemand_state =
125 to_intel_pmdemand_state(obj_state: display->pmdemand.obj.state);
126 struct intel_connector *connector;
127 struct drm_connector_list_iter conn_iter;
128
129 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
130 for_each_intel_connector_iter(connector, &conn_iter) {
131 if (connector->base.encoder != &encoder->base)
132 continue;
133
134 /* Clear the corresponding bit in pmdemand active phys mask */
135 intel_pmdemand_update_phys_mask(display, encoder,
136 pmdemand_state, clear_bit: false);
137
138 set_encoder_for_connector(connector, NULL);
139
140 connector->base.dpms = DRM_MODE_DPMS_OFF;
141 connector->base.encoder = NULL;
142 }
143 drm_connector_list_iter_end(iter: &conn_iter);
144}
145
146static void reset_crtc_encoder_state(struct intel_crtc *crtc)
147{
148 struct intel_display *display = to_intel_display(crtc);
149 struct intel_encoder *encoder;
150
151 for_each_encoder_on_crtc(display->drm, &crtc->base, encoder) {
152 reset_encoder_connector_state(encoder);
153 encoder->base.crtc = NULL;
154 }
155}
156
157static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
158{
159 struct intel_display *display = to_intel_display(crtc);
160 struct intel_pmdemand_state *pmdemand_state =
161 to_intel_pmdemand_state(obj_state: display->pmdemand.obj.state);
162 struct intel_crtc_state *crtc_state =
163 to_intel_crtc_state(crtc->base.state);
164 enum pipe pipe = crtc->pipe;
165
166 __drm_atomic_helper_crtc_destroy_state(state: &crtc_state->uapi);
167 intel_crtc_free_hw_state(crtc_state);
168 intel_crtc_state_reset(crtc_state, crtc);
169
170 reset_crtc_encoder_state(crtc);
171
172 intel_fbc_disable(crtc);
173 intel_update_watermarks(display);
174
175 intel_display_power_put_all_in_set(display, power_domain_set: &crtc->enabled_power_domains);
176
177 intel_cdclk_crtc_disable_noatomic(crtc);
178 skl_wm_crtc_disable_noatomic(crtc);
179 intel_bw_crtc_disable_noatomic(crtc);
180 intel_dbuf_bw_crtc_disable_noatomic(crtc);
181
182 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, port_clock: 0);
183}
184
185/*
186 * Return all the pipes using a transcoder in @transcoder_mask.
187 * For joiner configs return only the joiner primary.
188 */
189static u8 get_transcoder_pipes(struct intel_display *display,
190 u8 transcoder_mask)
191{
192 struct intel_crtc *temp_crtc;
193 u8 pipes = 0;
194
195 for_each_intel_crtc(display->drm, temp_crtc) {
196 struct intel_crtc_state *temp_crtc_state =
197 to_intel_crtc_state(temp_crtc->base.state);
198
199 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
200 continue;
201
202 if (intel_crtc_is_joiner_secondary(crtc_state: temp_crtc_state))
203 continue;
204
205 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
206 pipes |= BIT(temp_crtc->pipe);
207 }
208
209 return pipes;
210}
211
212/*
213 * Return the port sync master and slave pipes linked to @crtc.
214 * For joiner configs return only the joiner primary pipes.
215 */
216static void get_portsync_pipes(struct intel_crtc *crtc,
217 u8 *master_pipe_mask, u8 *slave_pipes_mask)
218{
219 struct intel_display *display = to_intel_display(crtc);
220 struct intel_crtc_state *crtc_state =
221 to_intel_crtc_state(crtc->base.state);
222 struct intel_crtc *master_crtc;
223 struct intel_crtc_state *master_crtc_state;
224 enum transcoder master_transcoder;
225
226 if (!is_trans_port_sync_mode(state: crtc_state)) {
227 *master_pipe_mask = BIT(crtc->pipe);
228 *slave_pipes_mask = 0;
229
230 return;
231 }
232
233 if (is_trans_port_sync_master(state: crtc_state))
234 master_transcoder = crtc_state->cpu_transcoder;
235 else
236 master_transcoder = crtc_state->master_transcoder;
237
238 *master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder));
239 drm_WARN_ON(display->drm, !is_power_of_2(*master_pipe_mask));
240
241 master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);
242 master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
243 *slave_pipes_mask = get_transcoder_pipes(display, transcoder_mask: master_crtc_state->sync_mode_slaves_mask);
244}
245
246static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask)
247{
248 struct intel_crtc *primary_crtc;
249 u8 pipes = 0;
250
251 for_each_intel_crtc_in_pipe_mask(display->drm, primary_crtc, primary_pipes_mask) {
252 struct intel_crtc_state *primary_crtc_state =
253 to_intel_crtc_state(primary_crtc->base.state);
254
255 pipes |= intel_crtc_joiner_secondary_pipes(crtc_state: primary_crtc_state);
256 }
257
258 return pipes;
259}
260
261static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
262 struct drm_modeset_acquire_ctx *ctx)
263{
264 struct intel_display *display = to_intel_display(crtc);
265 struct intel_crtc *temp_crtc;
266 u8 portsync_master_mask;
267 u8 portsync_slaves_mask;
268 u8 joiner_secondaries_mask;
269
270 /* TODO: Add support for MST */
271 get_portsync_pipes(crtc, master_pipe_mask: &portsync_master_mask, slave_pipes_mask: &portsync_slaves_mask);
272 joiner_secondaries_mask = get_joiner_secondary_pipes(display,
273 primary_pipes_mask: portsync_master_mask |
274 portsync_slaves_mask);
275
276 drm_WARN_ON(display->drm,
277 portsync_master_mask & portsync_slaves_mask ||
278 portsync_master_mask & joiner_secondaries_mask ||
279 portsync_slaves_mask & joiner_secondaries_mask);
280
281 for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask)
282 intel_crtc_disable_noatomic_begin(crtc: temp_crtc, ctx);
283
284 for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_slaves_mask)
285 intel_crtc_disable_noatomic_begin(crtc: temp_crtc, ctx);
286
287 for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_master_mask)
288 intel_crtc_disable_noatomic_begin(crtc: temp_crtc, ctx);
289
290 for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,
291 joiner_secondaries_mask |
292 portsync_slaves_mask |
293 portsync_master_mask)
294 intel_crtc_disable_noatomic_complete(crtc: temp_crtc);
295}
296
297static void intel_modeset_update_connector_atomic_state(struct intel_display *display)
298{
299 struct intel_connector *connector;
300 struct drm_connector_list_iter conn_iter;
301
302 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
303 for_each_intel_connector_iter(connector, &conn_iter) {
304 struct drm_connector_state *conn_state = connector->base.state;
305 struct intel_encoder *encoder =
306 to_intel_encoder(connector->base.encoder);
307
308 set_encoder_for_connector(connector, encoder);
309
310 if (encoder) {
311 struct intel_crtc *crtc =
312 to_intel_crtc(encoder->base.crtc);
313 const struct intel_crtc_state *crtc_state =
314 to_intel_crtc_state(crtc->base.state);
315
316 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
317 }
318 }
319 drm_connector_list_iter_end(iter: &conn_iter);
320}
321
322static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
323{
324 struct intel_display *display = to_intel_display(crtc_state);
325
326 if (intel_crtc_is_joiner_secondary(crtc_state))
327 return;
328
329 crtc_state->uapi.enable = crtc_state->hw.enable;
330 crtc_state->uapi.active = crtc_state->hw.active;
331 drm_WARN_ON(crtc_state->uapi.crtc->dev,
332 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
333
334 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
335 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
336
337 if (DISPLAY_INFO(display)->color.degamma_lut_size) {
338 /* assume 1:1 mapping */
339 drm_property_replace_blob(blob: &crtc_state->hw.degamma_lut,
340 new_blob: crtc_state->pre_csc_lut);
341 drm_property_replace_blob(blob: &crtc_state->hw.gamma_lut,
342 new_blob: crtc_state->post_csc_lut);
343 } else {
344 /*
345 * ilk/snb hw may be configured for either pre_csc_lut
346 * or post_csc_lut, but we don't advertise degamma_lut as
347 * being available in the uapi since there is only one
348 * hardware LUT. Always assign the result of the readout
349 * to gamma_lut as that is the only valid source of LUTs
350 * in the uapi.
351 */
352 drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&
353 crtc_state->pre_csc_lut);
354
355 drm_property_replace_blob(blob: &crtc_state->hw.degamma_lut,
356 NULL);
357 drm_property_replace_blob(blob: &crtc_state->hw.gamma_lut,
358 new_blob: crtc_state->post_csc_lut ?:
359 crtc_state->pre_csc_lut);
360 }
361
362 drm_property_replace_blob(blob: &crtc_state->uapi.degamma_lut,
363 new_blob: crtc_state->hw.degamma_lut);
364 drm_property_replace_blob(blob: &crtc_state->uapi.gamma_lut,
365 new_blob: crtc_state->hw.gamma_lut);
366 drm_property_replace_blob(blob: &crtc_state->uapi.ctm,
367 new_blob: crtc_state->hw.ctm);
368}
369
370static void
371intel_sanitize_plane_mapping(struct intel_display *display)
372{
373 struct intel_crtc *crtc;
374
375 if (DISPLAY_VER(display) >= 4)
376 return;
377
378 for_each_intel_crtc(display->drm, crtc) {
379 struct intel_plane *plane =
380 to_intel_plane(crtc->base.primary);
381 struct intel_crtc *plane_crtc;
382 enum pipe pipe;
383
384 if (!plane->get_hw_state(plane, &pipe))
385 continue;
386
387 if (pipe == crtc->pipe)
388 continue;
389
390 drm_dbg_kms(display->drm,
391 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
392 plane->base.base.id, plane->base.name);
393
394 plane_crtc = intel_crtc_for_pipe(display, pipe);
395 intel_plane_disable_noatomic(crtc: plane_crtc, plane);
396 }
397}
398
399static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
400{
401 struct drm_device *dev = crtc->base.dev;
402 struct intel_encoder *encoder;
403
404 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
405 return true;
406
407 return false;
408}
409
410static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
411{
412 struct drm_device *dev = crtc->base.dev;
413 struct intel_encoder *encoder;
414
415 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
416 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
417
418 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
419 return true;
420 }
421
422 return false;
423}
424
425static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
426{
427 struct intel_display *display = to_intel_display(encoder);
428 struct drm_connector_list_iter conn_iter;
429 struct intel_connector *connector;
430 struct intel_connector *found_connector = NULL;
431
432 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
433 for_each_intel_connector_iter(connector, &conn_iter) {
434 if (&encoder->base == connector->base.encoder) {
435 found_connector = connector;
436 break;
437 }
438 }
439 drm_connector_list_iter_end(iter: &conn_iter);
440
441 return found_connector;
442}
443
444static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
445{
446 struct intel_display *display = to_intel_display(crtc_state);
447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
448
449 /*
450 * We start out with underrun reporting disabled on active
451 * pipes to avoid races.
452 *
453 * Also on gmch platforms we dont have any hardware bits to
454 * disable the underrun reporting. Which means we need to start
455 * out with underrun reporting disabled also on inactive pipes,
456 * since otherwise we'll complain about the garbage we read when
457 * e.g. coming up after runtime pm.
458 *
459 * No protection against concurrent access is required - at
460 * worst a fifo underrun happens which also sets this to false.
461 */
462 intel_init_fifo_underrun_reporting(display, crtc,
463 enable: !crtc_state->hw.active &&
464 !HAS_GMCH(display));
465}
466
467static bool intel_sanitize_crtc(struct intel_crtc *crtc,
468 struct drm_modeset_acquire_ctx *ctx)
469{
470 struct intel_display *display = to_intel_display(crtc);
471 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
472 bool needs_link_reset;
473
474 if (crtc_state->hw.active) {
475 struct intel_plane *plane;
476
477 /* Disable everything but the primary plane */
478 for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
479 const struct intel_plane_state *plane_state =
480 to_intel_plane_state(plane->base.state);
481
482 if (plane_state->uapi.visible &&
483 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
484 intel_plane_disable_noatomic(crtc, plane);
485 }
486
487 /* Disable any background color/etc. set by the BIOS */
488 intel_color_commit_noarm(NULL, crtc_state);
489 intel_color_commit_arm(NULL, crtc_state);
490 }
491
492 if (!crtc_state->hw.active ||
493 intel_crtc_is_joiner_secondary(crtc_state))
494 return false;
495
496 needs_link_reset = intel_crtc_needs_link_reset(crtc);
497
498 /*
499 * Adjust the state of the output pipe according to whether we have
500 * active connectors/encoders.
501 */
502 if (!needs_link_reset && intel_crtc_has_encoders(crtc))
503 return false;
504
505 intel_crtc_disable_noatomic(crtc, ctx);
506
507 /*
508 * The HPD state on other active/disconnected TC ports may be stuck in
509 * the connected state until this port is disabled and a ~10ms delay has
510 * passed, wait here for that so that sanitizing other CRTCs will see the
511 * up-to-date HPD state.
512 */
513 if (needs_link_reset)
514 msleep(msecs: 20);
515
516 return true;
517}
518
519static void intel_sanitize_all_crtcs(struct intel_display *display,
520 struct drm_modeset_acquire_ctx *ctx)
521{
522 struct intel_crtc *crtc;
523 u32 crtcs_forced_off = 0;
524
525 /*
526 * An active and disconnected TypeC port prevents the HPD live state
527 * to get updated on other active/disconnected TypeC ports, so after
528 * a port gets disabled the CRTCs using other TypeC ports must be
529 * rechecked wrt. their link status.
530 */
531 for (;;) {
532 u32 old_mask = crtcs_forced_off;
533
534 for_each_intel_crtc(display->drm, crtc) {
535 u32 crtc_mask = drm_crtc_mask(crtc: &crtc->base);
536
537 if (crtcs_forced_off & crtc_mask)
538 continue;
539
540 if (intel_sanitize_crtc(crtc, ctx))
541 crtcs_forced_off |= crtc_mask;
542 }
543 if (crtcs_forced_off == old_mask)
544 break;
545 }
546
547 for_each_intel_crtc(display->drm, crtc) {
548 struct intel_crtc_state *crtc_state =
549 to_intel_crtc_state(crtc->base.state);
550
551 intel_crtc_state_dump(crtc_state, NULL, context: "setup_hw_state");
552 }
553}
554
555static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
556{
557 struct intel_display *display = to_intel_display(crtc_state);
558
559 /*
560 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
561 * the hardware when a high res displays plugged in. DPLL P
562 * divider is zero, and the pipe timings are bonkers. We'll
563 * try to disable everything in that case.
564 *
565 * FIXME would be nice to be able to sanitize this state
566 * without several WARNs, but for now let's take the easy
567 * road.
568 */
569 return display->platform.sandybridge &&
570 crtc_state->hw.active &&
571 crtc_state->intel_dpll &&
572 crtc_state->port_clock == 0;
573}
574
575static void intel_sanitize_encoder(struct intel_encoder *encoder)
576{
577 struct intel_display *display = to_intel_display(encoder);
578 struct intel_connector *connector;
579 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
580 struct intel_crtc_state *crtc_state = crtc ?
581 to_intel_crtc_state(crtc->base.state) : NULL;
582 struct intel_pmdemand_state *pmdemand_state =
583 to_intel_pmdemand_state(obj_state: display->pmdemand.obj.state);
584
585 /*
586 * We need to check both for a crtc link (meaning that the encoder is
587 * active and trying to read from a pipe) and the pipe itself being
588 * active.
589 */
590 bool has_active_crtc = crtc_state &&
591 crtc_state->hw.active;
592
593 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
594 drm_dbg_kms(display->drm,
595 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
596 pipe_name(crtc->pipe));
597 has_active_crtc = false;
598 }
599
600 connector = intel_encoder_find_connector(encoder);
601 if (connector && !has_active_crtc) {
602 drm_dbg_kms(display->drm,
603 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
604 encoder->base.base.id,
605 encoder->base.name);
606
607 /* Clear the corresponding bit in pmdemand active phys mask */
608 intel_pmdemand_update_phys_mask(display, encoder,
609 pmdemand_state, clear_bit: false);
610
611 /*
612 * Connector is active, but has no active pipe. This is fallout
613 * from our resume register restoring. Disable the encoder
614 * manually again.
615 */
616 if (crtc_state) {
617 struct drm_encoder *best_encoder;
618
619 drm_dbg_kms(display->drm,
620 "[ENCODER:%d:%s] manually disabled\n",
621 encoder->base.base.id,
622 encoder->base.name);
623
624 /* avoid oopsing in case the hooks consult best_encoder */
625 best_encoder = connector->base.state->best_encoder;
626 connector->base.state->best_encoder = &encoder->base;
627
628 /* FIXME NULL atomic state passed! */
629 if (encoder->disable)
630 encoder->disable(NULL, encoder, crtc_state,
631 connector->base.state);
632 if (encoder->post_disable)
633 encoder->post_disable(NULL, encoder, crtc_state,
634 connector->base.state);
635
636 connector->base.state->best_encoder = best_encoder;
637 }
638 encoder->base.crtc = NULL;
639
640 /*
641 * Inconsistent output/port/pipe state happens presumably due to
642 * a bug in one of the get_hw_state functions. Or someplace else
643 * in our code, like the register restore mess on resume. Clamp
644 * things to off as a safer default.
645 */
646 connector->base.dpms = DRM_MODE_DPMS_OFF;
647 connector->base.encoder = NULL;
648 }
649
650 /* notify opregion of the sanitized encoder state */
651 intel_opregion_notify_encoder(encoder, enable: connector && has_active_crtc);
652
653 if (HAS_DDI(display))
654 intel_ddi_sanitize_encoder_pll_mapping(encoder);
655}
656
657/* FIXME read out full plane state for all planes */
658static void readout_plane_state(struct intel_display *display)
659{
660 struct intel_plane *plane;
661 struct intel_crtc *crtc;
662
663 for_each_intel_plane(display->drm, plane) {
664 struct intel_plane_state *plane_state =
665 to_intel_plane_state(plane->base.state);
666 struct intel_crtc_state *crtc_state;
667 enum pipe pipe = PIPE_A;
668 bool visible;
669
670 visible = plane->get_hw_state(plane, &pipe);
671
672 crtc = intel_crtc_for_pipe(display, pipe);
673 crtc_state = to_intel_crtc_state(crtc->base.state);
674
675 intel_set_plane_visible(crtc_state, plane_state, visible);
676
677 drm_dbg_kms(display->drm,
678 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
679 plane->base.base.id, plane->base.name,
680 str_enabled_disabled(visible), pipe_name(pipe));
681 }
682
683 for_each_intel_crtc(display->drm, crtc) {
684 struct intel_crtc_state *crtc_state =
685 to_intel_crtc_state(crtc->base.state);
686
687 intel_plane_fixup_bitmasks(crtc_state);
688 }
689}
690
691static void intel_modeset_readout_hw_state(struct intel_display *display)
692{
693 struct intel_pmdemand_state *pmdemand_state =
694 to_intel_pmdemand_state(obj_state: display->pmdemand.obj.state);
695 enum pipe pipe;
696 struct intel_crtc *crtc;
697 struct intel_encoder *encoder;
698 struct intel_connector *connector;
699 struct drm_connector_list_iter conn_iter;
700
701 for_each_intel_crtc(display->drm, crtc) {
702 struct intel_crtc_state *crtc_state =
703 to_intel_crtc_state(crtc->base.state);
704
705 __drm_atomic_helper_crtc_destroy_state(state: &crtc_state->uapi);
706 intel_crtc_free_hw_state(crtc_state);
707 intel_crtc_state_reset(crtc_state, crtc);
708
709 intel_crtc_get_pipe_config(crtc_state);
710
711 crtc_state->hw.enable = crtc_state->hw.active;
712
713 crtc->base.enabled = crtc_state->hw.enable;
714 crtc->active = crtc_state->hw.active;
715
716 drm_dbg_kms(display->drm,
717 "[CRTC:%d:%s] hw state readout: %s\n",
718 crtc->base.base.id, crtc->base.name,
719 str_enabled_disabled(crtc_state->hw.active));
720 }
721
722 readout_plane_state(display);
723
724 for_each_intel_encoder(display->drm, encoder) {
725 struct intel_crtc_state *crtc_state = NULL;
726
727 pipe = 0;
728
729 if (encoder->get_hw_state(encoder, &pipe)) {
730 crtc = intel_crtc_for_pipe(display, pipe);
731 crtc_state = to_intel_crtc_state(crtc->base.state);
732
733 encoder->base.crtc = &crtc->base;
734 intel_encoder_get_config(encoder, crtc_state);
735
736 /* read out to secondary crtc as well for joiner */
737 if (crtc_state->joiner_pipes) {
738 struct intel_crtc *secondary_crtc;
739
740 /* encoder should read be linked to joiner primary */
741 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
742
743 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
744 intel_crtc_joiner_secondary_pipes(crtc_state)) {
745 struct intel_crtc_state *secondary_crtc_state;
746
747 secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state);
748 intel_encoder_get_config(encoder, crtc_state: secondary_crtc_state);
749 }
750 }
751
752 intel_pmdemand_update_phys_mask(display, encoder,
753 pmdemand_state,
754 clear_bit: true);
755 } else {
756 intel_pmdemand_update_phys_mask(display, encoder,
757 pmdemand_state,
758 clear_bit: false);
759
760 encoder->base.crtc = NULL;
761 }
762
763 if (encoder->sync_state)
764 encoder->sync_state(encoder, crtc_state);
765
766 drm_dbg_kms(display->drm,
767 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
768 encoder->base.base.id, encoder->base.name,
769 str_enabled_disabled(encoder->base.crtc),
770 pipe_name(pipe));
771 }
772
773 intel_dpll_readout_hw_state(display);
774
775 drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
776 for_each_intel_connector_iter(connector, &conn_iter) {
777 struct intel_crtc_state *crtc_state = NULL;
778
779 if (connector->get_hw_state(connector)) {
780 struct intel_crtc *crtc;
781
782 connector->base.dpms = DRM_MODE_DPMS_ON;
783
784 encoder = intel_attached_encoder(connector);
785 connector->base.encoder = &encoder->base;
786
787 crtc = to_intel_crtc(encoder->base.crtc);
788 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
789
790 if (crtc_state && crtc_state->hw.active) {
791 /*
792 * This has to be done during hardware readout
793 * because anything calling .crtc_disable may
794 * rely on the connector_mask being accurate.
795 */
796 crtc_state->uapi.connector_mask |=
797 drm_connector_mask(connector: &connector->base);
798 crtc_state->uapi.encoder_mask |=
799 drm_encoder_mask(encoder: &encoder->base);
800 }
801 } else {
802 connector->base.dpms = DRM_MODE_DPMS_OFF;
803 connector->base.encoder = NULL;
804 }
805
806 if (connector->sync_state)
807 connector->sync_state(connector, crtc_state);
808
809 drm_dbg_kms(display->drm,
810 "[CONNECTOR:%d:%s] hw state readout: %s\n",
811 connector->base.base.id, connector->base.name,
812 str_enabled_disabled(connector->base.encoder));
813 }
814 drm_connector_list_iter_end(iter: &conn_iter);
815
816 for_each_intel_crtc(display->drm, crtc) {
817 struct intel_crtc_state *crtc_state =
818 to_intel_crtc_state(crtc->base.state);
819 struct intel_plane *plane;
820
821 /*
822 * The initial mode needs to be set in order to keep
823 * the atomic core happy. It wants a valid mode if the
824 * crtc's enabled, so we do the above call.
825 *
826 * But we don't set all the derived state fully, hence
827 * set a flag to indicate that a full recalculation is
828 * needed on the next commit.
829 */
830 crtc_state->inherited = true;
831
832 if (crtc_state->hw.active) {
833 intel_crtc_update_active_timings(crtc_state,
834 vrr_enable: crtc_state->vrr.enable);
835
836 intel_crtc_copy_hw_to_uapi_state(crtc_state);
837 }
838
839 for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
840 const struct intel_plane_state *plane_state =
841 to_intel_plane_state(plane->base.state);
842
843 /*
844 * FIXME don't have the fb yet, so can't
845 * use intel_plane_data_rate() :(
846 */
847 if (plane_state->uapi.visible)
848 crtc_state->data_rate[plane->id] =
849 4 * crtc_state->pixel_rate;
850 /*
851 * FIXME don't have the fb yet, so can't
852 * use plane->min_cdclk() :(
853 */
854 if (plane_state->uapi.visible && plane->min_cdclk) {
855 if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
856 crtc_state->plane_min_cdclk[plane->id] =
857 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
858 else
859 crtc_state->plane_min_cdclk[plane->id] =
860 crtc_state->pixel_rate;
861 }
862 drm_dbg_kms(display->drm,
863 "[PLANE:%d:%s] min_cdclk %d kHz\n",
864 plane->base.base.id, plane->base.name,
865 crtc_state->plane_min_cdclk[plane->id]);
866 }
867
868 crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state);
869
870 drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",
871 crtc->base.base.id, crtc->base.name, crtc_state->min_cdclk);
872
873 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
874 port_clock: crtc_state->port_clock);
875 }
876
877 /* TODO move here (or even earlier?) on all platforms */
878 if (DISPLAY_VER(display) >= 9)
879 intel_wm_get_hw_state(display);
880
881 intel_bw_update_hw_state(display);
882 intel_dbuf_bw_update_hw_state(display);
883 intel_cdclk_update_hw_state(display);
884
885 intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
886}
887
888static void
889get_encoder_power_domains(struct intel_display *display)
890{
891 struct intel_encoder *encoder;
892
893 for_each_intel_encoder(display->drm, encoder) {
894 struct intel_crtc_state *crtc_state;
895
896 if (!encoder->get_power_domains)
897 continue;
898
899 /*
900 * MST-primary and inactive encoders don't have a crtc state
901 * and neither of these require any power domain references.
902 */
903 if (!encoder->base.crtc)
904 continue;
905
906 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
907 encoder->get_power_domains(encoder, crtc_state);
908 }
909}
910
911static void intel_early_display_was(struct intel_display *display)
912{
913 /*
914 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
915 * Also known as Wa_14010480278.
916 */
917 if (IS_DISPLAY_VER(display, 10, 12))
918 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, clear: 0, DARBF_GATING_DIS);
919
920 /*
921 * WaRsPkgCStateDisplayPMReq:hsw
922 * System hang if this isn't done before disabling all planes!
923 */
924 if (display->platform.haswell)
925 intel_de_rmw(display, CHICKEN_PAR1_1, clear: 0, FORCE_ARB_IDLE_PLANES);
926
927 if (display->platform.kabylake || display->platform.coffeelake ||
928 display->platform.cometlake) {
929 /* Display WA #1142:kbl,cfl,cml */
930 intel_de_rmw(display, CHICKEN_PAR1_1,
931 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
932 intel_de_rmw(display, CHICKEN_MISC_2,
933 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
934 KBL_ARB_FILL_SPARE_14);
935 }
936}
937
938void intel_modeset_setup_hw_state(struct intel_display *display,
939 struct drm_modeset_acquire_ctx *ctx)
940{
941 struct intel_encoder *encoder;
942 struct intel_crtc *crtc;
943 intel_wakeref_t wakeref;
944
945 wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_INIT);
946
947 intel_early_display_was(display);
948 intel_vga_disable(display);
949
950 intel_modeset_readout_hw_state(display);
951
952 /* HW state is read out, now we need to sanitize this mess. */
953 get_encoder_power_domains(display);
954
955 intel_pch_sanitize(display);
956
957 intel_cmtg_sanitize(display);
958
959 /*
960 * intel_sanitize_plane_mapping() may need to do vblank
961 * waits, so we need vblank interrupts restored beforehand.
962 */
963 for_each_intel_crtc(display->drm, crtc) {
964 struct intel_crtc_state *crtc_state =
965 to_intel_crtc_state(crtc->base.state);
966
967 intel_sanitize_fifo_underrun_reporting(crtc_state);
968
969 drm_crtc_vblank_reset(crtc: &crtc->base);
970
971 if (crtc_state->hw.active) {
972 intel_dmc_enable_pipe(crtc_state);
973 intel_crtc_vblank_on(crtc_state);
974 }
975 }
976
977 intel_fbc_sanitize(display);
978
979 intel_sanitize_plane_mapping(display);
980
981 for_each_intel_encoder(display->drm, encoder)
982 intel_sanitize_encoder(encoder);
983
984 /*
985 * Sanitizing CRTCs needs their connector atomic state to be
986 * up-to-date, so ensure that already here.
987 */
988 intel_modeset_update_connector_atomic_state(display);
989
990 intel_sanitize_all_crtcs(display, ctx);
991
992 intel_dpll_sanitize_state(display);
993
994 /* TODO move earlier on all platforms */
995 if (DISPLAY_VER(display) < 9)
996 intel_wm_get_hw_state(display);
997 intel_wm_sanitize(display);
998
999 for_each_intel_crtc(display->drm, crtc) {
1000 struct intel_crtc_state *crtc_state =
1001 to_intel_crtc_state(crtc->base.state);
1002 struct intel_power_domain_mask put_domains;
1003
1004 intel_modeset_get_crtc_power_domains(crtc_state, old_domains: &put_domains);
1005 if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
1006 intel_modeset_put_crtc_power_domains(crtc, domains: &put_domains);
1007 }
1008
1009 intel_display_power_put(display, domain: POWER_DOMAIN_INIT, wakeref);
1010
1011 intel_power_domains_sanitize_state(display);
1012}
1013

source code of linux/drivers/gpu/drm/i915/display/intel_modeset_setup.c