| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright © 2023 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <drm/drm_print.h> |
| 7 | |
| 8 | #include "i915_reg.h" |
| 9 | #include "intel_de.h" |
| 10 | #include "intel_display_core.h" |
| 11 | #include "intel_display_regs.h" |
| 12 | #include "intel_display_wa.h" |
| 13 | |
| 14 | static void gen11_display_wa_apply(struct intel_display *display) |
| 15 | { |
| 16 | /* Wa_14010594013 */ |
| 17 | intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, clear: 0, ICL_DELAY_PMRSP); |
| 18 | } |
| 19 | |
| 20 | static void xe_d_display_wa_apply(struct intel_display *display) |
| 21 | { |
| 22 | /* Wa_14013723622 */ |
| 23 | intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, set: 0); |
| 24 | } |
| 25 | |
| 26 | static void adlp_display_wa_apply(struct intel_display *display) |
| 27 | { |
| 28 | /* Wa_22011091694:adlp */ |
| 29 | intel_de_rmw(display, GEN9_CLKGATE_DIS_5, clear: 0, DPCE_GATING_DIS); |
| 30 | |
| 31 | /* Bspec/49189 Initialize Sequence */ |
| 32 | intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, set: 0); |
| 33 | } |
| 34 | |
| 35 | void intel_display_wa_apply(struct intel_display *display) |
| 36 | { |
| 37 | if (display->platform.alderlake_p) |
| 38 | adlp_display_wa_apply(display); |
| 39 | else if (DISPLAY_VER(display) == 12) |
| 40 | xe_d_display_wa_apply(display); |
| 41 | else if (DISPLAY_VER(display) == 11) |
| 42 | gen11_display_wa_apply(display); |
| 43 | } |
| 44 | |
| 45 | /* |
| 46 | * Wa_16025573575: |
| 47 | * Fixes: Issue with bitbashing on Xe3 based platforms. |
| 48 | * Workaround: Set masks bits in GPIO CTL and preserve it during bitbashing sequence. |
| 49 | */ |
| 50 | static bool intel_display_needs_wa_16025573575(struct intel_display *display) |
| 51 | { |
| 52 | return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 || |
| 53 | DISPLAY_VERx100(display) == 3500; |
| 54 | } |
| 55 | |
| 56 | /* |
| 57 | * Wa_14011503117: |
| 58 | * Fixes: Before enabling the scaler DE fatal error is masked |
| 59 | * Workaround: Unmask the DE fatal error register after enabling the scaler |
| 60 | * and after waiting of at least 1 frame. |
| 61 | */ |
| 62 | bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name) |
| 63 | { |
| 64 | switch (wa) { |
| 65 | case INTEL_DISPLAY_WA_16023588340: |
| 66 | return intel_display_needs_wa_16023588340(display); |
| 67 | case INTEL_DISPLAY_WA_16025573575: |
| 68 | return intel_display_needs_wa_16025573575(display); |
| 69 | case INTEL_DISPLAY_WA_14011503117: |
| 70 | return DISPLAY_VER(display) == 13; |
| 71 | case INTEL_DISPLAY_WA_22014263786: |
| 72 | return IS_DISPLAY_VERx100(display, 1100, 1400); |
| 73 | default: |
| 74 | drm_WARN(display->drm, 1, "Missing Wa number: %s\n" , name); |
| 75 | break; |
| 76 | } |
| 77 | |
| 78 | return false; |
| 79 | } |
| 80 | |