1// SPDX-License-Identifier: MIT
2/* Copyright © 2025 Intel Corporation */
3
4#include <drm/drm_print.h>
5
6#include "i915_reg.h"
7#include "intel_casf.h"
8#include "intel_casf_regs.h"
9#include "intel_de.h"
10#include "intel_display_regs.h"
11#include "intel_display_types.h"
12#include "skl_scaler.h"
13
14#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080)
15#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160)
16
17#define FILTER_COEFF_0_125 125
18#define FILTER_COEFF_0_25 250
19#define FILTER_COEFF_0_5 500
20#define FILTER_COEFF_1_0 1000
21#define FILTER_COEFF_0_0 0
22#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN))
23
24/**
25 * DOC: Content Adaptive Sharpness Filter (CASF)
26 *
27 * Starting from LNL the display engine supports an
28 * adaptive sharpening filter, enhancing the image
29 * quality. The display hardware utilizes the second
30 * pipe scaler for implementing CASF.
31 * If sharpness is being enabled then pipe scaling
32 * cannot be used.
33 * This filter operates on a region of pixels based
34 * on the tap size. Coefficients are used to generate
35 * an alpha value which blends the sharpened image to
36 * original image.
37 */
38
39/* Default LUT values to be loaded one time. */
40static const u16 sharpness_lut[] = {
41 4095, 2047, 1364, 1022, 816, 678, 579,
42 504, 444, 397, 357, 323, 293, 268, 244, 224,
43 204, 187, 170, 154, 139, 125, 111, 98, 85,
44 73, 60, 48, 36, 24, 12, 0
45};
46
47const u16 filtercoeff_1[] = {
48 FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5,
49 FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0,
50 FILTER_COEFF_0_0,
51};
52
53const u16 filtercoeff_2[] = {
54 FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
55 FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
56 FILTER_COEFF_0_0,
57};
58
59const u16 filtercoeff_3[] = {
60 FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5,
61 FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25,
62 FILTER_COEFF_0_125,
63};
64
65static void intel_casf_filter_lut_load(struct intel_crtc *crtc,
66 const struct intel_crtc_state *crtc_state)
67{
68 struct intel_display *display = to_intel_display(crtc_state);
69 int i;
70
71 intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
72 INDEX_AUTO_INCR | INDEX_VALUE(0));
73
74 for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
75 intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
76 val: sharpness_lut[i]);
77}
78
79void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
80{
81 struct intel_display *display = to_intel_display(crtc_state);
82 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
83 int win_size;
84
85 intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK,
86 FILTER_STRENGTH(crtc_state->hw.casf_params.strength));
87
88 win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));
89
90 intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, 1), val: win_size);
91}
92
93static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state)
94{
95 const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
96 u32 total_pixels = mode->hdisplay * mode->vdisplay;
97
98 if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER)
99 crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3;
100 else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER)
101 crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5;
102 else
103 crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7;
104}
105
106int intel_casf_compute_config(struct intel_crtc_state *crtc_state)
107{
108 struct intel_display *display = to_intel_display(crtc_state);
109
110 if (!HAS_CASF(display))
111 return 0;
112
113 if (crtc_state->uapi.sharpness_strength == 0) {
114 crtc_state->hw.casf_params.casf_enable = false;
115 crtc_state->hw.casf_params.strength = 0;
116 return 0;
117 }
118
119 crtc_state->hw.casf_params.casf_enable = true;
120
121 /*
122 * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
123 * Strength is from 0.0-14.9375 ie from 0-239.
124 * User can give value from 0-255 but is clamped to 239.
125 * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
126 * 6.3125 in 4.4 format is b01100101 which is equal to 101.
127 * Also 85 + 16 = 101.
128 */
129 crtc_state->hw.casf_params.strength =
130 min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
131
132 intel_casf_compute_win_size(crtc_state);
133
134 intel_casf_scaler_compute_config(crtc_state);
135
136 return 0;
137}
138
139void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state)
140{
141 struct intel_display *display = to_intel_display(crtc_state);
142 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
143 u32 sharp;
144
145 sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));
146 if (sharp & FILTER_EN) {
147 if (drm_WARN_ON(display->drm,
148 REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16))
149 crtc_state->hw.casf_params.strength = 0;
150 else
151 crtc_state->hw.casf_params.strength =
152 REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp);
153 crtc_state->hw.casf_params.casf_enable = true;
154 crtc_state->hw.casf_params.win_size =
155 REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
156 }
157}
158
159bool intel_casf_needs_scaler(const struct intel_crtc_state *crtc_state)
160{
161 if (crtc_state->hw.casf_params.casf_enable)
162 return true;
163
164 return false;
165}
166
167static int casf_coeff_tap(int i)
168{
169 return i % SCALER_FILTER_NUM_TAPS;
170}
171
172static u32 casf_coeff(struct intel_crtc_state *crtc_state, int t)
173{
174 struct scaler_filter_coeff value;
175 u32 coeff;
176
177 value = crtc_state->hw.casf_params.coeff[t];
178 value.sign = 0;
179
180 coeff = value.sign << 15 | value.exp << 12 | value.mantissa << 3;
181 return coeff;
182}
183
184/*
185 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
186 * To enable casf: program scaler coefficients with the coeffients
187 * that are calculated and stored in hw.casf_params.coeff as per
188 * SCALER_COEFFICIENT_FORMAT
189 */
190static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state)
191{
192 struct intel_display *display = to_intel_display(crtc_state);
193 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
194 int id = crtc_state->scaler_state.scaler_id;
195 int i;
196
197 if (id != 1) {
198 drm_WARN(display->drm, 0, "Second scaler not enabled\n");
199 return;
200 }
201
202 intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
203 PS_COEF_INDEX_AUTO_INC);
204
205 for (i = 0; i < 17 * SCALER_FILTER_NUM_TAPS; i += 2) {
206 u32 tmp;
207 int t;
208
209 t = casf_coeff_tap(i);
210 tmp = casf_coeff(crtc_state, t);
211
212 t = casf_coeff_tap(i: i + 1);
213 tmp |= casf_coeff(crtc_state, t) << 16;
214
215 intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),
216 val: tmp);
217 }
218}
219
220static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
221 u16 coefficient)
222{
223 if (coefficient < 25) {
224 coeff->mantissa = (coefficient * 2048) / 100;
225 coeff->exp = 3;
226 } else if (coefficient < 50) {
227 coeff->mantissa = (coefficient * 1024) / 100;
228 coeff->exp = 2;
229 } else if (coefficient < 100) {
230 coeff->mantissa = (coefficient * 512) / 100;
231 coeff->exp = 1;
232 } else {
233 coeff->mantissa = (coefficient * 256) / 100;
234 coeff->exp = 0;
235 }
236}
237
238void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state)
239{
240 const u16 *filtercoeff;
241 u16 filter_coeff[SCALER_FILTER_NUM_TAPS];
242 u16 sumcoeff = 0;
243 int i;
244
245 if (crtc_state->hw.casf_params.win_size == 0)
246 filtercoeff = filtercoeff_1;
247 else if (crtc_state->hw.casf_params.win_size == 1)
248 filtercoeff = filtercoeff_2;
249 else
250 filtercoeff = filtercoeff_3;
251
252 for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++)
253 sumcoeff += *(filtercoeff + i);
254
255 for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) {
256 filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff);
257 convert_sharpness_coef_binary(coeff: &crtc_state->hw.casf_params.coeff[i],
258 coefficient: filter_coeff[i]);
259 }
260}
261
262void intel_casf_enable(struct intel_crtc_state *crtc_state)
263{
264 struct intel_display *display = to_intel_display(crtc_state);
265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
266 u32 sharpness_ctl;
267
268 intel_casf_filter_lut_load(crtc, crtc_state);
269
270 intel_casf_write_coeff(crtc_state);
271
272 sharpness_ctl = FILTER_EN | FILTER_STRENGTH(crtc_state->hw.casf_params.strength);
273
274 sharpness_ctl |= crtc_state->hw.casf_params.win_size;
275
276 intel_de_write(display, SHARPNESS_CTL(crtc->pipe), val: sharpness_ctl);
277
278 skl_scaler_setup_casf(crtc_state);
279}
280
281void intel_casf_disable(const struct intel_crtc_state *crtc_state)
282{
283 struct intel_display *display = to_intel_display(crtc_state);
284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
285
286 intel_de_write(display, SKL_PS_CTRL(crtc->pipe, 1), val: 0);
287 intel_de_write(display, SKL_PS_WIN_POS(crtc->pipe, 1), val: 0);
288 intel_de_write(display, SHARPNESS_CTL(crtc->pipe), val: 0);
289 intel_de_write(display, SKL_PS_WIN_SZ(crtc->pipe, 1), val: 0);
290}
291

source code of linux/drivers/gpu/drm/i915/display/intel_casf.c