1/*
2 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/export.h>
25#include <linux/i2c.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28
29#include <drm/display/drm_scdc_helper.h>
30#include <drm/drm_connector.h>
31#include <drm/drm_device.h>
32#include <drm/drm_print.h>
33
34/**
35 * DOC: scdc helpers
36 *
37 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
38 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
39 * HDMI source and HDMI sink to exchange data. The same I2C interface that
40 * is used to access EDID serves as the transport mechanism for SCDC.
41 *
42 * Note: The SCDC status is going to be lost when the display is
43 * disconnected. This can happen physically when the user disconnects
44 * the cable, but also when a display is switched on (such as waking up
45 * a TV).
46 *
47 * This is further complicated by the fact that, upon a disconnection /
48 * reconnection, KMS won't change the mode on its own. This means that
49 * one can't just rely on setting the SCDC status on enable, but also
50 * has to track the connector status changes using interrupts and
51 * restore the SCDC status. The typical solution for this is to trigger an
52 * empty modeset in drm_connector_helper_funcs.detect_ctx(), like what vc4 does
53 * in vc4_hdmi_reset_link().
54 */
55
56#define SCDC_I2C_SLAVE_ADDRESS 0x54
57
58/**
59 * drm_scdc_read - read a block of data from SCDC
60 * @adapter: I2C controller
61 * @offset: start offset of block to read
62 * @buffer: return location for the block to read
63 * @size: size of the block to read
64 *
65 * Reads a block of data from SCDC, starting at a given offset.
66 *
67 * Returns:
68 * 0 on success, negative error code on failure.
69 */
70ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
71 size_t size)
72{
73 int ret;
74 struct i2c_msg msgs[2] = {
75 {
76 .addr = SCDC_I2C_SLAVE_ADDRESS,
77 .flags = 0,
78 .len = 1,
79 .buf = &offset,
80 }, {
81 .addr = SCDC_I2C_SLAVE_ADDRESS,
82 .flags = I2C_M_RD,
83 .len = size,
84 .buf = buffer,
85 }
86 };
87
88 ret = i2c_transfer(adap: adapter, msgs, ARRAY_SIZE(msgs));
89 if (ret < 0)
90 return ret;
91 if (ret != ARRAY_SIZE(msgs))
92 return -EPROTO;
93
94 return 0;
95}
96EXPORT_SYMBOL(drm_scdc_read);
97
98/**
99 * drm_scdc_write - write a block of data to SCDC
100 * @adapter: I2C controller
101 * @offset: start offset of block to write
102 * @buffer: block of data to write
103 * @size: size of the block to write
104 *
105 * Writes a block of data to SCDC, starting at a given offset.
106 *
107 * Returns:
108 * 0 on success, negative error code on failure.
109 */
110ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
111 const void *buffer, size_t size)
112{
113 struct i2c_msg msg = {
114 .addr = SCDC_I2C_SLAVE_ADDRESS,
115 .flags = 0,
116 .len = 1 + size,
117 .buf = NULL,
118 };
119 void *data;
120 int err;
121
122 data = kmalloc(1 + size, GFP_KERNEL);
123 if (!data)
124 return -ENOMEM;
125
126 msg.buf = data;
127
128 memcpy(data, &offset, sizeof(offset));
129 memcpy(data + 1, buffer, size);
130
131 err = i2c_transfer(adap: adapter, msgs: &msg, num: 1);
132
133 kfree(objp: data);
134
135 if (err < 0)
136 return err;
137 if (err != 1)
138 return -EPROTO;
139
140 return 0;
141}
142EXPORT_SYMBOL(drm_scdc_write);
143
144/**
145 * drm_scdc_get_scrambling_status - what is status of scrambling?
146 * @connector: connector
147 *
148 * Reads the scrambler status over SCDC, and checks the
149 * scrambling status.
150 *
151 * Returns:
152 * True if the scrambling is enabled, false otherwise.
153 */
154bool drm_scdc_get_scrambling_status(struct drm_connector *connector)
155{
156 u8 status;
157 int ret;
158
159 ret = drm_scdc_readb(adapter: connector->ddc, SCDC_SCRAMBLER_STATUS, value: &status);
160 if (ret < 0) {
161 drm_dbg_kms(connector->dev,
162 "[CONNECTOR:%d:%s] Failed to read scrambling status: %d\n",
163 connector->base.id, connector->name, ret);
164 return false;
165 }
166
167 return status & SCDC_SCRAMBLING_STATUS;
168}
169EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
170
171/**
172 * drm_scdc_set_scrambling - enable scrambling
173 * @connector: connector
174 * @enable: bool to indicate if scrambling is to be enabled/disabled
175 *
176 * Writes the TMDS config register over SCDC channel, and:
177 * enables scrambling when enable = 1
178 * disables scrambling when enable = 0
179 *
180 * Returns:
181 * True if scrambling is set/reset successfully, false otherwise.
182 */
183bool drm_scdc_set_scrambling(struct drm_connector *connector,
184 bool enable)
185{
186 u8 config;
187 int ret;
188
189 ret = drm_scdc_readb(adapter: connector->ddc, SCDC_TMDS_CONFIG, value: &config);
190 if (ret < 0) {
191 drm_dbg_kms(connector->dev,
192 "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
193 connector->base.id, connector->name, ret);
194 return false;
195 }
196
197 if (enable)
198 config |= SCDC_SCRAMBLING_ENABLE;
199 else
200 config &= ~SCDC_SCRAMBLING_ENABLE;
201
202 ret = drm_scdc_writeb(adapter: connector->ddc, SCDC_TMDS_CONFIG, value: config);
203 if (ret < 0) {
204 drm_dbg_kms(connector->dev,
205 "[CONNECTOR:%d:%s] Failed to enable scrambling: %d\n",
206 connector->base.id, connector->name, ret);
207 return false;
208 }
209
210 return true;
211}
212EXPORT_SYMBOL(drm_scdc_set_scrambling);
213
214/**
215 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
216 * @connector: connector
217 * @set: ret or reset the high clock ratio
218 *
219 *
220 * TMDS clock ratio calculations go like this:
221 * TMDS character = 10 bit TMDS encoded value
222 *
223 * TMDS character rate = The rate at which TMDS characters are
224 * transmitted (Mcsc)
225 *
226 * TMDS bit rate = 10x TMDS character rate
227 *
228 * As per the spec:
229 * TMDS clock rate for pixel clock < 340 MHz = 1x the character
230 * rate = 1/10 pixel clock rate
231 *
232 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
233 * rate = 1/40 pixel clock rate
234 *
235 * Writes to the TMDS config register over SCDC channel, and:
236 * sets TMDS clock ratio to 1/40 when set = 1
237 *
238 * sets TMDS clock ratio to 1/10 when set = 0
239 *
240 * Returns:
241 * True if write is successful, false otherwise.
242 */
243bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector,
244 bool set)
245{
246 u8 config;
247 int ret;
248
249 ret = drm_scdc_readb(adapter: connector->ddc, SCDC_TMDS_CONFIG, value: &config);
250 if (ret < 0) {
251 drm_dbg_kms(connector->dev,
252 "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
253 connector->base.id, connector->name, ret);
254 return false;
255 }
256
257 if (set)
258 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
259 else
260 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
261
262 ret = drm_scdc_writeb(adapter: connector->ddc, SCDC_TMDS_CONFIG, value: config);
263 if (ret < 0) {
264 drm_dbg_kms(connector->dev,
265 "[CONNECTOR:%d:%s] Failed to set TMDS clock ratio: %d\n",
266 connector->base.id, connector->name, ret);
267 return false;
268 }
269
270 /*
271 * The spec says that a source should wait minimum 1ms and maximum
272 * 100ms after writing the TMDS config for clock ratio. Lets allow a
273 * wait of up to 2ms here.
274 */
275 usleep_range(min: 1000, max: 2000);
276 return true;
277}
278EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
279

source code of linux/drivers/gpu/drm/display/drm_scdc_helper.c