1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
4	*
5	* The TC358767/TC358867/TC9595 can operate in multiple modes.
6	* All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
7	*
8	* Copyright (C) 2016 CogentEmbedded Inc
9	* Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
10	*
11	* Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
12	*
13	* Copyright (C) 2016 Zodiac Inflight Innovations
14	*
15	* Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
16	*
17	* Copyright (C) 2012 Texas Instruments
18	* Author: Rob Clark <robdclark@gmail.com>
19	*/
20
21	#include <linux/bitfield.h>
22	#include <linux/clk.h>
23	#include <linux/device.h>
24	#include <linux/gpio/consumer.h>
25	#include <linux/i2c.h>
26	#include <linux/kernel.h>
27	#include <linux/media-bus-format.h>
28	#include <linux/module.h>
29	#include <linux/regmap.h>
30	#include <linux/slab.h>
31
32	#include <drm/display/drm_dp_helper.h>
33	#include <drm/drm_atomic_helper.h>
34	#include <drm/drm_bridge.h>
35	#include <drm/drm_edid.h>
36	#include <drm/drm_mipi_dsi.h>
37	#include <drm/drm_of.h>
38	#include <drm/drm_panel.h>
39	#include <drm/drm_print.h>
40	#include <drm/drm_probe_helper.h>
41
42	/* Registers */
43
44	/* DSI D-PHY Layer registers */
45	#define D0W_DPHYCONTTX 0x0004
46	#define CLW_DPHYCONTTX 0x0020
47	#define D0W_DPHYCONTRX 0x0024
48	#define D1W_DPHYCONTRX 0x0028
49	#define D2W_DPHYCONTRX 0x002c
50	#define D3W_DPHYCONTRX 0x0030
51	#define COM_DPHYCONTRX 0x0038
52	#define CLW_CNTRL 0x0040
53	#define D0W_CNTRL 0x0044
54	#define D1W_CNTRL 0x0048
55	#define D2W_CNTRL 0x004c
56	#define D3W_CNTRL 0x0050
57	#define TESTMODE_CNTRL 0x0054
58
59	/* PPI layer registers */
60	#define PPI_STARTPPI 0x0104 /* START control bit */
61	#define PPI_BUSYPPI 0x0108 /* PPI busy status */
62	#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
63	#define LPX_PERIOD 3
64	#define PPI_LANEENABLE 0x0134
65	#define PPI_TX_RX_TA 0x013c
66	#define TTA_GET 0x40000
67	#define TTA_SURE 6
68	#define PPI_D0S_ATMR 0x0144
69	#define PPI_D1S_ATMR 0x0148
70	#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
71	#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
72	#define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */
73	#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
74	#define PPI_START_FUNCTION BIT(0)
75
76	/* DSI layer registers */
77	#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
78	#define DSI_BUSYDSI 0x0208 /* DSI busy status */
79	#define DSI_LANEENABLE 0x0210 /* Enables each lane */
80	#define DSI_RX_START BIT(0)
81
82	/* Lane enable PPI and DSI register bits */
83	#define LANEENABLE_CLEN BIT(0)
84	#define LANEENABLE_L0EN BIT(1)
85	#define LANEENABLE_L1EN BIT(2)
86	#define LANEENABLE_L2EN BIT(1)
87	#define LANEENABLE_L3EN BIT(2)
88
89	#define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */
90	#define DSI_LANESTATUS1 0x0218 /* DSI lane status 1 */
91	#define DSI_INTSTATUS 0x0220 /* Interrupt Status */
92	#define DSI_INTMASK 0x0224 /* Interrupt Mask */
93	#define DSI_INTCLR 0x0228 /* Interrupt Clear */
94	#define DSI_LPTXTO 0x0230 /* LPTX Time Out Counter */
95
96	/* DSI General Registers */
97	#define DSIERRCNT 0x0300 /* DSI Error Count Register */
98
99	/* DSI Application Layer Registers */
100	#define APLCTRL 0x0400 /* Application layer Control Register */
101	#define RDPKTLN 0x0404 /* DSI Read packet Length Register */
102
103	/* Display Parallel Input Interface */
104	#define DPIPXLFMT 0x0440
105	#define VS_POL_ACTIVE_LOW (1 << 10)
106	#define HS_POL_ACTIVE_LOW (1 << 9)
107	#define DE_POL_ACTIVE_HIGH (0 << 8)
108	#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
109	#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
110	#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
111	#define DPI_BPP_RGB888 (0 << 0)
112	#define DPI_BPP_RGB666 (1 << 0)
113	#define DPI_BPP_RGB565 (2 << 0)
114
115	/* Display Parallel Output Interface */
116	#define POCTRL 0x0448
117	#define POCTRL_S2P BIT(7)
118	#define POCTRL_PCLK_POL BIT(3)
119	#define POCTRL_VS_POL BIT(2)
120	#define POCTRL_HS_POL BIT(1)
121	#define POCTRL_DE_POL BIT(0)
122
123	/* Video Path */
124	#define VPCTRL0 0x0450
125	#define VSDELAY GENMASK(31, 20)
126	#define OPXLFMT_RGB666 (0 << 8)
127	#define OPXLFMT_RGB888 (1 << 8)
128	#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
129	#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
130	#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
131	#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
132	#define HTIM01 0x0454
133	#define HPW GENMASK(8, 0)
134	#define HBPR GENMASK(24, 16)
135	#define HTIM02 0x0458
136	#define HDISPR GENMASK(10, 0)
137	#define HFPR GENMASK(24, 16)
138	#define VTIM01 0x045c
139	#define VSPR GENMASK(7, 0)
140	#define VBPR GENMASK(23, 16)
141	#define VTIM02 0x0460
142	#define VFPR GENMASK(23, 16)
143	#define VDISPR GENMASK(10, 0)
144	#define VFUEN0 0x0464
145	#define VFUEN BIT(0) /* Video Frame Timing Upload */
146
147	/* System */
148	#define TC_IDREG 0x0500 /* Chip ID and Revision ID */
149	#define SYSBOOT 0x0504 /* System BootStrap Status Register */
150	#define SYSSTAT 0x0508 /* System Status Register */
151	#define SYSRSTENB 0x050c /* System Reset/Enable Register */
152	#define ENBI2C (1 << 0)
153	#define ENBLCD0 (1 << 2)
154	#define ENBBM (1 << 3)
155	#define ENBDSIRX (1 << 4)
156	#define ENBREG (1 << 5)
157	#define ENBHDCP (1 << 8)
158	#define SYSCTRL 0x0510 /* System Control Register */
159	#define DP0_AUDSRC_NO_INPUT (0 << 3)
160	#define DP0_AUDSRC_I2S_RX (1 << 3)
161	#define DP0_VIDSRC_NO_INPUT (0 << 0)
162	#define DP0_VIDSRC_DSI_RX (1 << 0)
163	#define DP0_VIDSRC_DPI_RX (2 << 0)
164	#define DP0_VIDSRC_COLOR_BAR (3 << 0)
165	#define GPIOM 0x0540 /* GPIO Mode Control Register */
166	#define GPIOC 0x0544 /* GPIO Direction Control Register */
167	#define GPIOO 0x0548 /* GPIO Output Register */
168	#define GPIOI 0x054c /* GPIO Input Register */
169	#define INTCTL_G 0x0560 /* General Interrupts Control Register */
170	#define INTSTS_G 0x0564 /* General Interrupts Status Register */
171
172	#define INT_SYSERR BIT(16)
173	#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
174	#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
175
176	#define TEST_INT_C 0x0570 /* Test Interrupts Control Register */
177	#define TEST_INT_S 0x0574 /* Test Interrupts Status Register */
178
179	#define INT_GP0_LCNT 0x0584 /* Interrupt GPIO0 Low Count Value Register */
180	#define INT_GP1_LCNT 0x0588 /* Interrupt GPIO1 Low Count Value Register */
181
182	/* Control */
183	#define DP0CTL 0x0600
184	#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
185	#define EF_EN BIT(5) /* Enable Enhanced Framing */
186	#define VID_EN BIT(1) /* Video transmission enable */
187	#define DP_EN BIT(0) /* Enable DPTX function */
188
189	/* Clocks */
190	#define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */
191	#define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */
192	#define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */
193	#define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */
194	#define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */
195	#define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */
196
197	/* Main Channel */
198	#define DP0_SECSAMPLE 0x0640
199	#define DP0_VIDSYNCDELAY 0x0644
200	#define VID_SYNC_DLY GENMASK(15, 0)
201	#define THRESH_DLY GENMASK(31, 16)
202
203	#define DP0_TOTALVAL 0x0648
204	#define H_TOTAL GENMASK(15, 0)
205	#define V_TOTAL GENMASK(31, 16)
206	#define DP0_STARTVAL 0x064c
207	#define H_START GENMASK(15, 0)
208	#define V_START GENMASK(31, 16)
209	#define DP0_ACTIVEVAL 0x0650
210	#define H_ACT GENMASK(15, 0)
211	#define V_ACT GENMASK(31, 16)
212
213	#define DP0_SYNCVAL 0x0654
214	#define VS_WIDTH GENMASK(30, 16)
215	#define HS_WIDTH GENMASK(14, 0)
216	#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
217	#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
218	#define DP0_MISC 0x0658
219	#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
220	#define MAX_TU_SYMBOL GENMASK(28, 23)
221	#define TU_SIZE GENMASK(21, 16)
222	#define BPC_6 (0 << 5)
223	#define BPC_8 (1 << 5)
224
225	/* AUX channel */
226	#define DP0_AUXCFG0 0x0660
227	#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
228	#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
229	#define DP0_AUXCFG1 0x0664
230	#define AUX_RX_FILTER_EN BIT(16)
231
232	#define DP0_AUXADDR 0x0668
233	#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
234	#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
235	#define DP0_AUXSTATUS 0x068c
236	#define AUX_BYTES GENMASK(15, 8)
237	#define AUX_STATUS GENMASK(7, 4)
238	#define AUX_TIMEOUT BIT(1)
239	#define AUX_BUSY BIT(0)
240	#define DP0_AUXI2CADR 0x0698
241
242	/* Link Training */
243	#define DP0_SRCCTRL 0x06a0
244	#define DP0_SRCCTRL_PRE1 GENMASK(29, 28)
245	#define DP0_SRCCTRL_SWG1 GENMASK(25, 24)
246	#define DP0_SRCCTRL_PRE0 GENMASK(21, 20)
247	#define DP0_SRCCTRL_SWG0 GENMASK(17, 16)
248	#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
249	#define DP0_SRCCTRL_EN810B BIT(12)
250	#define DP0_SRCCTRL_NOTP (0 << 8)
251	#define DP0_SRCCTRL_TP1 (1 << 8)
252	#define DP0_SRCCTRL_TP2 (2 << 8)
253	#define DP0_SRCCTRL_LANESKEW BIT(7)
254	#define DP0_SRCCTRL_SSCG BIT(3)
255	#define DP0_SRCCTRL_LANES_1 (0 << 2)
256	#define DP0_SRCCTRL_LANES_2 (1 << 2)
257	#define DP0_SRCCTRL_BW27 (1 << 1)
258	#define DP0_SRCCTRL_BW162 (0 << 1)
259	#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
260	#define DP0_LTSTAT 0x06d0
261	#define LT_LOOPDONE BIT(13)
262	#define LT_STATUS_MASK (0x1f << 8)
263	#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
264	#define LT_INTERLANE_ALIGN_DONE BIT(3)
265	#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
266	#define DP0_SNKLTCHGREQ 0x06d4
267	#define DP0_LTLOOPCTRL 0x06d8
268	#define DP0_SNKLTCTRL 0x06e4
269	#define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */
270	#define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */
271	#define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */
272	#define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */
273
274	#define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */
275	#define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */
276	#define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */
277	#define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */
278	#define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */
279	#define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */
280	#define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */
281	#define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */
282	#define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */
283
284	#define DP1_SRCCTRL 0x07a0 /* DP1 Control Register */
285	#define DP1_SRCCTRL_PRE GENMASK(21, 20)
286	#define DP1_SRCCTRL_SWG GENMASK(17, 16)
287
288	/* PHY */
289	#define DP_PHY_CTRL 0x0800
290	#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
291	#define BGREN BIT(25) /* AUX PHY BGR Enable */
292	#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
293	#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
294	#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
295	#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
296	#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
297	#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
298	#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
299	#define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */
300	#define DP_PHY_CFG_RD 0x0814 /* DP PHY Configuration Test Read Register */
301	#define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */
302	#define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */
303
304	/* I2S */
305	#define I2SCFG 0x0880 /* I2S Audio Config 0 Register */
306	#define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */
307	#define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */
308	#define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */
309	#define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */
310	#define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */
311	#define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */
312	#define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */
313	#define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */
314	#define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */
315	#define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */
316	#define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */
317	#define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */
318
319	/* PLL */
320	#define DP0_PLLCTRL 0x0900
321	#define DP1_PLLCTRL 0x0904 /* not defined in DS */
322	#define PXL_PLLCTRL 0x0908
323	#define PLLUPDATE BIT(2)
324	#define PLLBYP BIT(1)
325	#define PLLEN BIT(0)
326	#define PXL_PLLPARAM 0x0914
327	#define IN_SEL_REFCLK (0 << 14)
328	#define SYS_PLLPARAM 0x0918
329	#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
330	#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
331	#define REF_FREQ_26M (2 << 8) /* 26 MHz */
332	#define REF_FREQ_13M (3 << 8) /* 13 MHz */
333	#define SYSCLK_SEL_LSCLK (0 << 4)
334	#define LSCLK_DIV_1 (0 << 0)
335	#define LSCLK_DIV_2 (1 << 0)
336
337	/* Test & Debug */
338	#define TSTCTL 0x0a00
339	#define COLOR_R GENMASK(31, 24)
340	#define COLOR_G GENMASK(23, 16)
341	#define COLOR_B GENMASK(15, 8)
342	#define ENI2CFILTER BIT(4)
343	#define COLOR_BAR_MODE GENMASK(1, 0)
344	#define COLOR_BAR_MODE_BARS 2
345	#define PLL_DBG 0x0a04
346
347	enum tc_mode {
348	mode_dpi_to_edp = BIT(1) | BIT(2),
349	mode_dpi_to_dp = BIT(1),
350	mode_dsi_to_edp = BIT(0) | BIT(2),
351	mode_dsi_to_dp = BIT(0),
352	mode_dsi_to_dpi = BIT(0) | BIT(1),
353	};
354
355	static bool tc_test_pattern;
356	module_param_named(test, tc_test_pattern, bool, 0644);
357
358	struct tc_edp_link {
359	u8 dpcd[DP_RECEIVER_CAP_SIZE];
360	unsigned int rate;
361	u8 num_lanes;
362	u8 assr;
363	bool scrambler_dis;
364	bool spread;
365	};
366
367	struct tc_data {
368	struct device *dev;
369	struct regmap *regmap;
370	struct drm_dp_aux aux;
371
372	struct drm_bridge bridge;
373	struct drm_bridge *panel_bridge;
374	struct drm_connector connector;
375
376	struct mipi_dsi_device *dsi;
377
378	/* link settings */
379	struct tc_edp_link link;
380
381	/* current mode */
382	struct drm_display_mode mode;
383
384	u32 rev;
385	u8 assr;
386	u8 pre_emphasis[2];
387
388	struct gpio_desc *sd_gpio;
389	struct gpio_desc *reset_gpio;
390	struct clk *refclk;
391
392	/* do we have IRQ */
393	bool have_irq;
394
395	/* Input connector type, DSI and not DPI. */
396	bool input_connector_dsi;
397
398	/* HPD pin number (0 or 1) or -ENODEV */
399	int hpd_pin;
400	};
401
402	static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
403	{
404	return container_of(a, struct tc_data, aux);
405	}
406
407	static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
408	{
409	return container_of(b, struct tc_data, bridge);
410	}
411
412	static inline struct tc_data *connector_to_tc(struct drm_connector *c)
413	{
414	return container_of(c, struct tc_data, connector);
415	}
416
417	static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
418	unsigned int cond_mask,
419	unsigned int cond_value,
420	unsigned long sleep_us, u64 timeout_us)
421	{
422	unsigned int val;
423
424	return regmap_read_poll_timeout(tc->regmap, addr, val,
425	(val & cond_mask) == cond_value,
426	sleep_us, timeout_us);
427	}
428
429	static int tc_aux_wait_busy(struct tc_data *tc)
430	{
431	return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, cond_value: 0, sleep_us: 100, timeout_us: 100000);
432	}
433
434	static int tc_aux_write_data(struct tc_data *tc, const void *data,
435	size_t size)
436	{
437	u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
438	int ret, count = ALIGN(size, sizeof(u32));
439
440	memcpy(auxwdata, data, size);
441
442	ret = regmap_raw_write(map: tc->regmap, DP0_AUXWDATA(0), val: auxwdata, val_len: count);
443	if (ret)
444	return ret;
445
446	return size;
447	}
448
449	static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
450	{
451	u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
452	int ret, count = ALIGN(size, sizeof(u32));
453
454	ret = regmap_raw_read(map: tc->regmap, DP0_AUXRDATA(0), val: auxrdata, val_len: count);
455	if (ret)
456	return ret;
457
458	memcpy(data, auxrdata, size);
459
460	return size;
461	}
462
463	static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
464	{
465	u32 auxcfg0 = msg->request;
466
467	if (size)
468	auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
469	else
470	auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
471
472	return auxcfg0;
473	}
474
475	static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
476	struct drm_dp_aux_msg *msg)
477	{
478	struct tc_data *tc = aux_to_tc(a: aux);
479	size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
480	u8 request = msg->request & ~DP_AUX_I2C_MOT;
481	u32 auxstatus;
482	int ret;
483
484	ret = tc_aux_wait_busy(tc);
485	if (ret)
486	return ret;
487
488	switch (request) {
489	case DP_AUX_NATIVE_READ:
490	case DP_AUX_I2C_READ:
491	break;
492	case DP_AUX_NATIVE_WRITE:
493	case DP_AUX_I2C_WRITE:
494	if (size) {
495	ret = tc_aux_write_data(tc, data: msg->buffer, size);
496	if (ret < 0)
497	return ret;
498	}
499	break;
500	default:
501	return -EINVAL;
502	}
503
504	/* Store address */
505	ret = regmap_write(map: tc->regmap, DP0_AUXADDR, val: msg->address);
506	if (ret)
507	return ret;
508	/* Start transfer */
509	ret = regmap_write(map: tc->regmap, DP0_AUXCFG0, val: tc_auxcfg0(msg, size));
510	if (ret)
511	return ret;
512
513	ret = tc_aux_wait_busy(tc);
514	if (ret)
515	return ret;
516
517	ret = regmap_read(map: tc->regmap, DP0_AUXSTATUS, val: &auxstatus);
518	if (ret)
519	return ret;
520
521	if (auxstatus & AUX_TIMEOUT)
522	return -ETIMEDOUT;
523	/*
524	* For some reason address-only DP_AUX_I2C_WRITE (MOT), still
525	* reports 1 byte transferred in its status. To deal we that
526	* we ignore aux_bytes field if we know that this was an
527	* address-only transfer
528	*/
529	if (size)
530	size = FIELD_GET(AUX_BYTES, auxstatus);
531	msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
532
533	switch (request) {
534	case DP_AUX_NATIVE_READ:
535	case DP_AUX_I2C_READ:
536	if (size)
537	return tc_aux_read_data(tc, data: msg->buffer, size);
538	break;
539	}
540
541	return size;
542	}
543
544	static const char * const training_pattern1_errors[] = {
545	"No errors",
546	"Aux write error",
547	"Aux read error",
548	"Max voltage reached error",
549	"Loop counter expired error",
550	"res", "res", "res"
551	};
552
553	static const char * const training_pattern2_errors[] = {
554	"No errors",
555	"Aux write error",
556	"Aux read error",
557	"Clock recovery failed error",
558	"Loop counter expired error",
559	"res", "res", "res"
560	};
561
562	static u32 tc_srcctrl(struct tc_data *tc)
563	{
564	/*
565	* No training pattern, skew lane 1 data by two LSCLK cycles with
566	* respect to lane 0 data, AutoCorrect Mode = 0
567	*/
568	u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
569
570	if (tc->link.scrambler_dis)
571	reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
572	if (tc->link.spread)
573	reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
574	if (tc->link.num_lanes == 2)
575	reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
576	if (tc->link.rate != 162000)
577	reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
578	return reg;
579	}
580
581	static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
582	{
583	int ret;
584
585	ret = regmap_write(map: tc->regmap, reg: pllctrl, PLLUPDATE | PLLEN);
586	if (ret)
587	return ret;
588
589	/* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
590	usleep_range(min: 15000, max: 20000);
591
592	return 0;
593	}
594
595	static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
596	int *out_best_pixelclock, u32 *out_pxl_pllparam)
597	{
598	int i_pre, best_pre = 1;
599	int i_post, best_post = 1;
600	int div, best_div = 1;
601	int mul, best_mul = 1;
602	int delta, best_delta;
603	int ext_div[] = {1, 2, 3, 5, 7};
604	int clk_min, clk_max;
605	int best_pixelclock = 0;
606	int vco_hi = 0;
607	u32 pxl_pllparam;
608
609	/*
610	* refclk * mul / (ext_pre_div * pre_div) should be in range:
611	* - DPI ..... 0 to 100 MHz
612	* - (e)DP ... 150 to 650 MHz
613	*/
614	if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
615	clk_min = 0;
616	clk_max = 100000000;
617	} else {
618	clk_min = 150000000;
619	clk_max = 650000000;
620	}
621
622	dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
623	refclk);
624	best_delta = pixelclock;
625	/* Loop over all possible ext_divs, skipping invalid configurations */
626	for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
627	/*
628	* refclk / ext_pre_div should be in the 1 to 200 MHz range.
629	* We don't allow any refclk > 200 MHz, only check lower bounds.
630	*/
631	if (refclk / ext_div[i_pre] < 1000000)
632	continue;
633	for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
634	for (div = 1; div <= 16; div++) {
635	u32 clk, iclk;
636	u64 tmp;
637
638	/* PCLK PLL input unit clock ... 6..40 MHz */
639	iclk = refclk / (div * ext_div[i_pre]);
640	if (iclk < 6000000 || iclk > 40000000)
641	continue;
642
643	tmp = pixelclock * ext_div[i_pre] *
644	ext_div[i_post] * div;
645	do_div(tmp, refclk);
646	mul = tmp;
647
648	/* Check limits */
649	if ((mul < 1) || (mul > 128))
650	continue;
651
652	clk = (refclk / ext_div[i_pre] / div) * mul;
653	if ((clk > clk_max) || (clk < clk_min))
654	continue;
655
656	clk = clk / ext_div[i_post];
657	delta = clk - pixelclock;
658
659	if (abs(delta) < abs(best_delta)) {
660	best_pre = i_pre;
661	best_post = i_post;
662	best_div = div;
663	best_mul = mul;
664	best_delta = delta;
665	best_pixelclock = clk;
666	}
667	}
668	}
669	}
670	if (best_pixelclock == 0) {
671	dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
672	pixelclock);
673	return -EINVAL;
674	}
675
676	dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta);
677	dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
678	ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
679
680	/* if VCO >= 300 MHz */
681	if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
682	vco_hi = 1;
683	/* see DS */
684	if (best_div == 16)
685	best_div = 0;
686	if (best_mul == 128)
687	best_mul = 0;
688
689	pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
690	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
691	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
692	pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
693	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
694	pxl_pllparam |= best_mul; /* Multiplier for PLL */
695
696	if (out_best_pixelclock)
697	*out_best_pixelclock = best_pixelclock;
698
699	if (out_pxl_pllparam)
700	*out_pxl_pllparam = pxl_pllparam;
701
702	return 0;
703	}
704
705	static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
706	{
707	u32 pxl_pllparam = 0;
708	int ret;
709
710	ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, out_pxl_pllparam: &pxl_pllparam);
711	if (ret)
712	return ret;
713
714	/* Power up PLL and switch to bypass */
715	ret = regmap_write(map: tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
716	if (ret)
717	return ret;
718
719	ret = regmap_write(map: tc->regmap, PXL_PLLPARAM, val: pxl_pllparam);
720	if (ret)
721	return ret;
722
723	/* Force PLL parameter update and disable bypass */
724	return tc_pllupdate(tc, PXL_PLLCTRL);
725	}
726
727	static int tc_pxl_pll_dis(struct tc_data *tc)
728	{
729	/* Enable PLL bypass, power down PLL */
730	return regmap_write(map: tc->regmap, PXL_PLLCTRL, PLLBYP);
731	}
732
733	static int tc_stream_clock_calc(struct tc_data *tc)
734	{
735	/*
736	* If the Stream clock and Link Symbol clock are
737	* asynchronous with each other, the value of M changes over
738	* time. This way of generating link clock and stream
739	* clock is called Asynchronous Clock mode. The value M
740	* must change while the value N stays constant. The
741	* value of N in this Asynchronous Clock mode must be set
742	* to 2^15 or 32,768.
743	*
744	* LSCLK = 1/10 of high speed link clock
745	*
746	* f_STRMCLK = M/N * f_LSCLK
747	* M/N = f_STRMCLK / f_LSCLK
748	*
749	*/
750	return regmap_write(map: tc->regmap, DP0_VIDMNGEN1, val: 32768);
751	}
752
753	static int tc_set_syspllparam(struct tc_data *tc)
754	{
755	unsigned long rate;
756	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;
757
758	rate = clk_get_rate(clk: tc->refclk);
759	switch (rate) {
760	case 38400000:
761	pllparam |= REF_FREQ_38M4;
762	break;
763	case 26000000:
764	pllparam |= REF_FREQ_26M;
765	break;
766	case 19200000:
767	pllparam |= REF_FREQ_19M2;
768	break;
769	case 13000000:
770	pllparam |= REF_FREQ_13M;
771	break;
772	default:
773	dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
774	return -EINVAL;
775	}
776
777	return regmap_write(map: tc->regmap, SYS_PLLPARAM, val: pllparam);
778	}
779
780	static int tc_aux_link_setup(struct tc_data *tc)
781	{
782	int ret;
783	u32 dp0_auxcfg1;
784
785	/* Setup DP-PHY / PLL */
786	ret = tc_set_syspllparam(tc);
787	if (ret)
788	goto err;
789
790	ret = regmap_write(map: tc->regmap, DP_PHY_CTRL,
791	BGREN | PWR_SW_EN | PHY_A0_EN);
792	if (ret)
793	goto err;
794	/*
795	* Initially PLLs are in bypass. Force PLL parameter update,
796	* disable PLL bypass, enable PLL
797	*/
798	ret = tc_pllupdate(tc, DP0_PLLCTRL);
799	if (ret)
800	goto err;
801
802	ret = tc_pllupdate(tc, DP1_PLLCTRL);
803	if (ret)
804	goto err;
805
806	ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, sleep_us: 100, timeout_us: 100000);
807	if (ret == -ETIMEDOUT) {
808	dev_err(tc->dev, "Timeout waiting for PHY to become ready");
809	return ret;
810	} else if (ret) {
811	goto err;
812	}
813
814	/* Setup AUX link */
815	dp0_auxcfg1 = AUX_RX_FILTER_EN;
816	dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
817	dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
818
819	ret = regmap_write(map: tc->regmap, DP0_AUXCFG1, val: dp0_auxcfg1);
820	if (ret)
821	goto err;
822
823	/* Register DP AUX channel */
824	tc->aux.name = "TC358767 AUX i2c adapter";
825	tc->aux.dev = tc->dev;
826	tc->aux.transfer = tc_aux_transfer;
827	drm_dp_aux_init(aux: &tc->aux);
828
829	return 0;
830	err:
831	dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
832	return ret;
833	}
834
835	static int tc_get_display_props(struct tc_data *tc)
836	{
837	u8 revision, num_lanes;
838	unsigned int rate;
839	int ret;
840	u8 reg;
841
842	/* Read DP Rx Link Capability */
843	ret = drm_dp_dpcd_read(aux: &tc->aux, DP_DPCD_REV, buffer: tc->link.dpcd,
844	DP_RECEIVER_CAP_SIZE);
845	if (ret < 0)
846	goto err_dpcd_read;
847
848	revision = tc->link.dpcd[DP_DPCD_REV];
849	rate = drm_dp_max_link_rate(dpcd: tc->link.dpcd);
850	num_lanes = drm_dp_max_lane_count(dpcd: tc->link.dpcd);
851
852	if (rate != 162000 && rate != 270000) {
853	dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
854	rate = 270000;
855	}
856
857	tc->link.rate = rate;
858
859	if (num_lanes > 2) {
860	dev_dbg(tc->dev, "Falling to 2 lanes\n");
861	num_lanes = 2;
862	}
863
864	tc->link.num_lanes = num_lanes;
865
866	ret = drm_dp_dpcd_readb(aux: &tc->aux, DP_MAX_DOWNSPREAD, valuep: &reg);
867	if (ret < 0)
868	goto err_dpcd_read;
869	tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
870
871	ret = drm_dp_dpcd_readb(aux: &tc->aux, DP_MAIN_LINK_CHANNEL_CODING, valuep: &reg);
872	if (ret < 0)
873	goto err_dpcd_read;
874
875	tc->link.scrambler_dis = false;
876	/* read assr */
877	ret = drm_dp_dpcd_readb(aux: &tc->aux, DP_EDP_CONFIGURATION_SET, valuep: &reg);
878	if (ret < 0)
879	goto err_dpcd_read;
880	tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
881
882	dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
883	revision >> 4, revision & 0x0f,
884	(tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
885	tc->link.num_lanes,
886	drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
887	"enhanced" : "default");
888	dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
889	tc->link.spread ? "0.5%" : "0.0%",
890	tc->link.scrambler_dis ? "disabled" : "enabled");
891	dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
892	tc->link.assr, tc->assr);
893
894	return 0;
895
896	err_dpcd_read:
897	dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
898	return ret;
899	}
900
901	static int tc_set_common_video_mode(struct tc_data *tc,
902	const struct drm_display_mode *mode)
903	{
904	int left_margin = mode->htotal - mode->hsync_end;
905	int right_margin = mode->hsync_start - mode->hdisplay;
906	int hsync_len = mode->hsync_end - mode->hsync_start;
907	int upper_margin = mode->vtotal - mode->vsync_end;
908	int lower_margin = mode->vsync_start - mode->vdisplay;
909	int vsync_len = mode->vsync_end - mode->vsync_start;
910	int ret;
911
912	dev_dbg(tc->dev, "set mode %dx%d\n",
913	mode->hdisplay, mode->vdisplay);
914	dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
915	left_margin, right_margin, hsync_len);
916	dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
917	upper_margin, lower_margin, vsync_len);
918	dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
919
920	/*
921	* LCD Ctl Frame Size
922	* datasheet is not clear of vsdelay in case of DPI
923	* assume we do not need any delay when DPI is a source of
924	* sync signals
925	*/
926	ret = regmap_write(map: tc->regmap, VPCTRL0,
927	FIELD_PREP(VSDELAY, right_margin + 10) |
928	OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED);
929	if (ret)
930	return ret;
931
932	ret = regmap_write(map: tc->regmap, HTIM01,
933	FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
934	FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
935	if (ret)
936	return ret;
937
938	ret = regmap_write(map: tc->regmap, HTIM02,
939	FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
940	FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
941	if (ret)
942	return ret;
943
944	ret = regmap_write(map: tc->regmap, VTIM01,
945	FIELD_PREP(VBPR, upper_margin) |
946	FIELD_PREP(VSPR, vsync_len));
947	if (ret)
948	return ret;
949
950	ret = regmap_write(map: tc->regmap, VTIM02,
951	FIELD_PREP(VFPR, lower_margin) |
952	FIELD_PREP(VDISPR, mode->vdisplay));
953	if (ret)
954	return ret;
955
956	ret = regmap_write(map: tc->regmap, VFUEN0, VFUEN); /* update settings */
957	if (ret)
958	return ret;
959
960	/* Test pattern settings */
961	ret = regmap_write(map: tc->regmap, TSTCTL,
962	FIELD_PREP(COLOR_R, 120) |
963	FIELD_PREP(COLOR_G, 20) |
964	FIELD_PREP(COLOR_B, 99) |
965	ENI2CFILTER |
966	FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
967
968	return ret;
969	}
970
971	static int tc_set_dpi_video_mode(struct tc_data *tc,
972	const struct drm_display_mode *mode)
973	{
974	u32 value = POCTRL_S2P;
975
976	if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
977	value |= POCTRL_HS_POL;
978
979	if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
980	value |= POCTRL_VS_POL;
981
982	return regmap_write(map: tc->regmap, POCTRL, val: value);
983	}
984
985	static int tc_set_edp_video_mode(struct tc_data *tc,
986	const struct drm_display_mode *mode)
987	{
988	int ret;
989	int vid_sync_dly;
990	int max_tu_symbol;
991
992	int left_margin = mode->htotal - mode->hsync_end;
993	int hsync_len = mode->hsync_end - mode->hsync_start;
994	int upper_margin = mode->vtotal - mode->vsync_end;
995	int vsync_len = mode->vsync_end - mode->vsync_start;
996	u32 dp0_syncval;
997	u32 bits_per_pixel = 24;
998	u32 in_bw, out_bw;
999	u32 dpipxlfmt;
1000
1001	/*
1002	* Recommended maximum number of symbols transferred in a transfer unit:
1003	* DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
1004	* (output active video bandwidth in bytes))
1005	* Must be less than tu_size.
1006	*/
1007
1008	in_bw = mode->clock * bits_per_pixel / 8;
1009	out_bw = tc->link.num_lanes * tc->link.rate;
1010	max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
1011
1012	/* DP Main Stream Attributes */
1013	vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
1014	ret = regmap_write(map: tc->regmap, DP0_VIDSYNCDELAY,
1015	FIELD_PREP(THRESH_DLY, max_tu_symbol) |
1016	FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
1017
1018	ret = regmap_write(map: tc->regmap, DP0_TOTALVAL,
1019	FIELD_PREP(H_TOTAL, mode->htotal) |
1020	FIELD_PREP(V_TOTAL, mode->vtotal));
1021	if (ret)
1022	return ret;
1023
1024	ret = regmap_write(map: tc->regmap, DP0_STARTVAL,
1025	FIELD_PREP(H_START, left_margin + hsync_len) |
1026	FIELD_PREP(V_START, upper_margin + vsync_len));
1027	if (ret)
1028	return ret;
1029
1030	ret = regmap_write(map: tc->regmap, DP0_ACTIVEVAL,
1031	FIELD_PREP(V_ACT, mode->vdisplay) |
1032	FIELD_PREP(H_ACT, mode->hdisplay));
1033	if (ret)
1034	return ret;
1035
1036	dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
1037	FIELD_PREP(HS_WIDTH, hsync_len);
1038
1039	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1040	dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
1041
1042	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1043	dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
1044
1045	ret = regmap_write(map: tc->regmap, DP0_SYNCVAL, val: dp0_syncval);
1046	if (ret)
1047	return ret;
1048
1049	dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888;
1050
1051	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1052	dpipxlfmt |= VS_POL_ACTIVE_LOW;
1053
1054	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1055	dpipxlfmt |= HS_POL_ACTIVE_LOW;
1056
1057	ret = regmap_write(map: tc->regmap, DPIPXLFMT, val: dpipxlfmt);
1058	if (ret)
1059	return ret;
1060
1061	ret = regmap_write(map: tc->regmap, DP0_MISC,
1062	FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
1063	FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
1064	BPC_8);
1065	return ret;
1066	}
1067
1068	static int tc_wait_link_training(struct tc_data *tc)
1069	{
1070	u32 value;
1071	int ret;
1072
1073	ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
1074	LT_LOOPDONE, sleep_us: 500, timeout_us: 100000);
1075	if (ret) {
1076	dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
1077	return ret;
1078	}
1079
1080	ret = regmap_read(map: tc->regmap, DP0_LTSTAT, val: &value);
1081	if (ret)
1082	return ret;
1083
1084	return (value >> 8) & 0x7;
1085	}
1086
1087	static int tc_main_link_enable(struct tc_data *tc)
1088	{
1089	struct drm_dp_aux *aux = &tc->aux;
1090	struct device *dev = tc->dev;
1091	u32 dp_phy_ctrl;
1092	u32 value;
1093	int ret;
1094	u8 tmp[DP_LINK_STATUS_SIZE];
1095
1096	dev_dbg(tc->dev, "link enable\n");
1097
1098	ret = regmap_read(map: tc->regmap, DP0CTL, val: &value);
1099	if (ret)
1100	return ret;
1101
1102	if (WARN_ON(value & DP_EN)) {
1103	ret = regmap_write(map: tc->regmap, DP0CTL, val: 0);
1104	if (ret)
1105	return ret;
1106	}
1107
1108	ret = regmap_write(map: tc->regmap, DP0_SRCCTRL,
1109	val: tc_srcctrl(tc) |
1110	FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1111	FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1112	if (ret)
1113	return ret;
1114	/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
1115	ret = regmap_write(map: tc->regmap, DP1_SRCCTRL,
1116	val: (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1117	((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0) |
1118	FIELD_PREP(DP1_SRCCTRL_PRE, tc->pre_emphasis[1]));
1119	if (ret)
1120	return ret;
1121
1122	ret = tc_set_syspllparam(tc);
1123	if (ret)
1124	return ret;
1125
1126	/* Setup Main Link */
1127	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
1128	if (tc->link.num_lanes == 2)
1129	dp_phy_ctrl |= PHY_2LANE;
1130
1131	ret = regmap_write(map: tc->regmap, DP_PHY_CTRL, val: dp_phy_ctrl);
1132	if (ret)
1133	return ret;
1134
1135	/* PLL setup */
1136	ret = tc_pllupdate(tc, DP0_PLLCTRL);
1137	if (ret)
1138	return ret;
1139
1140	ret = tc_pllupdate(tc, DP1_PLLCTRL);
1141	if (ret)
1142	return ret;
1143
1144	/* Reset/Enable Main Links */
1145	dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
1146	ret = regmap_write(map: tc->regmap, DP_PHY_CTRL, val: dp_phy_ctrl);
1147	usleep_range(min: 100, max: 200);
1148	dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
1149	ret = regmap_write(map: tc->regmap, DP_PHY_CTRL, val: dp_phy_ctrl);
1150
1151	ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, sleep_us: 500, timeout_us: 100000);
1152	if (ret) {
1153	dev_err(dev, "timeout waiting for phy become ready");
1154	return ret;
1155	}
1156
1157	/* Set misc: 8 bits per color */
1158	ret = regmap_update_bits(map: tc->regmap, DP0_MISC, BPC_8, BPC_8);
1159	if (ret)
1160	return ret;
1161
1162	/*
1163	* ASSR mode
1164	* on TC358767 side ASSR configured through strap pin
1165	* seems there is no way to change this setting from SW
1166	*
1167	* check is tc configured for same mode
1168	*/
1169	if (tc->assr != tc->link.assr) {
1170	dev_dbg(dev, "Trying to set display to ASSR: %d\n",
1171	tc->assr);
1172	/* try to set ASSR on display side */
1173	tmp[0] = tc->assr;
1174	ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, value: tmp[0]);
1175	if (ret < 0)
1176	goto err_dpcd_read;
1177	/* read back */
1178	ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, valuep: tmp);
1179	if (ret < 0)
1180	goto err_dpcd_read;
1181
1182	if (tmp[0] != tc->assr) {
1183	dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
1184	tc->assr);
1185	/* trying with disabled scrambler */
1186	tc->link.scrambler_dis = true;
1187	}
1188	}
1189
1190	/* Setup Link & DPRx Config for Training */
1191	tmp[0] = drm_dp_link_rate_to_bw_code(link_rate: tc->link.rate);
1192	tmp[1] = tc->link.num_lanes;
1193
1194	if (drm_dp_enhanced_frame_cap(dpcd: tc->link.dpcd))
1195	tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1196
1197	ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, buffer: tmp, size: 2);
1198	if (ret < 0)
1199	goto err_dpcd_write;
1200
1201	/* DOWNSPREAD_CTRL */
1202	tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1203	/* MAIN_LINK_CHANNEL_CODING_SET */
1204	tmp[1] = DP_SET_ANSI_8B10B;
1205	ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, buffer: tmp, size: 2);
1206	if (ret < 0)
1207	goto err_dpcd_write;
1208
1209	/* Reset voltage-swing & pre-emphasis */
1210	tmp[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1211	FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[0]);
1212	tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1213	FIELD_PREP(DP_TRAIN_PRE_EMPHASIS_MASK, tc->pre_emphasis[1]);
1214	ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, buffer: tmp, size: 2);
1215	if (ret < 0)
1216	goto err_dpcd_write;
1217
1218	/* Clock-Recovery */
1219
1220	/* Set DPCD 0x102 for Training Pattern 1 */
1221	ret = regmap_write(map: tc->regmap, DP0_SNKLTCTRL,
1222	DP_LINK_SCRAMBLING_DISABLE |
1223	DP_TRAINING_PATTERN_1);
1224	if (ret)
1225	return ret;
1226
1227	ret = regmap_write(map: tc->regmap, DP0_LTLOOPCTRL,
1228	val: (15 << 28) | /* Defer Iteration Count */
1229	(15 << 24) | /* Loop Iteration Count */
1230	(0xd << 0)); /* Loop Timer Delay */
1231	if (ret)
1232	return ret;
1233
1234	ret = regmap_write(map: tc->regmap, DP0_SRCCTRL,
1235	val: tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1236	DP0_SRCCTRL_AUTOCORRECT |
1237	DP0_SRCCTRL_TP1 |
1238	FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1239	FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1240	if (ret)
1241	return ret;
1242
1243	/* Enable DP0 to start Link Training */
1244	ret = regmap_write(map: tc->regmap, DP0CTL,
1245	val: (drm_dp_enhanced_frame_cap(dpcd: tc->link.dpcd) ?
1246	EF_EN : 0) | DP_EN);
1247	if (ret)
1248	return ret;
1249
1250	/* wait */
1251
1252	ret = tc_wait_link_training(tc);
1253	if (ret < 0)
1254	return ret;
1255
1256	if (ret) {
1257	dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1258	training_pattern1_errors[ret]);
1259	return -ENODEV;
1260	}
1261
1262	/* Channel Equalization */
1263
1264	/* Set DPCD 0x102 for Training Pattern 2 */
1265	ret = regmap_write(map: tc->regmap, DP0_SNKLTCTRL,
1266	DP_LINK_SCRAMBLING_DISABLE |
1267	DP_TRAINING_PATTERN_2);
1268	if (ret)
1269	return ret;
1270
1271	ret = regmap_write(map: tc->regmap, DP0_SRCCTRL,
1272	val: tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1273	DP0_SRCCTRL_AUTOCORRECT |
1274	DP0_SRCCTRL_TP2 |
1275	FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1276	FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1277	if (ret)
1278	return ret;
1279
1280	/* wait */
1281	ret = tc_wait_link_training(tc);
1282	if (ret < 0)
1283	return ret;
1284
1285	if (ret) {
1286	dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1287	training_pattern2_errors[ret]);
1288	return -ENODEV;
1289	}
1290
1291	/*
1292	* Toshiba's documentation suggests to first clear DPCD 0x102, then
1293	* clear the training pattern bit in DP0_SRCCTRL. Testing shows
1294	* that the link sometimes drops if those steps are done in that order,
1295	* but if the steps are done in reverse order, the link stays up.
1296	*
1297	* So we do the steps differently than documented here.
1298	*/
1299
1300	/* Clear Training Pattern, set AutoCorrect Mode = 1 */
1301	ret = regmap_write(map: tc->regmap, DP0_SRCCTRL, val: tc_srcctrl(tc) |
1302	DP0_SRCCTRL_AUTOCORRECT |
1303	FIELD_PREP(DP0_SRCCTRL_PRE0, tc->pre_emphasis[0]) |
1304	FIELD_PREP(DP0_SRCCTRL_PRE1, tc->pre_emphasis[1]));
1305	if (ret)
1306	return ret;
1307
1308	/* Clear DPCD 0x102 */
1309	/* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1310	tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1311	ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, value: tmp[0]);
1312	if (ret < 0)
1313	goto err_dpcd_write;
1314
1315	/* Check link status */
1316	ret = drm_dp_dpcd_read_link_status(aux, status: tmp);
1317	if (ret < 0)
1318	goto err_dpcd_read;
1319
1320	ret = 0;
1321
1322	value = tmp[0] & DP_CHANNEL_EQ_BITS;
1323
1324	if (value != DP_CHANNEL_EQ_BITS) {
1325	dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1326	ret = -ENODEV;
1327	}
1328
1329	if (tc->link.num_lanes == 2) {
1330	value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1331
1332	if (value != DP_CHANNEL_EQ_BITS) {
1333	dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1334	ret = -ENODEV;
1335	}
1336
1337	if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1338	dev_err(tc->dev, "Interlane align failed\n");
1339	ret = -ENODEV;
1340	}
1341	}
1342
1343	if (ret) {
1344	dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1345	dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1346	dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1347	dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1348	dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1349	dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1350	return ret;
1351	}
1352
1353	return 0;
1354	err_dpcd_read:
1355	dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1356	return ret;
1357	err_dpcd_write:
1358	dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1359	return ret;
1360	}
1361
1362	static int tc_main_link_disable(struct tc_data *tc)
1363	{
1364	int ret;
1365
1366	dev_dbg(tc->dev, "link disable\n");
1367
1368	ret = regmap_write(map: tc->regmap, DP0_SRCCTRL, val: 0);
1369	if (ret)
1370	return ret;
1371
1372	ret = regmap_write(map: tc->regmap, DP0CTL, val: 0);
1373	if (ret)
1374	return ret;
1375
1376	return regmap_update_bits(map: tc->regmap, DP_PHY_CTRL,
1377	PHY_M0_RST | PHY_M1_RST | PHY_M0_EN,
1378	PHY_M0_RST | PHY_M1_RST);
1379	}
1380
1381	static int tc_dsi_rx_enable(struct tc_data *tc)
1382	{
1383	u32 value;
1384	int ret;
1385
1386	regmap_write(map: tc->regmap, PPI_D0S_CLRSIPOCOUNT, val: 5);
1387	regmap_write(map: tc->regmap, PPI_D1S_CLRSIPOCOUNT, val: 5);
1388	regmap_write(map: tc->regmap, PPI_D2S_CLRSIPOCOUNT, val: 5);
1389	regmap_write(map: tc->regmap, PPI_D3S_CLRSIPOCOUNT, val: 5);
1390	regmap_write(map: tc->regmap, PPI_D0S_ATMR, val: 0);
1391	regmap_write(map: tc->regmap, PPI_D1S_ATMR, val: 0);
1392	regmap_write(map: tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1393	regmap_write(map: tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1394
1395	value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1396	LANEENABLE_CLEN;
1397	regmap_write(map: tc->regmap, PPI_LANEENABLE, val: value);
1398	regmap_write(map: tc->regmap, DSI_LANEENABLE, val: value);
1399
1400	/* Set input interface */
1401	value = DP0_AUDSRC_NO_INPUT;
1402	if (tc_test_pattern)
1403	value |= DP0_VIDSRC_COLOR_BAR;
1404	else
1405	value |= DP0_VIDSRC_DSI_RX;
1406	ret = regmap_write(map: tc->regmap, SYSCTRL, val: value);
1407	if (ret)
1408	return ret;
1409
1410	usleep_range(min: 120, max: 150);
1411
1412	regmap_write(map: tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1413	regmap_write(map: tc->regmap, DSI_STARTDSI, DSI_RX_START);
1414
1415	return 0;
1416	}
1417
1418	static int tc_dpi_rx_enable(struct tc_data *tc)
1419	{
1420	u32 value;
1421
1422	/* Set input interface */
1423	value = DP0_AUDSRC_NO_INPUT;
1424	if (tc_test_pattern)
1425	value |= DP0_VIDSRC_COLOR_BAR;
1426	else
1427	value |= DP0_VIDSRC_DPI_RX;
1428	return regmap_write(map: tc->regmap, SYSCTRL, val: value);
1429	}
1430
1431	static int tc_dpi_stream_enable(struct tc_data *tc)
1432	{
1433	int ret;
1434
1435	dev_dbg(tc->dev, "enable video stream\n");
1436
1437	/* Setup PLL */
1438	ret = tc_set_syspllparam(tc);
1439	if (ret)
1440	return ret;
1441
1442	/*
1443	* Initially PLLs are in bypass. Force PLL parameter update,
1444	* disable PLL bypass, enable PLL
1445	*/
1446	ret = tc_pllupdate(tc, DP0_PLLCTRL);
1447	if (ret)
1448	return ret;
1449
1450	ret = tc_pllupdate(tc, DP1_PLLCTRL);
1451	if (ret)
1452	return ret;
1453
1454	/* Pixel PLL must always be enabled for DPI mode */
1455	ret = tc_pxl_pll_en(tc, refclk: clk_get_rate(clk: tc->refclk),
1456	pixelclock: 1000 * tc->mode.clock);
1457	if (ret)
1458	return ret;
1459
1460	ret = tc_set_common_video_mode(tc, mode: &tc->mode);
1461	if (ret)
1462	return ret;
1463
1464	ret = tc_set_dpi_video_mode(tc, mode: &tc->mode);
1465	if (ret)
1466	return ret;
1467
1468	return tc_dsi_rx_enable(tc);
1469	}
1470
1471	static int tc_dpi_stream_disable(struct tc_data *tc)
1472	{
1473	dev_dbg(tc->dev, "disable video stream\n");
1474
1475	tc_pxl_pll_dis(tc);
1476
1477	return 0;
1478	}
1479
1480	static int tc_edp_stream_enable(struct tc_data *tc)
1481	{
1482	int ret;
1483	u32 value;
1484
1485	dev_dbg(tc->dev, "enable video stream\n");
1486
1487	/*
1488	* Pixel PLL must be enabled for DSI input mode and test pattern.
1489	*
1490	* Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1491	* "Clock Mode Selection and Clock Sources", either Pixel PLL
1492	* or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in
1493	* case valid Pixel Clock are supplied to the chip DPI input.
1494	* In case built-in test pattern is desired OR DSI input mode
1495	* is used, DPI_PCLK is not available and thus Pixel PLL must
1496	* be used instead.
1497	*/
1498	if (tc->input_connector_dsi || tc_test_pattern) {
1499	ret = tc_pxl_pll_en(tc, refclk: clk_get_rate(clk: tc->refclk),
1500	pixelclock: 1000 * tc->mode.clock);
1501	if (ret)
1502	return ret;
1503	}
1504
1505	ret = tc_set_common_video_mode(tc, mode: &tc->mode);
1506	if (ret)
1507	return ret;
1508
1509	ret = tc_set_edp_video_mode(tc, mode: &tc->mode);
1510	if (ret)
1511	return ret;
1512
1513	/* Set M/N */
1514	ret = tc_stream_clock_calc(tc);
1515	if (ret)
1516	return ret;
1517
1518	value = VID_MN_GEN | DP_EN;
1519	if (drm_dp_enhanced_frame_cap(dpcd: tc->link.dpcd))
1520	value |= EF_EN;
1521	ret = regmap_write(map: tc->regmap, DP0CTL, val: value);
1522	if (ret)
1523	return ret;
1524	/*
1525	* VID_EN assertion should be delayed by at least N * LSCLK
1526	* cycles from the time VID_MN_GEN is enabled in order to
1527	* generate stable values for VID_M. LSCLK is 270 MHz or
1528	* 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1529	* so a delay of at least 203 us should suffice.
1530	*/
1531	usleep_range(min: 500, max: 1000);
1532	value |= VID_EN;
1533	ret = regmap_write(map: tc->regmap, DP0CTL, val: value);
1534	if (ret)
1535	return ret;
1536
1537	/* Set input interface */
1538	if (tc->input_connector_dsi)
1539	return tc_dsi_rx_enable(tc);
1540	else
1541	return tc_dpi_rx_enable(tc);
1542	}
1543
1544	static int tc_edp_stream_disable(struct tc_data *tc)
1545	{
1546	int ret;
1547
1548	dev_dbg(tc->dev, "disable video stream\n");
1549
1550	ret = regmap_update_bits(map: tc->regmap, DP0CTL, VID_EN, val: 0);
1551	if (ret)
1552	return ret;
1553
1554	tc_pxl_pll_dis(tc);
1555
1556	return 0;
1557	}
1558
1559	static void tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge,
1560	struct drm_atomic_state *state)
1561
1562	{
1563	struct tc_data *tc = bridge_to_tc(b: bridge);
1564	int ret;
1565
1566	ret = tc_dpi_stream_enable(tc);
1567	if (ret < 0) {
1568	dev_err(tc->dev, "main link stream start error: %d\n", ret);
1569	tc_main_link_disable(tc);
1570	return;
1571	}
1572	}
1573
1574	static void tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge,
1575	struct drm_atomic_state *state)
1576	{
1577	struct tc_data *tc = bridge_to_tc(b: bridge);
1578	int ret;
1579
1580	ret = tc_dpi_stream_disable(tc);
1581	if (ret < 0)
1582	dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1583	}
1584
1585	static void tc_edp_bridge_atomic_enable(struct drm_bridge *bridge,
1586	struct drm_atomic_state *state)
1587	{
1588	struct tc_data *tc = bridge_to_tc(b: bridge);
1589	int ret;
1590
1591	ret = tc_get_display_props(tc);
1592	if (ret < 0) {
1593	dev_err(tc->dev, "failed to read display props: %d\n", ret);
1594	return;
1595	}
1596
1597	ret = tc_main_link_enable(tc);
1598	if (ret < 0) {
1599	dev_err(tc->dev, "main link enable error: %d\n", ret);
1600	return;
1601	}
1602
1603	ret = tc_edp_stream_enable(tc);
1604	if (ret < 0) {
1605	dev_err(tc->dev, "main link stream start error: %d\n", ret);
1606	tc_main_link_disable(tc);
1607	return;
1608	}
1609	}
1610
1611	static void tc_edp_bridge_atomic_disable(struct drm_bridge *bridge,
1612	struct drm_atomic_state *state)
1613	{
1614	struct tc_data *tc = bridge_to_tc(b: bridge);
1615	int ret;
1616
1617	ret = tc_edp_stream_disable(tc);
1618	if (ret < 0)
1619	dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1620
1621	ret = tc_main_link_disable(tc);
1622	if (ret < 0)
1623	dev_err(tc->dev, "main link disable error: %d\n", ret);
1624	}
1625
1626	static int tc_dpi_atomic_check(struct drm_bridge *bridge,
1627	struct drm_bridge_state *bridge_state,
1628	struct drm_crtc_state *crtc_state,
1629	struct drm_connector_state *conn_state)
1630	{
1631	struct tc_data *tc = bridge_to_tc(b: bridge);
1632	int adjusted_clock = 0;
1633	int ret;
1634
1635	ret = tc_pxl_pll_calc(tc, refclk: clk_get_rate(clk: tc->refclk),
1636	pixelclock: crtc_state->mode.clock * 1000,
1637	out_best_pixelclock: &adjusted_clock, NULL);
1638	if (ret)
1639	return ret;
1640
1641	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1642
1643	/* DSI->DPI interface clock limitation: upto 100 MHz */
1644	if (crtc_state->adjusted_mode.clock > 100000)
1645	return -EINVAL;
1646
1647	return 0;
1648	}
1649
1650	static int tc_edp_atomic_check(struct drm_bridge *bridge,
1651	struct drm_bridge_state *bridge_state,
1652	struct drm_crtc_state *crtc_state,
1653	struct drm_connector_state *conn_state)
1654	{
1655	struct tc_data *tc = bridge_to_tc(b: bridge);
1656	int adjusted_clock = 0;
1657	int ret;
1658
1659	ret = tc_pxl_pll_calc(tc, refclk: clk_get_rate(clk: tc->refclk),
1660	pixelclock: crtc_state->mode.clock * 1000,
1661	out_best_pixelclock: &adjusted_clock, NULL);
1662	if (ret)
1663	return ret;
1664
1665	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
1666
1667	/* DPI->(e)DP interface clock limitation: upto 154 MHz */
1668	if (crtc_state->adjusted_mode.clock > 154000)
1669	return -EINVAL;
1670
1671	return 0;
1672	}
1673
1674	static enum drm_mode_status
1675	tc_dpi_mode_valid(struct drm_bridge *bridge,
1676	const struct drm_display_info *info,
1677	const struct drm_display_mode *mode)
1678	{
1679	/* DPI interface clock limitation: upto 100 MHz */
1680	if (mode->clock > 100000)
1681	return MODE_CLOCK_HIGH;
1682
1683	return MODE_OK;
1684	}
1685
1686	static enum drm_mode_status
1687	tc_edp_mode_valid(struct drm_bridge *bridge,
1688	const struct drm_display_info *info,
1689	const struct drm_display_mode *mode)
1690	{
1691	struct tc_data *tc = bridge_to_tc(b: bridge);
1692	u32 req, avail;
1693	u32 bits_per_pixel = 24;
1694
1695	/* DPI->(e)DP interface clock limitation: up to 154 MHz */
1696	if (mode->clock > 154000)
1697	return MODE_CLOCK_HIGH;
1698
1699	req = mode->clock * bits_per_pixel / 8;
1700	avail = tc->link.num_lanes * tc->link.rate;
1701
1702	if (req > avail)
1703	return MODE_BAD;
1704
1705	return MODE_OK;
1706	}
1707
1708	static void tc_bridge_mode_set(struct drm_bridge *bridge,
1709	const struct drm_display_mode *mode,
1710	const struct drm_display_mode *adj)
1711	{
1712	struct tc_data *tc = bridge_to_tc(b: bridge);
1713
1714	drm_mode_copy(dst: &tc->mode, src: adj);
1715	}
1716
1717	static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge,
1718	struct drm_connector *connector)
1719	{
1720	struct tc_data *tc = bridge_to_tc(b: bridge);
1721	int ret;
1722
1723	ret = tc_get_display_props(tc);
1724	if (ret < 0) {
1725	dev_err(tc->dev, "failed to read display props: %d\n", ret);
1726	return 0;
1727	}
1728
1729	return drm_edid_read_ddc(connector, adapter: &tc->aux.ddc);
1730	}
1731
1732	static int tc_connector_get_modes(struct drm_connector *connector)
1733	{
1734	struct tc_data *tc = connector_to_tc(c: connector);
1735	int num_modes;
1736	const struct drm_edid *drm_edid;
1737	int ret;
1738
1739	ret = tc_get_display_props(tc);
1740	if (ret < 0) {
1741	dev_err(tc->dev, "failed to read display props: %d\n", ret);
1742	return 0;
1743	}
1744
1745	if (tc->panel_bridge) {
1746	num_modes = drm_bridge_get_modes(bridge: tc->panel_bridge, connector);
1747	if (num_modes > 0)
1748	return num_modes;
1749	}
1750
1751	drm_edid = tc_edid_read(bridge: &tc->bridge, connector);
1752	drm_edid_connector_update(connector, edid: drm_edid);
1753	num_modes = drm_edid_connector_add_modes(connector);
1754	drm_edid_free(drm_edid);
1755
1756	return num_modes;
1757	}
1758
1759	static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1760	.get_modes = tc_connector_get_modes,
1761	};
1762
1763	static enum drm_connector_status
1764	tc_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
1765	{
1766	struct tc_data *tc = bridge_to_tc(b: bridge);
1767	bool conn;
1768	u32 val;
1769	int ret;
1770
1771	ret = regmap_read(map: tc->regmap, GPIOI, val: &val);
1772	if (ret)
1773	return connector_status_unknown;
1774
1775	conn = val & BIT(tc->hpd_pin);
1776
1777	if (conn)
1778	return connector_status_connected;
1779	else
1780	return connector_status_disconnected;
1781	}
1782
1783	static enum drm_connector_status
1784	tc_connector_detect(struct drm_connector *connector, bool force)
1785	{
1786	struct tc_data *tc = connector_to_tc(c: connector);
1787
1788	if (tc->hpd_pin >= 0)
1789	return tc_bridge_detect(bridge: &tc->bridge, connector);
1790
1791	if (tc->panel_bridge)
1792	return connector_status_connected;
1793	else
1794	return connector_status_unknown;
1795	}
1796
1797	static const struct drm_connector_funcs tc_connector_funcs = {
1798	.detect = tc_connector_detect,
1799	.fill_modes = drm_helper_probe_single_connector_modes,
1800	.destroy = drm_connector_cleanup,
1801	.reset = drm_atomic_helper_connector_reset,
1802	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1803	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1804	};
1805
1806	static int tc_dpi_bridge_attach(struct drm_bridge *bridge,
1807	struct drm_encoder *encoder,
1808	enum drm_bridge_attach_flags flags)
1809	{
1810	struct tc_data *tc = bridge_to_tc(b: bridge);
1811
1812	if (!tc->panel_bridge)
1813	return 0;
1814
1815	return drm_bridge_attach(encoder: tc->bridge.encoder, bridge: tc->panel_bridge,
1816	previous: &tc->bridge, flags);
1817	}
1818
1819	static int tc_edp_bridge_attach(struct drm_bridge *bridge,
1820	struct drm_encoder *encoder,
1821	enum drm_bridge_attach_flags flags)
1822	{
1823	u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1824	struct tc_data *tc = bridge_to_tc(b: bridge);
1825	struct drm_device *drm = bridge->dev;
1826	int ret;
1827
1828	if (tc->panel_bridge) {
1829	/* If a connector is required then this driver shall create it */
1830	ret = drm_bridge_attach(encoder: tc->bridge.encoder, bridge: tc->panel_bridge,
1831	previous: &tc->bridge, flags: flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1832	if (ret)
1833	return ret;
1834	}
1835
1836	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1837	return 0;
1838
1839	tc->aux.drm_dev = drm;
1840	ret = drm_dp_aux_register(aux: &tc->aux);
1841	if (ret < 0)
1842	return ret;
1843
1844	/* Create DP/eDP connector */
1845	drm_connector_helper_add(connector: &tc->connector, funcs: &tc_connector_helper_funcs);
1846	ret = drm_connector_init(dev: drm, connector: &tc->connector, funcs: &tc_connector_funcs, connector_type: tc->bridge.type);
1847	if (ret)
1848	goto aux_unregister;
1849
1850	/* Don't poll if don't have HPD connected */
1851	if (tc->hpd_pin >= 0) {
1852	if (tc->have_irq)
1853	tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1854	else
1855	tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1856	DRM_CONNECTOR_POLL_DISCONNECT;
1857	}
1858
1859	drm_display_info_set_bus_formats(info: &tc->connector.display_info,
1860	formats: &bus_format, num_formats: 1);
1861	tc->connector.display_info.bus_flags =
1862	DRM_BUS_FLAG_DE_HIGH |
1863	DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1864	DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1865	drm_connector_attach_encoder(connector: &tc->connector, encoder: tc->bridge.encoder);
1866
1867	return 0;
1868	aux_unregister:
1869	drm_dp_aux_unregister(aux: &tc->aux);
1870	return ret;
1871	}
1872
1873	static void tc_edp_bridge_detach(struct drm_bridge *bridge)
1874	{
1875	drm_dp_aux_unregister(aux: &bridge_to_tc(b: bridge)->aux);
1876	}
1877
1878	#define MAX_INPUT_SEL_FORMATS 1
1879	#define MAX_OUTPUT_SEL_FORMATS 1
1880
1881	static u32 *
1882	tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1883	struct drm_bridge_state *bridge_state,
1884	struct drm_crtc_state *crtc_state,
1885	struct drm_connector_state *conn_state,
1886	u32 output_fmt,
1887	unsigned int *num_input_fmts)
1888	{
1889	u32 *input_fmts;
1890
1891	*num_input_fmts = 0;
1892
1893	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1894	GFP_KERNEL);
1895	if (!input_fmts)
1896	return NULL;
1897
1898	/* This is the DSI-end bus format */
1899	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1900	*num_input_fmts = 1;
1901
1902	return input_fmts;
1903	}
1904
1905	static u32 *
1906	tc_edp_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
1907	struct drm_bridge_state *bridge_state,
1908	struct drm_crtc_state *crtc_state,
1909	struct drm_connector_state *conn_state,
1910	unsigned int *num_output_fmts)
1911	{
1912	u32 *output_fmts;
1913
1914	*num_output_fmts = 0;
1915
1916	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
1917	GFP_KERNEL);
1918	if (!output_fmts)
1919	return NULL;
1920
1921	output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1922	*num_output_fmts = 1;
1923
1924	return output_fmts;
1925	}
1926
1927	static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
1928	.attach = tc_dpi_bridge_attach,
1929	.mode_valid = tc_dpi_mode_valid,
1930	.mode_set = tc_bridge_mode_set,
1931	.atomic_check = tc_dpi_atomic_check,
1932	.atomic_enable = tc_dpi_bridge_atomic_enable,
1933	.atomic_disable = tc_dpi_bridge_atomic_disable,
1934	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1935	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1936	.atomic_reset = drm_atomic_helper_bridge_reset,
1937	.atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts,
1938	};
1939
1940	static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
1941	.attach = tc_edp_bridge_attach,
1942	.detach = tc_edp_bridge_detach,
1943	.mode_valid = tc_edp_mode_valid,
1944	.mode_set = tc_bridge_mode_set,
1945	.atomic_check = tc_edp_atomic_check,
1946	.atomic_enable = tc_edp_bridge_atomic_enable,
1947	.atomic_disable = tc_edp_bridge_atomic_disable,
1948	.detect = tc_bridge_detect,
1949	.edid_read = tc_edid_read,
1950	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1951	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1952	.atomic_reset = drm_atomic_helper_bridge_reset,
1953	.atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
1954	.atomic_get_output_bus_fmts = tc_edp_atomic_get_output_bus_fmts,
1955	};
1956
1957	static bool tc_readable_reg(struct device *dev, unsigned int reg)
1958	{
1959	switch (reg) {
1960	/* DSI D-PHY Layer */
1961	case 0x004:
1962	case 0x020:
1963	case 0x024:
1964	case 0x028:
1965	case 0x02c:
1966	case 0x030:
1967	case 0x038:
1968	case 0x040:
1969	case 0x044:
1970	case 0x048:
1971	case 0x04c:
1972	case 0x050:
1973	case 0x054:
1974	/* DSI PPI Layer */
1975	case PPI_STARTPPI:
1976	case 0x108:
1977	case 0x110:
1978	case PPI_LPTXTIMECNT:
1979	case PPI_LANEENABLE:
1980	case PPI_TX_RX_TA:
1981	case 0x140:
1982	case PPI_D0S_ATMR:
1983	case PPI_D1S_ATMR:
1984	case 0x14c:
1985	case 0x150:
1986	case PPI_D0S_CLRSIPOCOUNT:
1987	case PPI_D1S_CLRSIPOCOUNT:
1988	case PPI_D2S_CLRSIPOCOUNT:
1989	case PPI_D3S_CLRSIPOCOUNT:
1990	case 0x180:
1991	case 0x184:
1992	case 0x188:
1993	case 0x18c:
1994	case 0x190:
1995	case 0x1a0:
1996	case 0x1a4:
1997	case 0x1a8:
1998	case 0x1ac:
1999	case 0x1b0:
2000	case 0x1c0:
2001	case 0x1c4:
2002	case 0x1c8:
2003	case 0x1cc:
2004	case 0x1d0:
2005	case 0x1e0:
2006	case 0x1e4:
2007	case 0x1f0:
2008	case 0x1f4:
2009	/* DSI Protocol Layer */
2010	case DSI_STARTDSI:
2011	case DSI_BUSYDSI:
2012	case DSI_LANEENABLE:
2013	case DSI_LANESTATUS0:
2014	case DSI_LANESTATUS1:
2015	case DSI_INTSTATUS:
2016	case 0x224:
2017	case 0x228:
2018	case 0x230:
2019	/* DSI General */
2020	case DSIERRCNT:
2021	/* DSI Application Layer */
2022	case 0x400:
2023	case 0x404:
2024	/* DPI */
2025	case DPIPXLFMT:
2026	/* Parallel Output */
2027	case POCTRL:
2028	/* Video Path0 Configuration */
2029	case VPCTRL0:
2030	case HTIM01:
2031	case HTIM02:
2032	case VTIM01:
2033	case VTIM02:
2034	case VFUEN0:
2035	/* System */
2036	case TC_IDREG:
2037	case 0x504:
2038	case SYSSTAT:
2039	case SYSRSTENB:
2040	case SYSCTRL:
2041	/* I2C */
2042	case 0x520:
2043	/* GPIO */
2044	case GPIOM:
2045	case GPIOC:
2046	case GPIOO:
2047	case GPIOI:
2048	/* Interrupt */
2049	case INTCTL_G:
2050	case INTSTS_G:
2051	case 0x570:
2052	case 0x574:
2053	case INT_GP0_LCNT:
2054	case INT_GP1_LCNT:
2055	/* DisplayPort Control */
2056	case DP0CTL:
2057	/* DisplayPort Clock */
2058	case DP0_VIDMNGEN0:
2059	case DP0_VIDMNGEN1:
2060	case DP0_VMNGENSTATUS:
2061	case 0x628:
2062	case 0x62c:
2063	case 0x630:
2064	/* DisplayPort Main Channel */
2065	case DP0_SECSAMPLE:
2066	case DP0_VIDSYNCDELAY:
2067	case DP0_TOTALVAL:
2068	case DP0_STARTVAL:
2069	case DP0_ACTIVEVAL:
2070	case DP0_SYNCVAL:
2071	case DP0_MISC:
2072	/* DisplayPort Aux Channel */
2073	case DP0_AUXCFG0:
2074	case DP0_AUXCFG1:
2075	case DP0_AUXADDR:
2076	case 0x66c:
2077	case 0x670:
2078	case 0x674:
2079	case 0x678:
2080	case 0x67c:
2081	case 0x680:
2082	case 0x684:
2083	case 0x688:
2084	case DP0_AUXSTATUS:
2085	case DP0_AUXI2CADR:
2086	/* DisplayPort Link Training */
2087	case DP0_SRCCTRL:
2088	case DP0_LTSTAT:
2089	case DP0_SNKLTCHGREQ:
2090	case DP0_LTLOOPCTRL:
2091	case DP0_SNKLTCTRL:
2092	case 0x6e8:
2093	case 0x6ec:
2094	case 0x6f0:
2095	case 0x6f4:
2096	/* DisplayPort Audio */
2097	case 0x700:
2098	case 0x704:
2099	case 0x708:
2100	case 0x70c:
2101	case 0x710:
2102	case 0x714:
2103	case 0x718:
2104	case 0x71c:
2105	case 0x720:
2106	/* DisplayPort Source Control */
2107	case DP1_SRCCTRL:
2108	/* DisplayPort PHY */
2109	case DP_PHY_CTRL:
2110	case 0x810:
2111	case 0x814:
2112	case 0x820:
2113	case 0x840:
2114	/* I2S */
2115	case 0x880:
2116	case 0x888:
2117	case 0x88c:
2118	case 0x890:
2119	case 0x894:
2120	case 0x898:
2121	case 0x89c:
2122	case 0x8a0:
2123	case 0x8a4:
2124	case 0x8a8:
2125	case 0x8ac:
2126	case 0x8b0:
2127	case 0x8b4:
2128	/* PLL */
2129	case DP0_PLLCTRL:
2130	case DP1_PLLCTRL:
2131	case PXL_PLLCTRL:
2132	case PXL_PLLPARAM:
2133	case SYS_PLLPARAM:
2134	/* HDCP */
2135	case 0x980:
2136	case 0x984:
2137	case 0x988:
2138	case 0x98c:
2139	case 0x990:
2140	case 0x994:
2141	case 0x998:
2142	case 0x99c:
2143	case 0x9a0:
2144	case 0x9a4:
2145	case 0x9a8:
2146	case 0x9ac:
2147	/* Debug */
2148	case TSTCTL:
2149	case PLL_DBG:
2150	return true;
2151	}
2152	return false;
2153	}
2154
2155	static const struct regmap_range tc_volatile_ranges[] = {
2156	regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI),
2157	regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI),
2158	regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS),
2159	regmap_reg_range(DSIERRCNT, DSIERRCNT),
2160	regmap_reg_range(VFUEN0, VFUEN0),
2161	regmap_reg_range(SYSSTAT, SYSSTAT),
2162	regmap_reg_range(GPIOI, GPIOI),
2163	regmap_reg_range(INTSTS_G, INTSTS_G),
2164	regmap_reg_range(DP0_VMNGENSTATUS, DP0_VMNGENSTATUS),
2165	regmap_reg_range(DP0_AMNGENSTATUS, DP0_AMNGENSTATUS),
2166	regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
2167	regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
2168	regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
2169	regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
2170	};
2171
2172	static const struct regmap_access_table tc_volatile_table = {
2173	.yes_ranges = tc_volatile_ranges,
2174	.n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
2175	};
2176
2177	static const struct regmap_range tc_precious_ranges[] = {
2178	regmap_reg_range(SYSSTAT, SYSSTAT),
2179	};
2180
2181	static const struct regmap_access_table tc_precious_table = {
2182	.yes_ranges = tc_precious_ranges,
2183	.n_yes_ranges = ARRAY_SIZE(tc_precious_ranges),
2184	};
2185
2186	static bool tc_writeable_reg(struct device *dev, unsigned int reg)
2187	{
2188	/* RO reg */
2189	switch (reg) {
2190	case PPI_BUSYPPI:
2191	case DSI_BUSYDSI:
2192	case DSI_LANESTATUS0:
2193	case DSI_LANESTATUS1:
2194	case DSI_INTSTATUS:
2195	case TC_IDREG:
2196	case SYSBOOT:
2197	case SYSSTAT:
2198	case GPIOI:
2199	case DP0_LTSTAT:
2200	case DP0_SNKLTCHGREQ:
2201	return false;
2202	}
2203	/* WO reg */
2204	switch (reg) {
2205	case DSI_STARTDSI:
2206	case DSI_INTCLR:
2207	return true;
2208	}
2209	return tc_readable_reg(dev, reg);
2210	}
2211
2212	static const struct regmap_config tc_regmap_config = {
2213	.name = "tc358767",
2214	.reg_bits = 16,
2215	.val_bits = 32,
2216	.reg_stride = 4,
2217	.max_register = PLL_DBG,
2218	.cache_type = REGCACHE_MAPLE,
2219	.readable_reg = tc_readable_reg,
2220	.writeable_reg = tc_writeable_reg,
2221	.volatile_table = &tc_volatile_table,
2222	.precious_table = &tc_precious_table,
2223	.reg_format_endian = REGMAP_ENDIAN_BIG,
2224	.val_format_endian = REGMAP_ENDIAN_LITTLE,
2225	};
2226
2227	static irqreturn_t tc_irq_handler(int irq, void *arg)
2228	{
2229	struct tc_data *tc = arg;
2230	u32 val;
2231	int r;
2232
2233	r = regmap_read(map: tc->regmap, INTSTS_G, val: &val);
2234	if (r)
2235	return IRQ_NONE;
2236
2237	if (!val)
2238	return IRQ_NONE;
2239
2240	if (val & INT_SYSERR) {
2241	u32 stat = 0;
2242
2243	regmap_read(map: tc->regmap, SYSSTAT, val: &stat);
2244
2245	dev_err(tc->dev, "syserr %x\n", stat);
2246	}
2247
2248	if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) {
2249	/*
2250	* H is triggered when the GPIO goes high.
2251	*
2252	* LC is triggered when the GPIO goes low and stays low for
2253	* the duration of LCNT
2254	*/
2255	bool h = val & INT_GPIO_H(tc->hpd_pin);
2256	bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2257
2258	if (h || lc) {
2259	dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2260	h ? "H" : "", lc ? "LC" : "");
2261	drm_kms_helper_hotplug_event(dev: tc->bridge.dev);
2262	}
2263	}
2264
2265	regmap_write(map: tc->regmap, INTSTS_G, val);
2266
2267	return IRQ_HANDLED;
2268	}
2269
2270	static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2271	{
2272	struct device *dev = tc->dev;
2273	struct device_node *host_node;
2274	struct device_node *endpoint;
2275	struct mipi_dsi_device *dsi;
2276	struct mipi_dsi_host *host;
2277	const struct mipi_dsi_device_info info = {
2278	.type = "tc358767",
2279	.channel = 0,
2280	.node = NULL,
2281	};
2282	int dsi_lanes, ret;
2283
2284	endpoint = of_graph_get_endpoint_by_regs(parent: dev->of_node, port_reg: 0, reg: -1);
2285	dsi_lanes = drm_of_get_data_lanes_count(endpoint, min: 1, max: 4);
2286	host_node = of_graph_get_remote_port_parent(node: endpoint);
2287	host = of_find_mipi_dsi_host_by_node(node: host_node);
2288	of_node_put(node: host_node);
2289	of_node_put(node: endpoint);
2290
2291	if (!host)
2292	return -EPROBE_DEFER;
2293
2294	if (dsi_lanes < 0)
2295	return dsi_lanes;
2296
2297	dsi = devm_mipi_dsi_device_register_full(dev, host, info: &info);
2298	if (IS_ERR(ptr: dsi))
2299	return dev_err_probe(dev, err: PTR_ERR(ptr: dsi),
2300	fmt: "failed to create dsi device\n");
2301
2302	tc->dsi = dsi;
2303	dsi->lanes = dsi_lanes;
2304	dsi->format = MIPI_DSI_FMT_RGB888;
2305	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2306	MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
2307
2308	ret = devm_mipi_dsi_attach(dev, dsi);
2309	if (ret < 0) {
2310	dev_err(dev, "failed to attach dsi to host: %d\n", ret);
2311	return ret;
2312	}
2313
2314	return 0;
2315	}
2316
2317	static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2318	{
2319	struct device *dev = tc->dev;
2320	struct drm_bridge *bridge;
2321	struct drm_panel *panel;
2322	int ret;
2323
2324	/* port@1 is the DPI input/output port */
2325	ret = drm_of_find_panel_or_bridge(np: dev->of_node, port: 1, endpoint: 0, panel: &panel, bridge: &bridge);
2326	if (ret && ret != -ENODEV)
2327	return dev_err_probe(dev, err: ret,
2328	fmt: "Could not find DPI panel or bridge\n");
2329
2330	if (panel) {
2331	bridge = devm_drm_panel_bridge_add(dev, panel);
2332	if (IS_ERR(ptr: bridge))
2333	return PTR_ERR(ptr: bridge);
2334	}
2335
2336	if (bridge) {
2337	tc->panel_bridge = bridge;
2338	tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2339
2340	return 0;
2341	}
2342
2343	return ret;
2344	}
2345
2346	static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2347	{
2348	struct device *dev = tc->dev;
2349	struct drm_panel *panel;
2350	int ret;
2351
2352	/* port@2 is the output port */
2353	ret = drm_of_find_panel_or_bridge(np: dev->of_node, port: 2, endpoint: 0, panel: &panel, NULL);
2354	if (ret && ret != -ENODEV)
2355	return dev_err_probe(dev, err: ret,
2356	fmt: "Could not find DSI panel or bridge\n");
2357
2358	if (panel) {
2359	struct drm_bridge *panel_bridge;
2360
2361	panel_bridge = devm_drm_panel_bridge_add(dev, panel);
2362	if (IS_ERR(ptr: panel_bridge))
2363	return PTR_ERR(ptr: panel_bridge);
2364
2365	tc->panel_bridge = panel_bridge;
2366	tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2367	} else {
2368	tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2369	}
2370
2371	if (tc->hpd_pin >= 0)
2372	tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2373	tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2374
2375	return 0;
2376	}
2377
2378	static enum tc_mode tc_probe_get_mode(struct device *dev)
2379	{
2380	struct of_endpoint endpoint;
2381	struct device_node *node = NULL;
2382	enum tc_mode mode = 0;
2383
2384	/*
2385	* Determine bridge configuration.
2386	*
2387	* Port allocation:
2388	* port@0 - DSI input
2389	* port@1 - DPI input/output
2390	* port@2 - eDP output
2391	*
2392	* Possible connections:
2393	* DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2394	* DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2395	* DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2396	*/
2397
2398	for_each_endpoint_of_node(dev->of_node, node) {
2399	of_graph_parse_endpoint(node, endpoint: &endpoint);
2400	if (endpoint.port > 2) {
2401	of_node_put(node);
2402	return -EINVAL;
2403	}
2404	mode |= BIT(endpoint.port);
2405	}
2406
2407	if (mode != mode_dpi_to_edp &&
2408	mode != mode_dpi_to_dp &&
2409	mode != mode_dsi_to_dpi &&
2410	mode != mode_dsi_to_edp &&
2411	mode != mode_dsi_to_dp) {
2412	dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
2413	return -EINVAL;
2414	}
2415
2416	return mode;
2417	}
2418
2419	static int tc_probe_bridge_endpoint(struct tc_data *tc, enum tc_mode mode)
2420	{
2421	struct device *dev = tc->dev;
2422	struct of_endpoint endpoint;
2423	struct device_node *node = NULL;
2424
2425	for_each_endpoint_of_node(dev->of_node, node) {
2426	of_graph_parse_endpoint(node, endpoint: &endpoint);
2427	if (endpoint.port == 2) {
2428	of_property_read_u8_array(np: node, propname: "toshiba,pre-emphasis",
2429	out_values: tc->pre_emphasis,
2430	ARRAY_SIZE(tc->pre_emphasis));
2431
2432	if (tc->pre_emphasis[0] < 0 || tc->pre_emphasis[0] > 2 ||
2433	tc->pre_emphasis[1] < 0 || tc->pre_emphasis[1] > 2) {
2434	dev_err(dev, "Incorrect Pre-Emphasis setting, use either 0=0dB 1=3.5dB 2=6dB\n");
2435	of_node_put(node);
2436	return -EINVAL;
2437	}
2438	}
2439	}
2440
2441	if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {
2442	tc->input_connector_dsi = false;
2443	return tc_probe_edp_bridge_endpoint(tc);
2444	} else if (mode == mode_dsi_to_dpi) {
2445	tc->input_connector_dsi = true;
2446	return tc_probe_dpi_bridge_endpoint(tc);
2447	} else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {
2448	tc->input_connector_dsi = true;
2449	return tc_probe_edp_bridge_endpoint(tc);
2450	}
2451
2452	/* Should never happen, mode was validated by tc_probe_get_mode() */
2453	return -EINVAL;
2454	}
2455
2456	static int tc_probe(struct i2c_client *client)
2457	{
2458	struct device *dev = &client->dev;
2459	const struct drm_bridge_funcs *funcs;
2460	struct tc_data *tc;
2461	int mode;
2462	int ret;
2463
2464	mode = tc_probe_get_mode(dev);
2465	funcs = (mode == mode_dsi_to_dpi) ? &tc_dpi_bridge_funcs : &tc_edp_bridge_funcs;
2466
2467	tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge, funcs);
2468	if (IS_ERR(ptr: tc))
2469	return PTR_ERR(ptr: tc);
2470
2471	tc->dev = dev;
2472
2473	ret = tc_probe_bridge_endpoint(tc, mode);
2474	if (ret)
2475	return ret;
2476
2477	tc->refclk = devm_clk_get_enabled(dev, id: "ref");
2478	if (IS_ERR(ptr: tc->refclk))
2479	return dev_err_probe(dev, err: PTR_ERR(ptr: tc->refclk),
2480	fmt: "Failed to get and enable the ref clk\n");
2481
2482	/* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
2483	usleep_range(min: 10, max: 15);
2484
2485	/* Shut down GPIO is optional */
2486	tc->sd_gpio = devm_gpiod_get_optional(dev, con_id: "shutdown", flags: GPIOD_OUT_HIGH);
2487	if (IS_ERR(ptr: tc->sd_gpio))
2488	return PTR_ERR(ptr: tc->sd_gpio);
2489
2490	if (tc->sd_gpio) {
2491	gpiod_set_value_cansleep(desc: tc->sd_gpio, value: 0);
2492	usleep_range(min: 5000, max: 10000);
2493	}
2494
2495	/* Reset GPIO is optional */
2496	tc->reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset", flags: GPIOD_OUT_LOW);
2497	if (IS_ERR(ptr: tc->reset_gpio))
2498	return PTR_ERR(ptr: tc->reset_gpio);
2499
2500	if (tc->reset_gpio) {
2501	gpiod_set_value_cansleep(desc: tc->reset_gpio, value: 1);
2502	usleep_range(min: 5000, max: 10000);
2503	}
2504
2505	tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2506	if (IS_ERR(ptr: tc->regmap)) {
2507	ret = PTR_ERR(ptr: tc->regmap);
2508	dev_err(dev, "Failed to initialize regmap: %d\n", ret);
2509	return ret;
2510	}
2511
2512	ret = of_property_read_u32(np: dev->of_node, propname: "toshiba,hpd-pin",
2513	out_value: &tc->hpd_pin);
2514	if (ret) {
2515	tc->hpd_pin = -ENODEV;
2516	} else {
2517	if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2518	dev_err(dev, "failed to parse HPD number\n");
2519	return -EINVAL;
2520	}
2521	}
2522
2523	if (client->irq > 0) {
2524	/* enable SysErr */
2525	regmap_write(map: tc->regmap, INTCTL_G, INT_SYSERR);
2526
2527	ret = devm_request_threaded_irq(dev, irq: client->irq,
2528	NULL, thread_fn: tc_irq_handler,
2529	IRQF_ONESHOT,
2530	devname: "tc358767-irq", dev_id: tc);
2531	if (ret) {
2532	dev_err(dev, "failed to register dp interrupt\n");
2533	return ret;
2534	}
2535
2536	tc->have_irq = true;
2537	}
2538
2539	ret = regmap_read(map: tc->regmap, TC_IDREG, val: &tc->rev);
2540	if (ret) {
2541	dev_err(tc->dev, "can not read device ID: %d\n", ret);
2542	return ret;
2543	}
2544
2545	if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2546	dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2547	return -EINVAL;
2548	}
2549
2550	tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2551
2552	if (!tc->reset_gpio) {
2553	/*
2554	* If the reset pin isn't present, do a software reset. It isn't
2555	* as thorough as the hardware reset, as we can't reset the I2C
2556	* communication block for obvious reasons, but it's getting the
2557	* chip into a defined state.
2558	*/
2559	regmap_update_bits(map: tc->regmap, SYSRSTENB,
2560	ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2561	val: 0);
2562	regmap_update_bits(map: tc->regmap, SYSRSTENB,
2563	ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2564	ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
2565	usleep_range(min: 5000, max: 10000);
2566	}
2567
2568	if (tc->hpd_pin >= 0) {
2569	u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2570	u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2571
2572	/* Set LCNT to 2ms */
2573	regmap_write(map: tc->regmap, reg: lcnt_reg,
2574	val: clk_get_rate(clk: tc->refclk) * 2 / 1000);
2575	/* We need the "alternate" mode for HPD */
2576	regmap_write(map: tc->regmap, GPIOM, BIT(tc->hpd_pin));
2577
2578	if (tc->have_irq) {
2579	/* enable H & LC */
2580	regmap_update_bits(map: tc->regmap, INTCTL_G, mask: h_lc, val: h_lc);
2581	}
2582	}
2583
2584	if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2585	ret = tc_aux_link_setup(tc);
2586	if (ret)
2587	return ret;
2588	}
2589
2590	tc->bridge.of_node = dev->of_node;
2591	drm_bridge_add(bridge: &tc->bridge);
2592
2593	i2c_set_clientdata(client, data: tc);
2594
2595	if (tc->input_connector_dsi) { /* DSI input */
2596	ret = tc_mipi_dsi_host_attach(tc);
2597	if (ret) {
2598	drm_bridge_remove(bridge: &tc->bridge);
2599	return dev_err_probe(dev, err: ret, fmt: "Failed to attach DSI host\n");
2600	}
2601	}
2602
2603	return 0;
2604	}
2605
2606	static void tc_remove(struct i2c_client *client)
2607	{
2608	struct tc_data *tc = i2c_get_clientdata(client);
2609
2610	drm_bridge_remove(bridge: &tc->bridge);
2611	}
2612
2613	static const struct i2c_device_id tc358767_i2c_ids[] = {
2614	{ "tc358767" },
2615	{ }
2616	};
2617	MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
2618
2619	static const struct of_device_id tc358767_of_ids[] = {
2620	{ .compatible = "toshiba,tc358767", },
2621	{ }
2622	};
2623	MODULE_DEVICE_TABLE(of, tc358767_of_ids);
2624
2625	static struct i2c_driver tc358767_driver = {
2626	.driver = {
2627	.name = "tc358767",
2628	.of_match_table = tc358767_of_ids,
2629	},
2630	.id_table = tc358767_i2c_ids,
2631	.probe = tc_probe,
2632	.remove = tc_remove,
2633	};
2634	module_i2c_driver(tc358767_driver);
2635
2636	MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
2637	MODULE_DESCRIPTION("tc358767 eDP encoder driver");
2638	MODULE_LICENSE("GPL");
2639