1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016 MediaTek Inc.
4 */
5
6#include <linux/delay.h>
7#include <linux/err.h>
8#include <linux/gpio/consumer.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/of_graph.h>
12#include <linux/pm_runtime.h>
13#include <linux/regmap.h>
14#include <linux/regulator/consumer.h>
15
16#include <drm/display/drm_dp_aux_bus.h>
17#include <drm/display/drm_dp_helper.h>
18#include <drm/drm_atomic_state_helper.h>
19#include <drm/drm_bridge.h>
20#include <drm/drm_edid.h>
21#include <drm/drm_mipi_dsi.h>
22#include <drm/drm_of.h>
23#include <drm/drm_print.h>
24
25#define PAGE0_AUXCH_CFG3 0x76
26#define AUXCH_CFG3_RESET 0xff
27#define PAGE0_SWAUX_ADDR_7_0 0x7d
28#define PAGE0_SWAUX_ADDR_15_8 0x7e
29#define PAGE0_SWAUX_ADDR_23_16 0x7f
30#define SWAUX_ADDR_MASK GENMASK(19, 0)
31#define PAGE0_SWAUX_LENGTH 0x80
32#define SWAUX_LENGTH_MASK GENMASK(3, 0)
33#define SWAUX_NO_PAYLOAD BIT(7)
34#define PAGE0_SWAUX_WDATA 0x81
35#define PAGE0_SWAUX_RDATA 0x82
36#define PAGE0_SWAUX_CTRL 0x83
37#define SWAUX_SEND BIT(0)
38#define PAGE0_SWAUX_STATUS 0x84
39#define SWAUX_M_MASK GENMASK(4, 0)
40#define SWAUX_STATUS_MASK GENMASK(7, 5)
41#define SWAUX_STATUS_NACK (0x1 << 5)
42#define SWAUX_STATUS_DEFER (0x2 << 5)
43#define SWAUX_STATUS_ACKM (0x3 << 5)
44#define SWAUX_STATUS_INVALID (0x4 << 5)
45#define SWAUX_STATUS_I2C_NACK (0x5 << 5)
46#define SWAUX_STATUS_I2C_DEFER (0x6 << 5)
47#define SWAUX_STATUS_TIMEOUT (0x7 << 5)
48
49#define PAGE2_GPIO_H 0xa7
50#define PS_GPIO9 BIT(1)
51#define PAGE2_I2C_BYPASS 0xea
52#define I2C_BYPASS_EN 0xd0
53#define PAGE2_MCS_EN 0xf3
54#define MCS_EN BIT(0)
55
56#define PAGE3_SET_ADD 0xfe
57#define VDO_CTL_ADD 0x13
58#define VDO_DIS 0x18
59#define VDO_EN 0x1c
60
61#define NUM_MIPI_LANES 4
62
63#define COMMON_PS8640_REGMAP_CONFIG \
64 .reg_bits = 8, \
65 .val_bits = 8, \
66 .cache_type = REGCACHE_NONE
67
68/*
69 * PS8640 uses multiple addresses:
70 * page[0]: for DP control
71 * page[1]: for VIDEO Bridge
72 * page[2]: for control top
73 * page[3]: for DSI Link Control1
74 * page[4]: for MIPI Phy
75 * page[5]: for VPLL
76 * page[6]: for DSI Link Control2
77 * page[7]: for SPI ROM mapping
78 */
79enum page_addr_offset {
80 PAGE0_DP_CNTL = 0,
81 PAGE1_VDO_BDG,
82 PAGE2_TOP_CNTL,
83 PAGE3_DSI_CNTL1,
84 PAGE4_MIPI_PHY,
85 PAGE5_VPLL,
86 PAGE6_DSI_CNTL2,
87 PAGE7_SPI_CNTL,
88 MAX_DEVS
89};
90
91enum ps8640_vdo_control {
92 DISABLE = VDO_DIS,
93 ENABLE = VDO_EN,
94};
95
96struct ps8640 {
97 struct drm_bridge bridge;
98 struct drm_bridge *panel_bridge;
99 struct drm_dp_aux aux;
100 struct mipi_dsi_device *dsi;
101 struct i2c_client *page[MAX_DEVS];
102 struct regmap *regmap[MAX_DEVS];
103 struct regulator_bulk_data supplies[2];
104 struct gpio_desc *gpio_reset;
105 struct gpio_desc *gpio_powerdown;
106 struct device_link *link;
107 bool pre_enabled;
108 bool need_post_hpd_delay;
109 struct mutex aux_lock;
110};
111
112static const struct regmap_config ps8640_regmap_config[] = {
113 [PAGE0_DP_CNTL] = {
114 COMMON_PS8640_REGMAP_CONFIG,
115 .max_register = 0xbf,
116 },
117 [PAGE1_VDO_BDG] = {
118 COMMON_PS8640_REGMAP_CONFIG,
119 .max_register = 0xff,
120 },
121 [PAGE2_TOP_CNTL] = {
122 COMMON_PS8640_REGMAP_CONFIG,
123 .max_register = 0xff,
124 },
125 [PAGE3_DSI_CNTL1] = {
126 COMMON_PS8640_REGMAP_CONFIG,
127 .max_register = 0xff,
128 },
129 [PAGE4_MIPI_PHY] = {
130 COMMON_PS8640_REGMAP_CONFIG,
131 .max_register = 0xff,
132 },
133 [PAGE5_VPLL] = {
134 COMMON_PS8640_REGMAP_CONFIG,
135 .max_register = 0x7f,
136 },
137 [PAGE6_DSI_CNTL2] = {
138 COMMON_PS8640_REGMAP_CONFIG,
139 .max_register = 0xff,
140 },
141 [PAGE7_SPI_CNTL] = {
142 COMMON_PS8640_REGMAP_CONFIG,
143 .max_register = 0xff,
144 },
145};
146
147static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
148{
149 return container_of(e, struct ps8640, bridge);
150}
151
152static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
153{
154 return container_of(aux, struct ps8640, aux);
155}
156
157static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
158{
159 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
160 int status;
161 int ret;
162
163 /*
164 * Apparently something about the firmware in the chip signals that
165 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
166 * actually connected to GPIO9).
167 */
168 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
169 status & PS_GPIO9, 20000, wait_us);
170
171 /*
172 * The first time we see HPD go high after a reset we delay an extra
173 * 50 ms. The best guess is that the MCU is doing "stuff" during this
174 * time (maybe talking to the panel) and we don't want to interrupt it.
175 *
176 * No locking is done around "need_post_hpd_delay". If we're here we
177 * know we're holding a PM Runtime reference and the only other place
178 * that touches this is PM Runtime resume.
179 */
180 if (!ret && ps_bridge->need_post_hpd_delay) {
181 ps_bridge->need_post_hpd_delay = false;
182 msleep(msecs: 50);
183 }
184
185 return ret;
186}
187
188static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
189{
190 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
191 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
192 int ret;
193
194 /*
195 * Note that this function is called by code that has already powered
196 * the panel. We have to power ourselves up but we don't need to worry
197 * about powering the panel.
198 */
199 pm_runtime_get_sync(dev);
200 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
201 pm_runtime_mark_last_busy(dev);
202 pm_runtime_put_autosuspend(dev);
203
204 return ret;
205}
206
207static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
208 struct drm_dp_aux_msg *msg)
209{
210 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
211 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
212 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
213 size_t len = msg->size;
214 unsigned int data;
215 unsigned int base;
216 int ret;
217 u8 request = msg->request &
218 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
219 u8 *buf = msg->buffer;
220 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
221 u8 i;
222 bool is_native_aux = false;
223
224 if (len > DP_AUX_MAX_PAYLOAD_BYTES)
225 return -EINVAL;
226
227 if (msg->address & ~SWAUX_ADDR_MASK)
228 return -EINVAL;
229
230 switch (request) {
231 case DP_AUX_NATIVE_WRITE:
232 case DP_AUX_NATIVE_READ:
233 is_native_aux = true;
234 fallthrough;
235 case DP_AUX_I2C_WRITE:
236 case DP_AUX_I2C_READ:
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
243 if (ret) {
244 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
245 ret);
246 return ret;
247 }
248
249 /* Assume it's good */
250 msg->reply = 0;
251
252 base = PAGE0_SWAUX_ADDR_7_0;
253 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
254 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
255 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
256 (msg->request << 4);
257 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
258 ((len - 1) & SWAUX_LENGTH_MASK);
259
260 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, val: addr_len,
261 ARRAY_SIZE(addr_len));
262
263 if (len && (request == DP_AUX_NATIVE_WRITE ||
264 request == DP_AUX_I2C_WRITE)) {
265 /* Write to the internal FIFO buffer */
266 for (i = 0; i < len; i++) {
267 ret = regmap_write(map, PAGE0_SWAUX_WDATA, val: buf[i]);
268 if (ret) {
269 DRM_DEV_ERROR(dev,
270 "failed to write WDATA: %d\n",
271 ret);
272 return ret;
273 }
274 }
275 }
276
277 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
278
279 /* Zero delay loop because i2c transactions are slow already */
280 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
281 !(data & SWAUX_SEND), 0, 50 * 1000);
282
283 regmap_read(map, PAGE0_SWAUX_STATUS, val: &data);
284 if (ret) {
285 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
286 ret);
287 return ret;
288 }
289
290 switch (data & SWAUX_STATUS_MASK) {
291 case SWAUX_STATUS_NACK:
292 case SWAUX_STATUS_I2C_NACK:
293 /*
294 * The programming guide is not clear about whether a I2C NACK
295 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
296 * we handle both cases together.
297 */
298 if (is_native_aux)
299 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
300 else
301 msg->reply |= DP_AUX_I2C_REPLY_NACK;
302
303 fallthrough;
304 case SWAUX_STATUS_ACKM:
305 len = data & SWAUX_M_MASK;
306 break;
307 case SWAUX_STATUS_DEFER:
308 case SWAUX_STATUS_I2C_DEFER:
309 if (is_native_aux)
310 msg->reply |= DP_AUX_NATIVE_REPLY_DEFER;
311 else
312 msg->reply |= DP_AUX_I2C_REPLY_DEFER;
313 len = data & SWAUX_M_MASK;
314 break;
315 case SWAUX_STATUS_INVALID:
316 return -EOPNOTSUPP;
317 case SWAUX_STATUS_TIMEOUT:
318 return -ETIMEDOUT;
319 }
320
321 if (len && (request == DP_AUX_NATIVE_READ ||
322 request == DP_AUX_I2C_READ)) {
323 /* Read from the internal FIFO buffer */
324 for (i = 0; i < len; i++) {
325 ret = regmap_read(map, PAGE0_SWAUX_RDATA, val: &data);
326 if (ret) {
327 DRM_DEV_ERROR(dev,
328 "failed to read RDATA: %d\n",
329 ret);
330 return ret;
331 }
332
333 if (i < msg->size)
334 buf[i] = data;
335 }
336 }
337
338 return min(len, msg->size);
339}
340
341static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
342 struct drm_dp_aux_msg *msg)
343{
344 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
345 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
346 int ret;
347
348 mutex_lock(&ps_bridge->aux_lock);
349 pm_runtime_get_sync(dev);
350 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us: 200 * 1000);
351 if (ret) {
352 pm_runtime_put_sync_suspend(dev);
353 goto exit;
354 }
355 ret = ps8640_aux_transfer_msg(aux, msg);
356 pm_runtime_mark_last_busy(dev);
357 pm_runtime_put_autosuspend(dev);
358
359exit:
360 mutex_unlock(lock: &ps_bridge->aux_lock);
361
362 return ret;
363}
364
365static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
366 const enum ps8640_vdo_control ctrl)
367{
368 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
369 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
370 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
371 int ret;
372
373 ret = regmap_bulk_write(map, PAGE3_SET_ADD,
374 val: vdo_ctrl_buf, val_count: sizeof(vdo_ctrl_buf));
375
376 if (ret < 0)
377 dev_err(dev, "failed to %sable VDO: %d\n",
378 ctrl == ENABLE ? "en" : "dis", ret);
379}
380
381static int __maybe_unused ps8640_resume(struct device *dev)
382{
383 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
384 int ret;
385
386 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
387 consumers: ps_bridge->supplies);
388 if (ret < 0) {
389 dev_err(dev, "cannot enable regulators %d\n", ret);
390 return ret;
391 }
392
393 gpiod_set_value(desc: ps_bridge->gpio_powerdown, value: 0);
394 gpiod_set_value(desc: ps_bridge->gpio_reset, value: 1);
395 usleep_range(min: 2000, max: 2500);
396 gpiod_set_value(desc: ps_bridge->gpio_reset, value: 0);
397 /* Double reset for T4 and T5 */
398 msleep(msecs: 50);
399 gpiod_set_value(desc: ps_bridge->gpio_reset, value: 1);
400 msleep(msecs: 50);
401 gpiod_set_value(desc: ps_bridge->gpio_reset, value: 0);
402
403 /* We just reset things, so we need a delay after the first HPD */
404 ps_bridge->need_post_hpd_delay = true;
405
406 /*
407 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
408 * this is truly necessary since the MCU will already signal that
409 * things are "good to go" by signaling HPD on "gpio 9". See
410 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
411 * just in case.
412 */
413 msleep(msecs: 200);
414
415 return 0;
416}
417
418static int __maybe_unused ps8640_suspend(struct device *dev)
419{
420 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
421 int ret;
422
423 gpiod_set_value(desc: ps_bridge->gpio_reset, value: 1);
424 gpiod_set_value(desc: ps_bridge->gpio_powerdown, value: 1);
425 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
426 consumers: ps_bridge->supplies);
427 if (ret < 0)
428 dev_err(dev, "cannot disable regulators %d\n", ret);
429
430 return ret;
431}
432
433static const struct dev_pm_ops ps8640_pm_ops = {
434 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
435 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
436 pm_runtime_force_resume)
437};
438
439static void ps8640_atomic_pre_enable(struct drm_bridge *bridge,
440 struct drm_atomic_state *state)
441{
442 struct ps8640 *ps_bridge = bridge_to_ps8640(e: bridge);
443 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
444 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
445 int ret;
446
447 pm_runtime_get_sync(dev);
448 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us: 200 * 1000);
449 if (ret < 0)
450 dev_warn(dev, "HPD didn't go high: %d\n", ret);
451
452 /*
453 * The Manufacturer Command Set (MCS) is a device dependent interface
454 * intended for factory programming of the display module default
455 * parameters. Once the display module is configured, the MCS shall be
456 * disabled by the manufacturer. Once disabled, all MCS commands are
457 * ignored by the display interface.
458 */
459
460 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, val: 0);
461 if (ret < 0)
462 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
463
464 /* Switch access edp panel's edid through i2c */
465 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
466 if (ret < 0)
467 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
468
469 ps8640_bridge_vdo_control(ps_bridge, ctrl: ENABLE);
470
471 ps_bridge->pre_enabled = true;
472}
473
474static void ps8640_atomic_post_disable(struct drm_bridge *bridge,
475 struct drm_atomic_state *state)
476{
477 struct ps8640 *ps_bridge = bridge_to_ps8640(e: bridge);
478
479 ps_bridge->pre_enabled = false;
480
481 ps8640_bridge_vdo_control(ps_bridge, ctrl: DISABLE);
482
483 /*
484 * The bridge seems to expect everything to be power cycled at the
485 * disable process, so grab a lock here to make sure
486 * ps8640_aux_transfer() is not holding a runtime PM reference and
487 * preventing the bridge from suspend.
488 */
489 mutex_lock(&ps_bridge->aux_lock);
490
491 pm_runtime_put_sync_suspend(dev: &ps_bridge->page[PAGE0_DP_CNTL]->dev);
492
493 mutex_unlock(lock: &ps_bridge->aux_lock);
494}
495
496static int ps8640_bridge_attach(struct drm_bridge *bridge,
497 struct drm_encoder *encoder,
498 enum drm_bridge_attach_flags flags)
499{
500 struct ps8640 *ps_bridge = bridge_to_ps8640(e: bridge);
501 struct device *dev = &ps_bridge->page[0]->dev;
502 int ret;
503
504 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
505 return -EINVAL;
506
507 ps_bridge->aux.drm_dev = bridge->dev;
508 ret = drm_dp_aux_register(aux: &ps_bridge->aux);
509 if (ret) {
510 dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
511 return ret;
512 }
513
514 ps_bridge->link = device_link_add(consumer: bridge->dev->dev, supplier: dev, DL_FLAG_STATELESS);
515 if (!ps_bridge->link) {
516 dev_err(dev, "failed to create device link");
517 ret = -EINVAL;
518 goto err_devlink;
519 }
520
521 /* Attach the panel-bridge to the dsi bridge */
522 ret = drm_bridge_attach(encoder, bridge: ps_bridge->panel_bridge,
523 previous: &ps_bridge->bridge, flags);
524 if (ret)
525 goto err_bridge_attach;
526
527 return 0;
528
529err_bridge_attach:
530 device_link_del(link: ps_bridge->link);
531err_devlink:
532 drm_dp_aux_unregister(aux: &ps_bridge->aux);
533
534 return ret;
535}
536
537static void ps8640_bridge_detach(struct drm_bridge *bridge)
538{
539 struct ps8640 *ps_bridge = bridge_to_ps8640(e: bridge);
540
541 drm_dp_aux_unregister(aux: &ps_bridge->aux);
542 if (ps_bridge->link)
543 device_link_del(link: ps_bridge->link);
544}
545
546static void ps8640_runtime_disable(void *data)
547{
548 pm_runtime_dont_use_autosuspend(dev: data);
549 pm_runtime_disable(dev: data);
550}
551
552static const struct drm_bridge_funcs ps8640_bridge_funcs = {
553 .attach = ps8640_bridge_attach,
554 .detach = ps8640_bridge_detach,
555 .atomic_post_disable = ps8640_atomic_post_disable,
556 .atomic_pre_enable = ps8640_atomic_pre_enable,
557 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
558 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
559 .atomic_reset = drm_atomic_helper_bridge_reset,
560};
561
562static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
563{
564 struct device_node *in_ep, *dsi_node;
565 struct mipi_dsi_device *dsi;
566 struct mipi_dsi_host *host;
567 const struct mipi_dsi_device_info info = { .type = "ps8640",
568 .channel = 0,
569 .node = NULL,
570 };
571
572 /* port@0 is ps8640 dsi input port */
573 in_ep = of_graph_get_endpoint_by_regs(parent: dev->of_node, port_reg: 0, reg: -1);
574 if (!in_ep)
575 return -ENODEV;
576
577 dsi_node = of_graph_get_remote_port_parent(node: in_ep);
578 of_node_put(node: in_ep);
579 if (!dsi_node)
580 return -ENODEV;
581
582 host = of_find_mipi_dsi_host_by_node(node: dsi_node);
583 of_node_put(node: dsi_node);
584 if (!host)
585 return -EPROBE_DEFER;
586
587 dsi = devm_mipi_dsi_device_register_full(dev, host, info: &info);
588 if (IS_ERR(ptr: dsi)) {
589 dev_err(dev, "failed to create dsi device\n");
590 return PTR_ERR(ptr: dsi);
591 }
592
593 ps_bridge->dsi = dsi;
594
595 dsi->host = host;
596 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
597 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
598 dsi->format = MIPI_DSI_FMT_RGB888;
599 dsi->lanes = NUM_MIPI_LANES;
600
601 return 0;
602}
603
604static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
605{
606 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
607 struct device *dev = aux->dev;
608 struct device_node *np = dev->of_node;
609 int ret;
610
611 /*
612 * NOTE about returning -EPROBE_DEFER from this function: if we
613 * return an error (most relevant to -EPROBE_DEFER) it will only
614 * be passed out to ps8640_probe() if it called this directly (AKA the
615 * panel isn't under the "aux-bus" node). That should be fine because
616 * if the panel is under "aux-bus" it's guaranteed to have probed by
617 * the time this function has been called.
618 */
619
620 /* port@1 is ps8640 output port */
621 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, node: np, port: 1, endpoint: 0);
622 if (IS_ERR(ptr: ps_bridge->panel_bridge))
623 return PTR_ERR(ptr: ps_bridge->panel_bridge);
624
625 ret = devm_drm_bridge_add(dev, bridge: &ps_bridge->bridge);
626 if (ret)
627 return ret;
628
629 return devm_mipi_dsi_attach(dev, dsi: ps_bridge->dsi);
630}
631
632static int ps8640_probe(struct i2c_client *client)
633{
634 struct device *dev = &client->dev;
635 struct ps8640 *ps_bridge;
636 int ret;
637 u32 i;
638
639 ps_bridge = devm_drm_bridge_alloc(dev, struct ps8640, bridge,
640 &ps8640_bridge_funcs);
641 if (IS_ERR(ptr: ps_bridge))
642 return PTR_ERR(ptr: ps_bridge);
643
644 mutex_init(&ps_bridge->aux_lock);
645
646 ps_bridge->supplies[0].supply = "vdd12";
647 ps_bridge->supplies[1].supply = "vdd33";
648 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
649 consumers: ps_bridge->supplies);
650 if (ret)
651 return ret;
652
653 ps_bridge->gpio_powerdown = devm_gpiod_get(dev: &client->dev, con_id: "powerdown",
654 flags: GPIOD_OUT_HIGH);
655 if (IS_ERR(ptr: ps_bridge->gpio_powerdown))
656 return PTR_ERR(ptr: ps_bridge->gpio_powerdown);
657
658 /*
659 * Assert the reset to avoid the bridge being initialized prematurely
660 */
661 ps_bridge->gpio_reset = devm_gpiod_get(dev: &client->dev, con_id: "reset",
662 flags: GPIOD_OUT_HIGH);
663 if (IS_ERR(ptr: ps_bridge->gpio_reset))
664 return PTR_ERR(ptr: ps_bridge->gpio_reset);
665
666 ps_bridge->bridge.of_node = dev->of_node;
667 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
668
669 /*
670 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
671 * we want to get them out of the way sooner.
672 */
673 ret = ps8640_bridge_get_dsi_resources(dev: &client->dev, ps_bridge);
674 if (ret)
675 return ret;
676
677 ps_bridge->page[PAGE0_DP_CNTL] = client;
678
679 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
680 if (IS_ERR(ptr: ps_bridge->regmap[PAGE0_DP_CNTL]))
681 return PTR_ERR(ptr: ps_bridge->regmap[PAGE0_DP_CNTL]);
682
683 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
684 ps_bridge->page[i] = devm_i2c_new_dummy_device(dev: &client->dev,
685 adap: client->adapter,
686 address: client->addr + i);
687 if (IS_ERR(ptr: ps_bridge->page[i]))
688 return PTR_ERR(ptr: ps_bridge->page[i]);
689
690 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
691 ps8640_regmap_config + i);
692 if (IS_ERR(ptr: ps_bridge->regmap[i]))
693 return PTR_ERR(ptr: ps_bridge->regmap[i]);
694 }
695
696 i2c_set_clientdata(client, data: ps_bridge);
697
698 ps_bridge->aux.name = "parade-ps8640-aux";
699 ps_bridge->aux.dev = dev;
700 ps_bridge->aux.transfer = ps8640_aux_transfer;
701 ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
702 drm_dp_aux_init(aux: &ps_bridge->aux);
703
704 pm_runtime_enable(dev);
705 /*
706 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
707 * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure
708 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
709 * during EDID read (~20ms in my experiment) and in between the last
710 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
711 * (~100ms in my experiment).
712 */
713 pm_runtime_set_autosuspend_delay(dev, delay: 2000);
714 pm_runtime_use_autosuspend(dev);
715 pm_suspend_ignore_children(dev, enable: true);
716 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
717 if (ret)
718 return ret;
719
720 ret = devm_of_dp_aux_populate_bus(aux: &ps_bridge->aux, done_probing: ps8640_bridge_link_panel);
721
722 /*
723 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
724 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
725 * the function is allowed to -EPROBE_DEFER.
726 */
727 if (ret == -ENODEV)
728 return ps8640_bridge_link_panel(aux: &ps_bridge->aux);
729
730 return ret;
731}
732
733static const struct of_device_id ps8640_match[] = {
734 { .compatible = "parade,ps8640" },
735 { }
736};
737MODULE_DEVICE_TABLE(of, ps8640_match);
738
739static struct i2c_driver ps8640_driver = {
740 .probe = ps8640_probe,
741 .driver = {
742 .name = "ps8640",
743 .of_match_table = ps8640_match,
744 .pm = &ps8640_pm_ops,
745 },
746};
747module_i2c_driver(ps8640_driver);
748
749MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
750MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
751MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
752MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
753MODULE_LICENSE("GPL v2");
754

source code of linux/drivers/gpu/drm/bridge/parade-ps8640.c