1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2	/*
3	* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4	*/
5	#include <linux/bits.h>
6	#include <linux/debugfs.h>
7	#include <linux/delay.h>
8	#include <linux/device.h>
9	#include <linux/err.h>
10	#include <linux/extcon.h>
11	#include <linux/fs.h>
12	#include <linux/gpio/consumer.h>
13	#include <linux/i2c.h>
14	#include <linux/interrupt.h>
15	#include <linux/kernel.h>
16	#include <linux/module.h>
17	#include <linux/pm_runtime.h>
18	#include <linux/regmap.h>
19	#include <linux/regulator/consumer.h>
20	#include <linux/types.h>
21	#include <linux/wait.h>
22	#include <linux/bitfield.h>
23
24	#include <crypto/sha1.h>
25
26	#include <drm/display/drm_dp_helper.h>
27	#include <drm/display/drm_hdcp_helper.h>
28	#include <drm/drm_atomic_helper.h>
29	#include <drm/drm_bridge.h>
30	#include <drm/drm_crtc.h>
31	#include <drm/drm_edid.h>
32	#include <drm/drm_print.h>
33	#include <drm/drm_probe_helper.h>
34
35	#include <sound/hdmi-codec.h>
36
37	#define REG_IC_VER 0x04
38
39	#define REG_RESET_CTRL 0x05
40	#define VIDEO_RESET BIT(0)
41	#define AUDIO_RESET BIT(1)
42	#define ALL_LOGIC_RESET BIT(2)
43	#define AUX_RESET BIT(3)
44	#define HDCP_RESET BIT(4)
45
46	#define INT_STATUS_01 0x06
47	#define INT_MASK_01 0x09
48	#define INT_HPD_CHANGE 0
49	#define INT_RECEIVE_HPD_IRQ 1
50	#define INT_SCDT_CHANGE 2
51	#define INT_HDCP_FAIL 3
52	#define INT_HDCP_DONE 4
53	#define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
54	#define BIT_INT_HPD INT_HPD_CHANGE
55	#define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
56	#define BIT_INT_SCDT INT_SCDT_CHANGE
57	#define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
58	#define BIT_INT_HDCP_DONE INT_HDCP_DONE
59
60	#define INT_STATUS_02 0x07
61	#define INT_MASK_02 0x0A
62	#define INT_AUX_CMD_FAIL 0
63	#define INT_HDCP_KSV_CHECK 1
64	#define INT_AUDIO_FIFO_ERROR 2
65	#define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
66	#define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
67	#define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
68
69	#define INT_STATUS_03 0x08
70	#define INT_MASK_03 0x0B
71	#define INT_LINK_TRAIN_FAIL 4
72	#define INT_VID_FIFO_ERROR 5
73	#define INT_IO_LATCH_FIFO_OVERFLOW 7
74	#define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
75	#define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
76	#define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
77
78	#define REG_SYSTEM_STS 0x0D
79	#define INT_STS BIT(0)
80	#define HPD_STS BIT(1)
81	#define VIDEO_STB BIT(2)
82
83	#define REG_LINK_TRAIN_STS 0x0E
84	#define LINK_STATE_CR BIT(2)
85	#define LINK_STATE_EQ BIT(3)
86	#define LINK_STATE_NORP BIT(4)
87
88	#define REG_BANK_SEL 0x0F
89	#define REG_CLK_CTRL0 0x10
90	#define M_PCLK_DELAY 0x03
91
92	#define REG_AUX_OPT 0x11
93	#define AUX_AUTO_RST BIT(0)
94	#define AUX_FIX_FREQ BIT(3)
95
96	#define REG_DATA_CTRL0 0x12
97	#define VIDEO_LATCH_EDGE BIT(4)
98	#define ENABLE_PCLK_COUNTER BIT(7)
99
100	#define REG_PCLK_COUNTER_VALUE 0x13
101
102	#define REG_501_FIFO_CTRL 0x15
103	#define RST_501_FIFO BIT(1)
104
105	#define REG_TRAIN_CTRL0 0x16
106	#define FORCE_LBR BIT(0)
107	#define LANE_COUNT_MASK 0x06
108	#define LANE_SWAP BIT(3)
109	#define SPREAD_AMP_5 BIT(4)
110	#define FORCE_CR_DONE BIT(5)
111	#define FORCE_EQ_DONE BIT(6)
112
113	#define REG_TRAIN_CTRL1 0x17
114	#define AUTO_TRAIN BIT(0)
115	#define MANUAL_TRAIN BIT(1)
116	#define FORCE_RETRAIN BIT(2)
117
118	#define REG_AUX_CTRL 0x23
119	#define CLR_EDID_FIFO BIT(0)
120	#define AUX_USER_MODE BIT(1)
121	#define AUX_NO_SEGMENT_WR BIT(6)
122	#define AUX_EN_FIFO_READ BIT(7)
123
124	#define REG_AUX_ADR_0_7 0x24
125	#define REG_AUX_ADR_8_15 0x25
126	#define REG_AUX_ADR_16_19 0x26
127	#define REG_AUX_OUT_DATA0 0x27
128
129	#define REG_AUX_CMD_REQ 0x2B
130	#define M_AUX_REQ_CMD 0x0F
131	#define AUX_BUSY BIT(5)
132
133	#define REG_AUX_DATA_0_7 0x2C
134	#define REG_AUX_DATA_8_15 0x2D
135	#define REG_AUX_DATA_16_23 0x2E
136	#define REG_AUX_DATA_24_31 0x2F
137
138	#define REG_AUX_DATA_FIFO 0x2F
139
140	#define REG_AUX_ERROR_STS 0x9F
141	#define M_AUX_REQ_FAIL 0x03
142
143	#define REG_HDCP_CTRL1 0x38
144	#define HDCP_CP_ENABLE BIT(0)
145
146	#define REG_HDCP_TRIGGER 0x39
147	#define HDCP_TRIGGER_START BIT(0)
148	#define HDCP_TRIGGER_CPIRQ BIT(1)
149	#define HDCP_TRIGGER_KSV_DONE BIT(4)
150	#define HDCP_TRIGGER_KSV_FAIL BIT(5)
151
152	#define REG_HDCP_CTRL2 0x3A
153	#define HDCP_AN_SEL BIT(0)
154	#define HDCP_AN_GEN BIT(1)
155	#define HDCP_HW_HPDIRQ_ACT BIT(2)
156	#define HDCP_EN_M0_READ BIT(5)
157
158	#define REG_M0_0_7 0x4C
159	#define REG_AN_0_7 0x4C
160	#define REG_SP_CTRL0 0x58
161	#define REG_IP_CTRL1 0x59
162	#define REG_IP_CTRL2 0x5A
163
164	#define REG_LINK_DRV 0x5C
165	#define DRV_HS BIT(1)
166
167	#define REG_DRV_LN_DATA_SEL 0x5D
168
169	#define REG_AUX 0x5E
170
171	#define REG_VID_BUS_CTRL0 0x60
172	#define IN_DDR BIT(2)
173	#define DDR_CD (0x01 << 6)
174
175	#define REG_VID_BUS_CTRL1 0x61
176	#define TX_FIFO_RESET BIT(1)
177
178	#define REG_INPUT_CTRL 0xA0
179	#define INPUT_HSYNC_POL BIT(0)
180	#define INPUT_VSYNC_POL BIT(2)
181	#define INPUT_INTERLACED BIT(4)
182
183	#define REG_INPUT_HTOTAL 0xA1
184	#define REG_INPUT_HACTIVE_START 0xA3
185	#define REG_INPUT_HACTIVE_WIDTH 0xA5
186	#define REG_INPUT_HFRONT_PORCH 0xA7
187	#define REG_INPUT_HSYNC_WIDTH 0xA9
188	#define REG_INPUT_VTOTAL 0xAB
189	#define REG_INPUT_VACTIVE_START 0xAD
190	#define REG_INPUT_VACTIVE_WIDTH 0xAF
191	#define REG_INPUT_VFRONT_PORCH 0xB1
192	#define REG_INPUT_VSYNC_WIDTH 0xB3
193
194	#define REG_AUDIO_SRC_CTRL 0xB8
195	#define M_AUDIO_I2S_EN 0x0F
196	#define EN_I2S0 BIT(0)
197	#define EN_I2S1 BIT(1)
198	#define EN_I2S2 BIT(2)
199	#define EN_I2S3 BIT(3)
200	#define AUDIO_FIFO_RESET BIT(7)
201
202	#define REG_AUDIO_FMT 0xB9
203	#define REG_AUDIO_FIFO_SEL 0xBA
204
205	#define REG_AUDIO_CTRL0 0xBB
206	#define AUDIO_FULL_PKT BIT(4)
207	#define AUDIO_16B_BOUND BIT(5)
208
209	#define REG_AUDIO_CTRL1 0xBC
210	#define REG_AUDIO_INPUT_FREQ 0xBE
211
212	#define REG_IEC958_STS0 0xBF
213	#define REG_IEC958_STS1 0xC0
214	#define REG_IEC958_STS2 0xC1
215	#define REG_IEC958_STS3 0xC2
216	#define REG_IEC958_STS4 0xC3
217
218	#define REG_HPD_IRQ_TIME 0xC9
219	#define REG_AUX_DEBUG_MODE 0xCA
220	#define REG_AUX_OPT2 0xCB
221	#define REG_HDCP_OPT 0xCE
222	#define REG_USER_DRV_PRE 0xCF
223
224	#define REG_DATA_MUTE_CTRL 0xD3
225	#define ENABLE_ENHANCED_FRAME BIT(0)
226	#define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
227	#define EN_VID_MUTE BIT(4)
228	#define EN_AUD_MUTE BIT(5)
229
230	#define REG_TIME_STMP_CTRL 0xD4
231	#define EN_ENHANCE_VID_STMP BIT(0)
232	#define EN_ENHANCE_AUD_STMP BIT(2)
233	#define M_STAMP_STEP 0x30
234	#define EN_SSC_GAT BIT(6)
235
236	#define REG_INFOFRAME_CTRL 0xE8
237	#define EN_AVI_PKT BIT(0)
238	#define EN_AUD_PKT BIT(1)
239	#define EN_MPG_PKT BIT(2)
240	#define EN_GEN_PKT BIT(3)
241	#define EN_VID_TIME_STMP BIT(4)
242	#define EN_AUD_TIME_STMP BIT(5)
243	#define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
244	#define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
245
246	#define REG_AUDIO_N_0_7 0xDE
247	#define REG_AUDIO_N_8_15 0xDF
248	#define REG_AUDIO_N_16_23 0xE0
249
250	#define REG_AVI_INFO_DB1 0xE9
251	#define REG_AVI_INFO_DB2 0xEA
252	#define REG_AVI_INFO_DB3 0xEB
253	#define REG_AVI_INFO_DB4 0xEC
254	#define REG_AVI_INFO_DB5 0xED
255	#define REG_AVI_INFO_SUM 0xF6
256
257	#define REG_AUD_INFOFRAM_DB1 0xF7
258	#define REG_AUD_INFOFRAM_DB2 0xF8
259	#define REG_AUD_INFOFRAM_DB3 0xF9
260	#define REG_AUD_INFOFRAM_DB4 0xFA
261	#define REG_AUD_INFOFRAM_SUM 0xFB
262
263	/* the following six registers are in bank1 */
264	#define REG_DRV_0_DB_800_MV 0x17E
265	#define REG_PRE_0_DB_800_MV 0x17F
266	#define REG_PRE_3P5_DB_800_MV 0x181
267	#define REG_SSC_CTRL0 0x188
268	#define REG_SSC_CTRL1 0x189
269	#define REG_SSC_CTRL2 0x18A
270
271	#define REG_AUX_USER_CTRL 0x190
272	#define EN_USER_AUX BIT(0)
273	#define USER_AUX_DONE BIT(1)
274	#define AUX_EVENT BIT(4)
275
276	#define REG_AUX_USER_DATA_REC 0x191
277	#define M_AUX_IN_REC 0xF0
278	#define M_AUX_OUT_REC 0x0F
279
280	#define REG_AUX_USER_REPLY 0x19A
281	#define REG_AUX_USER_RXB(n) (n + 0x19B)
282
283	#define RBR DP_LINK_BW_1_62
284	#define HBR DP_LINK_BW_2_7
285	#define HBR2 DP_LINK_BW_5_4
286	#define HBR3 DP_LINK_BW_8_1
287
288	#define DPCD_V_1_1 0x11
289	#define MISC_VERB 0xF0
290	#define MISC_VERC 0x70
291	#define I2S_INPUT_FORMAT_STANDARD 0
292	#define I2S_INPUT_FORMAT_32BIT 1
293	#define I2S_INPUT_LEFT_JUSTIFIED 0
294	#define I2S_INPUT_RIGHT_JUSTIFIED 1
295	#define I2S_DATA_1T_DELAY 0
296	#define I2S_DATA_NO_DELAY 1
297	#define I2S_WS_LEFT_CHANNEL 0
298	#define I2S_WS_RIGHT_CHANNEL 1
299	#define I2S_DATA_MSB_FIRST 0
300	#define I2S_DATA_LSB_FIRST 1
301	#define WORD_LENGTH_16BIT 0
302	#define WORD_LENGTH_18BIT 1
303	#define WORD_LENGTH_20BIT 2
304	#define WORD_LENGTH_24BIT 3
305	#define DEBUGFS_DIR_NAME "it6505-debugfs"
306	#define READ_BUFFER_SIZE 400
307
308	/* Vendor option */
309	#define HDCP_DESIRED 1
310	#define MAX_LANE_COUNT 4
311	#define MAX_LINK_RATE HBR
312	#define AUTO_TRAIN_RETRY 3
313	#define MAX_HDCP_DOWN_STREAM_COUNT 127
314	#define MAX_CR_LEVEL 0x03
315	#define MAX_EQ_LEVEL 0x03
316	#define AUX_WAIT_TIMEOUT_MS 15
317	#define AUX_FIFO_MAX_SIZE 16
318	#define AUX_I2C_MAX_SIZE 4
319	#define AUX_I2C_DEFER_RETRY 4
320	#define PIXEL_CLK_DELAY 1
321	#define PIXEL_CLK_INVERSE 0
322	#define ADJUST_PHASE_THRESHOLD 80000
323	#define DPI_PIXEL_CLK_MAX 95000
324	#define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
325	#define DEFAULT_PWR_ON 0
326	#define DEFAULT_DRV_HOLD 0
327
328	#define AUDIO_SELECT I2S
329	#define AUDIO_TYPE LPCM
330	#define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
331	#define AUDIO_CHANNEL_COUNT 2
332	#define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
333	#define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
334	#define I2S_DATA_DELAY I2S_DATA_1T_DELAY
335	#define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
336	#define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
337	#define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
338
339	enum aux_cmd_type {
340	CMD_AUX_NATIVE_READ = 0x0,
341	CMD_AUX_NATIVE_WRITE = 0x5,
342	CMD_AUX_GI2C_ADR = 0x08,
343	CMD_AUX_GI2C_READ = 0x09,
344	CMD_AUX_GI2C_WRITE = 0x0A,
345	CMD_AUX_I2C_EDID_READ = 0xB,
346	CMD_AUX_I2C_READ = 0x0D,
347	CMD_AUX_I2C_WRITE = 0x0C,
348
349	/* KSV read with AUX FIFO extend from CMD_AUX_NATIVE_READ*/
350	CMD_AUX_GET_KSV_LIST = 0x10,
351	};
352
353	enum aux_cmd_reply {
354	REPLY_ACK,
355	REPLY_NACK,
356	REPLY_DEFER,
357	};
358
359	enum link_train_status {
360	LINK_IDLE,
361	LINK_BUSY,
362	LINK_OK,
363	};
364
365	enum hdcp_state {
366	HDCP_AUTH_IDLE,
367	HDCP_AUTH_GOING,
368	HDCP_AUTH_DONE,
369	};
370
371	struct it6505_platform_data {
372	struct regulator *pwr18;
373	struct regulator *ovdd;
374	struct gpio_desc *gpiod_reset;
375	};
376
377	enum it6505_audio_select {
378	I2S = 0,
379	SPDIF,
380	};
381
382	enum it6505_audio_sample_rate {
383	SAMPLE_RATE_24K = 0x6,
384	SAMPLE_RATE_32K = 0x3,
385	SAMPLE_RATE_48K = 0x2,
386	SAMPLE_RATE_96K = 0xA,
387	SAMPLE_RATE_192K = 0xE,
388	SAMPLE_RATE_44_1K = 0x0,
389	SAMPLE_RATE_88_2K = 0x8,
390	SAMPLE_RATE_176_4K = 0xC,
391	};
392
393	enum it6505_audio_type {
394	LPCM = 0,
395	NLPCM,
396	DSS,
397	};
398
399	struct it6505_audio_data {
400	enum it6505_audio_select select;
401	enum it6505_audio_sample_rate sample_rate;
402	enum it6505_audio_type type;
403	u8 word_length;
404	u8 channel_count;
405	u8 i2s_input_format;
406	u8 i2s_justified;
407	u8 i2s_data_delay;
408	u8 i2s_ws_channel;
409	u8 i2s_data_sequence;
410	};
411
412	struct it6505_audio_sample_rate_map {
413	enum it6505_audio_sample_rate rate;
414	int sample_rate_value;
415	};
416
417	struct it6505_drm_dp_link {
418	unsigned char revision;
419	unsigned int rate;
420	unsigned int num_lanes;
421	unsigned long capabilities;
422	};
423
424	struct debugfs_entries {
425	char *name;
426	const struct file_operations *fops;
427	};
428
429	struct it6505 {
430	struct drm_dp_aux aux;
431	struct drm_bridge bridge;
432	struct device *dev;
433	struct it6505_drm_dp_link link;
434	struct it6505_platform_data pdata;
435	/*
436	* Mutex protects extcon and interrupt functions from interfering
437	* each other.
438	*/
439	struct mutex extcon_lock;
440	struct mutex mode_lock; /* used to bridge_detect */
441	struct mutex aux_lock; /* used to aux data transfers */
442	struct regmap *regmap;
443	struct drm_display_mode source_output_mode;
444	struct drm_display_mode video_info;
445	struct notifier_block event_nb;
446	struct extcon_dev *extcon;
447	struct work_struct extcon_wq;
448	int extcon_state;
449	enum drm_connector_status connector_status;
450	enum link_train_status link_state;
451	struct work_struct link_works;
452	u8 dpcd[DP_RECEIVER_CAP_SIZE];
453	u8 lane_count;
454	u8 link_rate_bw_code;
455	u8 sink_count;
456	bool step_train;
457	bool branch_device;
458	bool enable_ssc;
459	bool lane_swap_disabled;
460	bool lane_swap;
461	bool powered;
462	bool hpd_state;
463	u32 afe_setting;
464	u32 max_dpi_pixel_clock;
465	u32 max_lane_count;
466	enum hdcp_state hdcp_status;
467	struct delayed_work hdcp_work;
468	struct work_struct hdcp_wait_ksv_list;
469	struct completion extcon_completion;
470	u8 auto_train_retry;
471	bool hdcp_desired;
472	bool is_repeater;
473	u8 hdcp_down_stream_count;
474	u8 bksvs[DRM_HDCP_KSV_LEN];
475	u8 sha1_input[HDCP_SHA1_FIFO_LEN];
476	bool enable_enhanced_frame;
477	hdmi_codec_plugged_cb plugged_cb;
478	struct device *codec_dev;
479	struct delayed_work delayed_audio;
480	struct it6505_audio_data audio;
481	struct dentry *debugfs;
482
483	/* it6505 driver hold option */
484	bool enable_drv_hold;
485
486	const struct drm_edid *cached_edid;
487
488	int irq;
489	};
490
491	struct it6505_step_train_para {
492	u8 voltage_swing[MAX_LANE_COUNT];
493	u8 pre_emphasis[MAX_LANE_COUNT];
494	};
495
496	/*
497	* Vendor option afe settings for different platforms
498	* 0: without FPC cable
499	* 1: with FPC cable
500	*/
501
502	static const u8 afe_setting_table[][3] = {
503	{0x82, 0x00, 0x45},
504	{0x93, 0x2A, 0x85}
505	};
506
507	static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
508	{SAMPLE_RATE_24K, 24000},
509	{SAMPLE_RATE_32K, 32000},
510	{SAMPLE_RATE_48K, 48000},
511	{SAMPLE_RATE_96K, 96000},
512	{SAMPLE_RATE_192K, 192000},
513	{SAMPLE_RATE_44_1K, 44100},
514	{SAMPLE_RATE_88_2K, 88200},
515	{SAMPLE_RATE_176_4K, 176400},
516	};
517
518	static const struct regmap_range it6505_bridge_volatile_ranges[] = {
519	{ .range_min = 0, .range_max = 0x1FF },
520	};
521
522	static const struct regmap_access_table it6505_bridge_volatile_table = {
523	.yes_ranges = it6505_bridge_volatile_ranges,
524	.n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
525	};
526
527	static const struct regmap_range_cfg it6505_regmap_banks[] = {
528	{
529	.name = "it6505",
530	.range_min = 0x00,
531	.range_max = 0x1FF,
532	.selector_reg = REG_BANK_SEL,
533	.selector_mask = 0x1,
534	.selector_shift = 0,
535	.window_start = 0x00,
536	.window_len = 0x100,
537	},
538	};
539
540	static const struct regmap_config it6505_regmap_config = {
541	.reg_bits = 8,
542	.val_bits = 8,
543	.volatile_table = &it6505_bridge_volatile_table,
544	.cache_type = REGCACHE_NONE,
545	.ranges = it6505_regmap_banks,
546	.num_ranges = ARRAY_SIZE(it6505_regmap_banks),
547	.max_register = 0x1FF,
548	};
549
550	static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
551	{
552	unsigned int value;
553	int err;
554	struct device *dev = it6505->dev;
555
556	if (!it6505->powered)
557	return -ENODEV;
558
559	err = regmap_read(map: it6505->regmap, reg: reg_addr, val: &value);
560	if (err < 0) {
561	dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
562	return err;
563	}
564
565	return value;
566	}
567
568	static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
569	unsigned int reg_val)
570	{
571	int err;
572	struct device *dev = it6505->dev;
573
574	if (!it6505->powered)
575	return -ENODEV;
576
577	err = regmap_write(map: it6505->regmap, reg: reg_addr, val: reg_val);
578
579	if (err < 0) {
580	dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
581	reg_addr, reg_val, err);
582	return err;
583	}
584
585	return 0;
586	}
587
588	static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
589	unsigned int mask, unsigned int value)
590	{
591	int err;
592	struct device *dev = it6505->dev;
593
594	if (!it6505->powered)
595	return -ENODEV;
596
597	err = regmap_update_bits(map: it6505->regmap, reg, mask, val: value);
598	if (err < 0) {
599	dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
600	reg, value, mask, err);
601	return err;
602	}
603
604	return 0;
605	}
606
607	static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
608	const char *prefix)
609	{
610	struct device *dev = it6505->dev;
611	int val;
612
613	if (!drm_debug_enabled(DRM_UT_DRIVER))
614	return;
615
616	val = it6505_read(it6505, reg_addr: reg);
617	if (val < 0)
618	DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
619	prefix, reg, val);
620	else
621	DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
622	val);
623	}
624
625	static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
626	{
627	u8 value;
628	int ret;
629	struct device *dev = it6505->dev;
630
631	ret = drm_dp_dpcd_readb(aux: &it6505->aux, offset, valuep: &value);
632	if (ret < 0) {
633	dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
634	return ret;
635	}
636	return value;
637	}
638
639	static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
640	u8 datain)
641	{
642	int ret;
643	struct device *dev = it6505->dev;
644
645	ret = drm_dp_dpcd_writeb(aux: &it6505->aux, offset, value: datain);
646	if (ret < 0) {
647	dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
648	return ret;
649	}
650	return 0;
651	}
652
653	static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
654	{
655	int ret;
656	struct device *dev = it6505->dev;
657
658	ret = drm_dp_dpcd_read(aux: &it6505->aux, offset, buffer: dpcd, size: num);
659
660	if (ret < 0)
661	return ret;
662
663	DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
664	num, dpcd);
665
666	return 0;
667	}
668
669	static void it6505_dump(struct it6505 *it6505)
670	{
671	unsigned int i, j;
672	u8 regs[16];
673	struct device *dev = it6505->dev;
674
675	for (i = 0; i <= 0xff; i += 16) {
676	for (j = 0; j < 16; j++)
677	regs[j] = it6505_read(it6505, reg_addr: i + j);
678
679	DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
680	}
681	}
682
683	static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
684	{
685	int reg_0d;
686
687	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
688
689	if (reg_0d < 0)
690	return false;
691
692	return reg_0d & HPD_STS;
693	}
694
695	static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
696	{
697	int val0, val1;
698
699	val0 = it6505_read(it6505, reg_addr: reg);
700	if (val0 < 0)
701	return val0;
702
703	val1 = it6505_read(it6505, reg_addr: reg + 1);
704	if (val1 < 0)
705	return val1;
706
707	return (val1 << 8) | val0;
708	}
709
710	static void it6505_calc_video_info(struct it6505 *it6505)
711	{
712	struct device *dev = it6505->dev;
713	int hsync_pol, vsync_pol, interlaced;
714	int htotal, hdes, hdew, hfph, hsyncw;
715	int vtotal, vdes, vdew, vfph, vsyncw;
716	int rddata, i, pclk, sum = 0;
717
718	usleep_range(min: 10000, max: 15000);
719	rddata = it6505_read(it6505, REG_INPUT_CTRL);
720	hsync_pol = rddata & INPUT_HSYNC_POL;
721	vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
722	interlaced = (rddata & INPUT_INTERLACED) >> 4;
723
724	htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
725	hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
726	hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
727	hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
728	hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
729
730	vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
731	vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
732	vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
733	vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
734	vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
735
736	DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
737	hsync_pol, vsync_pol, interlaced);
738	DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
739	hdes, vdes);
740
741	for (i = 0; i < 3; i++) {
742	it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
743	ENABLE_PCLK_COUNTER);
744	usleep_range(min: 10000, max: 15000);
745	it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
746	value: 0x00);
747	rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
748	0xFFF;
749
750	sum += rddata;
751	}
752
753	if (sum == 0) {
754	DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
755	return;
756	}
757
758	sum /= 3;
759	pclk = 13500 * 2048 / sum;
760	it6505->video_info.clock = pclk;
761	it6505->video_info.hdisplay = hdew;
762	it6505->video_info.hsync_start = hdew + hfph;
763	it6505->video_info.hsync_end = hdew + hfph + hsyncw;
764	it6505->video_info.htotal = htotal;
765	it6505->video_info.vdisplay = vdew;
766	it6505->video_info.vsync_start = vdew + vfph;
767	it6505->video_info.vsync_end = vdew + vfph + vsyncw;
768	it6505->video_info.vtotal = vtotal;
769
770	DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
771	DRM_MODE_ARG(&it6505->video_info));
772	}
773
774	static void it6505_clear_int(struct it6505 *it6505)
775	{
776	it6505_write(it6505, INT_STATUS_01, reg_val: 0xFF);
777	it6505_write(it6505, INT_STATUS_02, reg_val: 0xFF);
778	it6505_write(it6505, INT_STATUS_03, reg_val: 0xFF);
779	}
780
781	static void it6505_int_mask_enable(struct it6505 *it6505)
782	{
783	it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
784	BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
785	BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
786
787	it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
788	BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
789
790	it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
791	BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
792	}
793
794	static void it6505_int_mask_disable(struct it6505 *it6505)
795	{
796	it6505_write(it6505, INT_MASK_01, reg_val: 0x00);
797	it6505_write(it6505, INT_MASK_02, reg_val: 0x00);
798	it6505_write(it6505, INT_MASK_03, reg_val: 0x00);
799	}
800
801	static void it6505_lane_termination_on(struct it6505 *it6505)
802	{
803	int regcf;
804
805	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
806
807	if (regcf == MISC_VERB)
808	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x00);
809
810	if (regcf == MISC_VERC) {
811	if (it6505->lane_swap) {
812	switch (it6505->lane_count) {
813	case 1:
814	case 2:
815	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
816	mask: 0x0C, value: 0x08);
817	break;
818	default:
819	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
820	mask: 0x0C, value: 0x0C);
821	break;
822	}
823	} else {
824	switch (it6505->lane_count) {
825	case 1:
826	case 2:
827	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
828	mask: 0x0C, value: 0x04);
829	break;
830	default:
831	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
832	mask: 0x0C, value: 0x0C);
833	break;
834	}
835	}
836	}
837	}
838
839	static void it6505_lane_termination_off(struct it6505 *it6505)
840	{
841	int regcf;
842
843	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
844
845	if (regcf == MISC_VERB)
846	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x80);
847
848	if (regcf == MISC_VERC)
849	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x0C, value: 0x00);
850	}
851
852	static void it6505_lane_power_on(struct it6505 *it6505)
853	{
854	it6505_set_bits(it6505, REG_LINK_DRV, mask: 0xF1,
855	value: (it6505->lane_swap ?
856	GENMASK(7, 8 - it6505->lane_count) :
857	GENMASK(3 + it6505->lane_count, 4)) |
858	0x01);
859	}
860
861	static void it6505_lane_power_off(struct it6505 *it6505)
862	{
863	it6505_set_bits(it6505, REG_LINK_DRV, mask: 0xF0, value: 0x00);
864	}
865
866	static void it6505_lane_off(struct it6505 *it6505)
867	{
868	it6505_lane_power_off(it6505);
869	it6505_lane_termination_off(it6505);
870	}
871
872	static void it6505_aux_termination_on(struct it6505 *it6505)
873	{
874	int regcf;
875
876	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
877
878	if (regcf == MISC_VERB)
879	it6505_lane_termination_on(it6505);
880
881	if (regcf == MISC_VERC)
882	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x80);
883	}
884
885	static void it6505_aux_power_on(struct it6505 *it6505)
886	{
887	it6505_set_bits(it6505, REG_AUX, mask: 0x02, value: 0x02);
888	}
889
890	static void it6505_aux_on(struct it6505 *it6505)
891	{
892	it6505_aux_power_on(it6505);
893	it6505_aux_termination_on(it6505);
894	}
895
896	static void it6505_aux_reset(struct it6505 *it6505)
897	{
898	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
899	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, value: 0x00);
900	}
901
902	static void it6505_reset_logic(struct it6505 *it6505)
903	{
904	regmap_write(map: it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
905	usleep_range(min: 1000, max: 1500);
906	}
907
908	static bool it6505_aux_op_finished(struct it6505 *it6505)
909	{
910	int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
911
912	if (reg2b < 0)
913	return false;
914
915	return (reg2b & AUX_BUSY) == 0;
916	}
917
918	static int it6505_aux_wait(struct it6505 *it6505)
919	{
920	int status;
921	unsigned long timeout;
922	struct device *dev = it6505->dev;
923
924	timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
925
926	while (!it6505_aux_op_finished(it6505)) {
927	if (time_after(jiffies, timeout)) {
928	dev_err(dev, "Timed out waiting AUX to finish");
929	return -ETIMEDOUT;
930	}
931	usleep_range(min: 1000, max: 2000);
932	}
933
934	status = it6505_read(it6505, REG_AUX_ERROR_STS);
935	if (status < 0) {
936	dev_err(dev, "Failed to read AUX channel: %d", status);
937	return status;
938	}
939
940	return 0;
941	}
942
943	static ssize_t it6505_aux_operation(struct it6505 *it6505,
944	enum aux_cmd_type cmd,
945	unsigned int address, u8 *buffer,
946	size_t size, enum aux_cmd_reply *reply)
947	{
948	int i, ret;
949	bool aux_write_check = false;
950
951	if (!it6505_get_sink_hpd_status(it6505))
952	return -EIO;
953
954	/* set AUX user mode */
955	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
956
957	aux_op_start:
958	/* HW AUX FIFO supports only EDID and DCPD KSV FIFO area */
959	if (cmd == CMD_AUX_I2C_EDID_READ || cmd == CMD_AUX_GET_KSV_LIST) {
960	/* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
961	size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
962	/* Enable AUX FIFO read back and clear FIFO */
963	it6505_set_bits(it6505, REG_AUX_CTRL,
964	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
965	AUX_EN_FIFO_READ | CLR_EDID_FIFO);
966
967	it6505_set_bits(it6505, REG_AUX_CTRL,
968	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
969	AUX_EN_FIFO_READ);
970	} else {
971	/* The DP AUX transmit buffer has 4 bytes. */
972	size = min_t(size_t, size, 4);
973	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
974	AUX_NO_SEGMENT_WR);
975	}
976
977	/* Start Address[7:0] */
978	it6505_write(it6505, REG_AUX_ADR_0_7, reg_val: (address >> 0) & 0xFF);
979	/* Start Address[15:8] */
980	it6505_write(it6505, REG_AUX_ADR_8_15, reg_val: (address >> 8) & 0xFF);
981	/* WriteNum[3:0]+StartAdr[19:16] */
982	it6505_write(it6505, REG_AUX_ADR_16_19,
983	reg_val: ((address >> 16) & 0x0F) | ((size - 1) << 4));
984
985	if (cmd == CMD_AUX_NATIVE_WRITE)
986	regmap_bulk_write(map: it6505->regmap, REG_AUX_OUT_DATA0, val: buffer,
987	val_count: size);
988
989	/* Aux Fire */
990	it6505_write(it6505, REG_AUX_CMD_REQ, FIELD_GET(M_AUX_REQ_CMD, cmd));
991
992	ret = it6505_aux_wait(it6505);
993	if (ret < 0)
994	goto aux_op_err;
995
996	ret = it6505_read(it6505, REG_AUX_ERROR_STS);
997	if (ret < 0)
998	goto aux_op_err;
999
1000	switch ((ret >> 6) & 0x3) {
1001	case 0:
1002	*reply = REPLY_ACK;
1003	break;
1004	case 1:
1005	*reply = REPLY_DEFER;
1006	ret = -EAGAIN;
1007	goto aux_op_err;
1008	case 2:
1009	*reply = REPLY_NACK;
1010	ret = -EIO;
1011	goto aux_op_err;
1012	case 3:
1013	ret = -ETIMEDOUT;
1014	goto aux_op_err;
1015	}
1016
1017	/* Read back Native Write data */
1018	if (cmd == CMD_AUX_NATIVE_WRITE) {
1019	aux_write_check = true;
1020	cmd = CMD_AUX_NATIVE_READ;
1021	goto aux_op_start;
1022	}
1023
1024	if (cmd == CMD_AUX_I2C_EDID_READ || cmd == CMD_AUX_GET_KSV_LIST) {
1025	for (i = 0; i < size; i++) {
1026	ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1027	if (ret < 0)
1028	goto aux_op_err;
1029	buffer[i] = ret;
1030	}
1031	} else {
1032	for (i = 0; i < size; i++) {
1033	ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1034	if (ret < 0)
1035	goto aux_op_err;
1036
1037	if (aux_write_check && buffer[size - 1 - i] != ret) {
1038	ret = -EINVAL;
1039	goto aux_op_err;
1040	}
1041
1042	buffer[size - 1 - i] = ret;
1043	}
1044	}
1045
1046	ret = i;
1047
1048	aux_op_err:
1049	if (cmd == CMD_AUX_I2C_EDID_READ || cmd == CMD_AUX_GET_KSV_LIST) {
1050	/* clear AUX FIFO */
1051	it6505_set_bits(it6505, REG_AUX_CTRL,
1052	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1053	AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1054	it6505_set_bits(it6505, REG_AUX_CTRL,
1055	AUX_EN_FIFO_READ | CLR_EDID_FIFO, value: 0x00);
1056	}
1057
1058	/* Leave AUX user mode */
1059	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, value: 0);
1060
1061	return ret;
1062	}
1063
1064	static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1065	enum aux_cmd_type cmd,
1066	unsigned int address, u8 *buffer,
1067	size_t size, enum aux_cmd_reply *reply)
1068	{
1069	int i, ret_size, ret = 0, request_size;
1070	int fifo_max_size = (cmd == CMD_AUX_I2C_EDID_READ || cmd == CMD_AUX_GET_KSV_LIST) ?
1071	AUX_FIFO_MAX_SIZE : 4;
1072
1073	mutex_lock(&it6505->aux_lock);
1074	i = 0;
1075	do {
1076	request_size = min_t(int, (int)size - i, fifo_max_size);
1077
1078	ret_size = it6505_aux_operation(it6505, cmd, address: address + i,
1079	buffer: buffer + i, size: request_size,
1080	reply);
1081	if (ret_size < 0) {
1082	ret = ret_size;
1083	goto aux_op_err;
1084	}
1085
1086	i += request_size;
1087	ret += ret_size;
1088	} while (i < size);
1089
1090	aux_op_err:
1091	mutex_unlock(lock: &it6505->aux_lock);
1092	return ret;
1093	}
1094
1095	static bool it6505_aux_i2c_reply_defer(u8 reply)
1096	{
1097	if (reply == DP_AUX_NATIVE_REPLY_DEFER || reply == DP_AUX_I2C_REPLY_DEFER)
1098	return true;
1099	return false;
1100	}
1101
1102	static bool it6505_aux_i2c_reply_nack(u8 reply)
1103	{
1104	if (reply == DP_AUX_NATIVE_REPLY_NACK || reply == DP_AUX_I2C_REPLY_NACK)
1105	return true;
1106	return false;
1107	}
1108
1109	static int it6505_aux_i2c_wait(struct it6505 *it6505, u8 *reply)
1110	{
1111	int err = 0;
1112	unsigned long timeout;
1113	struct device *dev = it6505->dev;
1114
1115	timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
1116
1117	do {
1118	if (it6505_read(it6505, REG_AUX_USER_CTRL) & AUX_EVENT)
1119	break;
1120	if (time_after(jiffies, timeout)) {
1121	dev_err(dev, "Timed out waiting AUX I2C, BUSY = %X\n",
1122	it6505_aux_op_finished(it6505));
1123	err = -ETIMEDOUT;
1124	goto end_aux_i2c_wait;
1125	}
1126	usleep_range(min: 300, max: 800);
1127	} while (!it6505_aux_op_finished(it6505));
1128
1129	*reply = it6505_read(it6505, REG_AUX_USER_REPLY) >> 4;
1130
1131	if (*reply == 0)
1132	goto end_aux_i2c_wait;
1133
1134	if (it6505_aux_i2c_reply_defer(reply: *reply))
1135	err = -EBUSY;
1136	else if (it6505_aux_i2c_reply_nack(reply: *reply))
1137	err = -ENXIO;
1138
1139	end_aux_i2c_wait:
1140	it6505_set_bits(it6505, REG_AUX_USER_CTRL, USER_AUX_DONE, USER_AUX_DONE);
1141	return err;
1142	}
1143
1144	static int it6505_aux_i2c_readb(struct it6505 *it6505, u8 *buf, size_t size, u8 *reply)
1145	{
1146	int ret, i;
1147	int retry;
1148
1149	for (retry = 0; retry < AUX_I2C_DEFER_RETRY; retry++) {
1150	it6505_write(it6505, REG_AUX_CMD_REQ, reg_val: CMD_AUX_GI2C_READ);
1151
1152	ret = it6505_aux_i2c_wait(it6505, reply);
1153	if (it6505_aux_i2c_reply_defer(reply: *reply))
1154	continue;
1155	if (ret >= 0)
1156	break;
1157	}
1158
1159	for (i = 0; i < size; i++)
1160	buf[i] = it6505_read(it6505, REG_AUX_USER_RXB(0 + i));
1161
1162	return size;
1163	}
1164
1165	static int it6505_aux_i2c_writeb(struct it6505 *it6505, u8 *buf, size_t size, u8 *reply)
1166	{
1167	int i, ret;
1168	int retry;
1169
1170	for (i = 0; i < size; i++)
1171	it6505_write(it6505, REG_AUX_OUT_DATA0 + i, reg_val: buf[i]);
1172
1173	for (retry = 0; retry < AUX_I2C_DEFER_RETRY; retry++) {
1174	it6505_write(it6505, REG_AUX_CMD_REQ, reg_val: CMD_AUX_GI2C_WRITE);
1175
1176	ret = it6505_aux_i2c_wait(it6505, reply);
1177	if (it6505_aux_i2c_reply_defer(reply: *reply))
1178	continue;
1179	if (ret >= 0)
1180	break;
1181	}
1182	return size;
1183	}
1184
1185	static ssize_t it6505_aux_i2c_operation(struct it6505 *it6505,
1186	struct drm_dp_aux_msg *msg)
1187	{
1188	int ret;
1189	ssize_t request_size, data_cnt = 0;
1190	u8 *buffer = msg->buffer;
1191
1192	/* set AUX user mode */
1193	it6505_set_bits(it6505, REG_AUX_CTRL,
1194	AUX_USER_MODE | AUX_NO_SEGMENT_WR, AUX_USER_MODE);
1195	it6505_set_bits(it6505, REG_AUX_USER_CTRL, EN_USER_AUX, EN_USER_AUX);
1196	/* clear AUX FIFO */
1197	it6505_set_bits(it6505, REG_AUX_CTRL,
1198	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1199	AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1200
1201	it6505_set_bits(it6505, REG_AUX_CTRL,
1202	AUX_EN_FIFO_READ | CLR_EDID_FIFO, value: 0x00);
1203
1204	it6505_write(it6505, REG_AUX_ADR_0_7, reg_val: 0x00);
1205	it6505_write(it6505, REG_AUX_ADR_8_15, reg_val: msg->address << 1);
1206
1207	if (msg->size == 0) {
1208	/* IIC Start/STOP dummy write */
1209	it6505_write(it6505, REG_AUX_ADR_16_19, reg_val: msg->request);
1210	it6505_write(it6505, REG_AUX_CMD_REQ, reg_val: CMD_AUX_GI2C_ADR);
1211	ret = it6505_aux_i2c_wait(it6505, reply: &msg->reply);
1212	goto end_aux_i2c_transfer;
1213	}
1214
1215	/* IIC data transfer */
1216	data_cnt = 0;
1217	do {
1218	request_size = min_t(ssize_t, msg->size - data_cnt, AUX_I2C_MAX_SIZE);
1219	it6505_write(it6505, REG_AUX_ADR_16_19,
1220	reg_val: msg->request | ((request_size - 1) << 4));
1221	if ((msg->request & DP_AUX_I2C_READ) == DP_AUX_I2C_READ)
1222	ret = it6505_aux_i2c_readb(it6505, buf: &buffer[data_cnt],
1223	size: request_size, reply: &msg->reply);
1224	else
1225	ret = it6505_aux_i2c_writeb(it6505, buf: &buffer[data_cnt],
1226	size: request_size, reply: &msg->reply);
1227
1228	if (ret < 0)
1229	goto end_aux_i2c_transfer;
1230
1231	data_cnt += request_size;
1232	} while (data_cnt < msg->size);
1233	ret = data_cnt;
1234	end_aux_i2c_transfer:
1235
1236	it6505_set_bits(it6505, REG_AUX_USER_CTRL, EN_USER_AUX, value: 0);
1237	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, value: 0);
1238	return ret;
1239	}
1240
1241	static ssize_t it6505_aux_i2c_transfer(struct drm_dp_aux *aux,
1242	struct drm_dp_aux_msg *msg)
1243	{
1244	struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1245
1246	guard(mutex)(T: &it6505->aux_lock);
1247	return it6505_aux_i2c_operation(it6505, msg);
1248	}
1249
1250	static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1251	struct drm_dp_aux_msg *msg)
1252	{
1253	struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1254	u8 cmd;
1255	bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1256	int ret;
1257	enum aux_cmd_reply reply;
1258
1259	if (is_i2c)
1260	return it6505_aux_i2c_transfer(aux, msg);
1261
1262	switch (msg->request) {
1263	case DP_AUX_NATIVE_READ:
1264	cmd = CMD_AUX_NATIVE_READ;
1265	break;
1266	case DP_AUX_NATIVE_WRITE:
1267	cmd = CMD_AUX_NATIVE_WRITE;
1268	break;
1269	default:
1270	return -EINVAL;
1271	}
1272
1273	ret = it6505_aux_do_transfer(it6505, cmd, address: msg->address, buffer: msg->buffer,
1274	size: msg->size, reply: &reply);
1275	if (ret < 0)
1276	return ret;
1277
1278	switch (reply) {
1279	case REPLY_ACK:
1280	msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1281	break;
1282	case REPLY_NACK:
1283	msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1284	break;
1285	case REPLY_DEFER:
1286	msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1287	break;
1288	}
1289
1290	return ret;
1291	}
1292
1293	static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1294	size_t len)
1295	{
1296	struct it6505 *it6505 = data;
1297	struct device *dev = it6505->dev;
1298	enum aux_cmd_reply reply;
1299	int offset, ret, aux_retry = 100;
1300
1301	it6505_aux_reset(it6505);
1302	DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1303
1304	for (offset = 0; offset < EDID_LENGTH;) {
1305	ret = it6505_aux_do_transfer(it6505, cmd: CMD_AUX_I2C_EDID_READ,
1306	address: block * EDID_LENGTH + offset,
1307	buffer: buf + offset, size: 8, reply: &reply);
1308
1309	if (ret < 0 && ret != -EAGAIN)
1310	return ret;
1311
1312	switch (reply) {
1313	case REPLY_ACK:
1314	DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1315	buf + offset);
1316	offset += 8;
1317	aux_retry = 100;
1318	break;
1319	case REPLY_NACK:
1320	return -EIO;
1321	case REPLY_DEFER:
1322	msleep(msecs: 20);
1323	if (!(--aux_retry))
1324	return -EIO;
1325	}
1326	}
1327
1328	return 0;
1329	}
1330
1331	static int it6505_get_ksvlist(struct it6505 *it6505, u8 *buf, size_t len)
1332	{
1333	struct device *dev = it6505->dev;
1334	enum aux_cmd_reply reply;
1335	int request_size, ret;
1336	int i = 0;
1337
1338	do {
1339	request_size = min_t(int, (int)len - i, 15);
1340
1341	ret = it6505_aux_do_transfer(it6505, cmd: CMD_AUX_GET_KSV_LIST,
1342	DP_AUX_HDCP_KSV_FIFO,
1343	buffer: buf + i, size: request_size, reply: &reply);
1344
1345	DRM_DEV_DEBUG_DRIVER(dev, "request_size = %d, ret =%d", request_size, ret);
1346	if (ret < 0)
1347	return ret;
1348
1349	i += request_size;
1350	} while (i < len);
1351
1352	DRM_DEV_DEBUG_DRIVER(dev, "ksv read cnt = %d down_stream_cnt=%d ", i, i / 5);
1353
1354	for (i = 0 ; i < len; i += 5) {
1355	DRM_DEV_DEBUG_DRIVER(dev, "ksv[%d] = %02X%02X%02X%02X%02X",
1356	i / 5, buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4]);
1357	}
1358
1359	return len;
1360	}
1361
1362	static void it6505_variable_config(struct it6505 *it6505)
1363	{
1364	it6505->link_rate_bw_code = HBR;
1365	it6505->lane_count = MAX_LANE_COUNT;
1366	it6505->link_state = LINK_IDLE;
1367	it6505->hdcp_desired = HDCP_DESIRED;
1368	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1369	it6505->audio.select = AUDIO_SELECT;
1370	it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1371	it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1372	it6505->audio.type = AUDIO_TYPE;
1373	it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1374	it6505->audio.i2s_justified = I2S_JUSTIFIED;
1375	it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1376	it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1377	it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1378	it6505->audio.word_length = AUDIO_WORD_LENGTH;
1379	memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1380	memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1381	}
1382
1383	static int it6505_send_video_infoframe(struct it6505 *it6505,
1384	struct hdmi_avi_infoframe *frame)
1385	{
1386	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1387	int err;
1388	struct device *dev = it6505->dev;
1389
1390	err = hdmi_avi_infoframe_pack(frame, buffer, size: sizeof(buffer));
1391	if (err < 0) {
1392	dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1393	return err;
1394	}
1395
1396	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, value: 0x00);
1397	if (err)
1398	return err;
1399
1400	err = regmap_bulk_write(map: it6505->regmap, REG_AVI_INFO_DB1,
1401	val: buffer + HDMI_INFOFRAME_HEADER_SIZE,
1402	val_count: frame->length);
1403	if (err)
1404	return err;
1405
1406	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1407	EN_AVI_PKT);
1408	if (err)
1409	return err;
1410
1411	return 0;
1412	}
1413
1414	static void it6505_get_extcon_property(struct it6505 *it6505)
1415	{
1416	int err;
1417	union extcon_property_value property;
1418	struct device *dev = it6505->dev;
1419
1420	if (it6505->extcon && !it6505->lane_swap_disabled) {
1421	err = extcon_get_property(edev: it6505->extcon, EXTCON_DISP_DP,
1422	EXTCON_PROP_USB_TYPEC_POLARITY,
1423	prop_val: &property);
1424	if (err) {
1425	dev_err(dev, "get property fail!");
1426	return;
1427	}
1428	it6505->lane_swap = property.intval;
1429	}
1430	}
1431
1432	static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1433	const struct drm_display_mode *mode)
1434	{
1435	int clock = mode->clock;
1436
1437	it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1438	value: clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1439	it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1440	PIXEL_CLK_INVERSE << 4);
1441	}
1442
1443	static void it6505_link_reset_step_train(struct it6505 *it6505)
1444	{
1445	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1446	FORCE_CR_DONE | FORCE_EQ_DONE, value: 0x00);
1447	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1448	DP_TRAINING_PATTERN_DISABLE);
1449	}
1450
1451	static void it6505_init(struct it6505 *it6505)
1452	{
1453	it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1454	it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1455	it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1456	it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1457	it6505_write(it6505, REG_VID_BUS_CTRL1, reg_val: 0x01);
1458	it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1459
1460	/* chip internal setting, don't modify */
1461	it6505_write(it6505, REG_HPD_IRQ_TIME, reg_val: 0xF5);
1462	it6505_write(it6505, REG_AUX_DEBUG_MODE, reg_val: 0x4D);
1463	it6505_write(it6505, REG_AUX_OPT2, reg_val: 0x17);
1464	it6505_write(it6505, REG_HDCP_OPT, reg_val: 0x60);
1465	it6505_write(it6505, REG_DATA_MUTE_CTRL,
1466	EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1467	it6505_write(it6505, REG_TIME_STMP_CTRL,
1468	EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1469	it6505_write(it6505, REG_INFOFRAME_CTRL, reg_val: 0x00);
1470	it6505_write(it6505, REG_DRV_0_DB_800_MV,
1471	reg_val: afe_setting_table[it6505->afe_setting][0]);
1472	it6505_write(it6505, REG_PRE_0_DB_800_MV,
1473	reg_val: afe_setting_table[it6505->afe_setting][1]);
1474	it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1475	reg_val: afe_setting_table[it6505->afe_setting][2]);
1476	it6505_write(it6505, REG_SSC_CTRL0, reg_val: 0x9E);
1477	it6505_write(it6505, REG_SSC_CTRL1, reg_val: 0x1C);
1478	it6505_write(it6505, REG_SSC_CTRL2, reg_val: 0x42);
1479	}
1480
1481	static void it6505_video_disable(struct it6505 *it6505)
1482	{
1483	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1484	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, value: 0x00);
1485	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1486	}
1487
1488	static void it6505_video_reset(struct it6505 *it6505)
1489	{
1490	it6505_link_reset_step_train(it6505);
1491	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1492	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, value: 0x00);
1493
1494	it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, TX_FIFO_RESET);
1495	it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, value: 0x00);
1496
1497	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1498	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, value: 0x00);
1499
1500	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1501	usleep_range(min: 1000, max: 2000);
1502	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, value: 0x00);
1503	}
1504
1505	static void it6505_update_video_parameter(struct it6505 *it6505,
1506	const struct drm_display_mode *mode)
1507	{
1508	it6505_clk_phase_adjustment(it6505, mode);
1509	it6505_video_disable(it6505);
1510	}
1511
1512	static bool it6505_audio_input(struct it6505 *it6505)
1513	{
1514	int reg05, regbe;
1515
1516	reg05 = it6505_read(it6505, REG_RESET_CTRL);
1517	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, value: 0x00);
1518	usleep_range(min: 3000, max: 4000);
1519	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1520	it6505_write(it6505, REG_RESET_CTRL, reg_val: reg05);
1521
1522	return regbe != 0xFF;
1523	}
1524
1525	static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1526	{
1527	enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1528	u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1529
1530	/* Channel Status */
1531	it6505_write(it6505, REG_IEC958_STS0, reg_val: it6505->audio.type << 1);
1532	it6505_write(it6505, REG_IEC958_STS1, reg_val: 0x00);
1533	it6505_write(it6505, REG_IEC958_STS2, reg_val: 0x00);
1534	it6505_write(it6505, REG_IEC958_STS3, reg_val: sample_rate);
1535	it6505_write(it6505, REG_IEC958_STS4, reg_val: (~sample_rate << 4) |
1536	audio_word_length_map[it6505->audio.word_length]);
1537	}
1538
1539	static void it6505_setup_audio_format(struct it6505 *it6505)
1540	{
1541	/* I2S MODE */
1542	it6505_write(it6505, REG_AUDIO_FMT,
1543	reg_val: (it6505->audio.word_length << 5) |
1544	(it6505->audio.i2s_data_sequence << 4) |
1545	(it6505->audio.i2s_ws_channel << 3) |
1546	(it6505->audio.i2s_data_delay << 2) |
1547	(it6505->audio.i2s_justified << 1) |
1548	it6505->audio.i2s_input_format);
1549	if (it6505->audio.select == SPDIF) {
1550	it6505_write(it6505, REG_AUDIO_FIFO_SEL, reg_val: 0x00);
1551	/* 0x30 = 128*FS */
1552	it6505_set_bits(it6505, REG_AUX_OPT, mask: 0xF0, value: 0x30);
1553	} else {
1554	it6505_write(it6505, REG_AUDIO_FIFO_SEL, reg_val: 0xE4);
1555	}
1556
1557	it6505_write(it6505, REG_AUDIO_CTRL0, reg_val: 0x20);
1558	it6505_write(it6505, REG_AUDIO_CTRL1, reg_val: 0x00);
1559	}
1560
1561	static void it6505_enable_audio_source(struct it6505 *it6505)
1562	{
1563	unsigned int audio_source_count;
1564
1565	audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1566	- 1;
1567
1568	audio_source_count |= it6505->audio.select << 4;
1569
1570	it6505_write(it6505, REG_AUDIO_SRC_CTRL, reg_val: audio_source_count);
1571	}
1572
1573	static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1574	{
1575	struct device *dev = it6505->dev;
1576	u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1577
1578	DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1579	audio_info_ca[it6505->audio.channel_count - 1]);
1580
1581	it6505_write(it6505, REG_AUD_INFOFRAM_DB1, reg_val: it6505->audio.channel_count
1582	- 1);
1583	it6505_write(it6505, REG_AUD_INFOFRAM_DB2, reg_val: 0x00);
1584	it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1585	reg_val: audio_info_ca[it6505->audio.channel_count - 1]);
1586	it6505_write(it6505, REG_AUD_INFOFRAM_DB4, reg_val: 0x00);
1587	it6505_write(it6505, REG_AUD_INFOFRAM_SUM, reg_val: 0x00);
1588
1589	/* Enable Audio InfoFrame */
1590	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1591	EN_AUD_CTRL_PKT);
1592	}
1593
1594	static void it6505_disable_audio(struct it6505 *it6505)
1595	{
1596	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1597	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, value: 0x00);
1598	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, value: 0x00);
1599	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1600	}
1601
1602	static void it6505_enable_audio(struct it6505 *it6505)
1603	{
1604	struct device *dev = it6505->dev;
1605	int regbe;
1606
1607	DRM_DEV_DEBUG_DRIVER(dev, "start");
1608	it6505_disable_audio(it6505);
1609
1610	it6505_setup_audio_channel_status(it6505);
1611	it6505_setup_audio_format(it6505);
1612	it6505_enable_audio_source(it6505);
1613	it6505_enable_audio_infoframe(it6505);
1614
1615	it6505_write(it6505, REG_AUDIO_N_0_7, reg_val: 0x00);
1616	it6505_write(it6505, REG_AUDIO_N_8_15, reg_val: 0x80);
1617	it6505_write(it6505, REG_AUDIO_N_16_23, reg_val: 0x00);
1618
1619	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1620	AUDIO_FIFO_RESET);
1621	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, value: 0x00);
1622	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, value: 0x00);
1623	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1624	DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1625	regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1626	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, value: 0x00);
1627	}
1628
1629	static bool it6505_use_step_train_check(struct it6505 *it6505)
1630	{
1631	if (it6505->link.revision >= 0x12)
1632	return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1633
1634	return true;
1635	}
1636
1637	static void it6505_parse_link_capabilities(struct it6505 *it6505)
1638	{
1639	struct device *dev = it6505->dev;
1640	struct it6505_drm_dp_link *link = &it6505->link;
1641	int bcaps;
1642
1643	if (it6505->dpcd[0] == 0) {
1644	dev_err(dev, "DPCD is not initialized");
1645	return;
1646	}
1647
1648	memset(link, 0, sizeof(*link));
1649
1650	link->revision = it6505->dpcd[0];
1651	link->rate = drm_dp_bw_code_to_link_rate(link_bw: it6505->dpcd[1]);
1652	link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1653
1654	if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1655	link->capabilities = DP_ENHANCED_FRAME_CAP;
1656
1657	DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1658	link->revision >> 4, link->revision & 0x0F);
1659
1660	DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1661	link->rate / 100000, link->rate / 1000 % 100);
1662
1663	it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link_rate: link->rate);
1664	DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1665	it6505->link_rate_bw_code);
1666	it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1667	MAX_LINK_RATE);
1668
1669	it6505->lane_count = link->num_lanes;
1670	DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1671	it6505->lane_count);
1672	it6505->lane_count = min_t(int, it6505->lane_count,
1673	it6505->max_lane_count);
1674
1675	it6505->branch_device = drm_dp_is_branch(dpcd: it6505->dpcd);
1676	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1677	it6505->branch_device ? "" : "Not ");
1678
1679	it6505->enable_enhanced_frame = link->capabilities;
1680	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1681	it6505->enable_enhanced_frame ? "" : "Not ");
1682
1683	it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1684	DP_MAX_DOWNSPREAD_0_5);
1685	DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1686	it6505->enable_ssc ? "0.5" : "0",
1687	it6505->enable_ssc ? "" : "Not ");
1688
1689	it6505->step_train = it6505_use_step_train_check(it6505);
1690	if (it6505->step_train)
1691	DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1692
1693	bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1694	DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1695	if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1696	it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1697	DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1698	it6505->is_repeater ? "repeater" :
1699	"receiver");
1700	} else {
1701	DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1702	it6505->hdcp_desired = false;
1703	}
1704	DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1705	it6505->hdcp_desired ? "desired" : "undesired");
1706	}
1707
1708	static void it6505_setup_ssc(struct it6505 *it6505)
1709	{
1710	it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1711	value: it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1712	if (it6505->enable_ssc) {
1713	it6505_write(it6505, REG_SSC_CTRL0, reg_val: 0x9E);
1714	it6505_write(it6505, REG_SSC_CTRL1, reg_val: 0x1C);
1715	it6505_write(it6505, REG_SSC_CTRL2, reg_val: 0x42);
1716	it6505_write(it6505, REG_SP_CTRL0, reg_val: 0x07);
1717	it6505_write(it6505, REG_IP_CTRL1, reg_val: 0x29);
1718	it6505_write(it6505, REG_IP_CTRL2, reg_val: 0x03);
1719	/* Stamp Interrupt Step */
1720	it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1721	value: 0x10);
1722	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1723	DP_SPREAD_AMP_0_5);
1724	} else {
1725	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, datain: 0x00);
1726	it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1727	value: 0x00);
1728	}
1729	}
1730
1731	static inline void it6505_link_rate_setup(struct it6505 *it6505)
1732	{
1733	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1734	value: (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1735	it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1736	value: (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1737	}
1738
1739	static void it6505_lane_count_setup(struct it6505 *it6505)
1740	{
1741	it6505_get_extcon_property(it6505);
1742	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1743	value: it6505->lane_swap ? LANE_SWAP : 0x00);
1744	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1745	value: (it6505->lane_count - 1) << 1);
1746	}
1747
1748	static void it6505_link_training_setup(struct it6505 *it6505)
1749	{
1750	struct device *dev = it6505->dev;
1751
1752	if (it6505->enable_enhanced_frame)
1753	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1754	ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1755
1756	it6505_link_rate_setup(it6505);
1757	it6505_lane_count_setup(it6505);
1758	it6505_setup_ssc(it6505);
1759	DRM_DEV_DEBUG_DRIVER(dev,
1760	"%s, %d lanes, %sable ssc, %sable enhanced frame",
1761	it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1762	it6505->lane_count,
1763	it6505->enable_ssc ? "en" : "dis",
1764	it6505->enable_enhanced_frame ? "en" : "dis");
1765	}
1766
1767	static bool it6505_link_start_auto_train(struct it6505 *it6505)
1768	{
1769	int timeout = 500, link_training_state;
1770	bool state = false;
1771
1772	mutex_lock(&it6505->aux_lock);
1773	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1774	FORCE_CR_DONE | FORCE_EQ_DONE, value: 0x00);
1775	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1776	it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1777
1778	while (timeout > 0) {
1779	usleep_range(min: 1000, max: 2000);
1780	link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1781
1782	if (link_training_state > 0 &&
1783	(link_training_state & LINK_STATE_NORP)) {
1784	state = true;
1785	goto unlock;
1786	}
1787
1788	timeout--;
1789	}
1790	unlock:
1791	mutex_unlock(lock: &it6505->aux_lock);
1792
1793	return state;
1794	}
1795
1796	static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1797	{
1798	u8 values[2];
1799	int err;
1800	struct drm_dp_aux *aux = &it6505->aux;
1801
1802	values[0] = it6505->link_rate_bw_code;
1803	values[1] = it6505->lane_count;
1804
1805	if (it6505->enable_enhanced_frame)
1806	values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1807
1808	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, buffer: values, size: sizeof(values));
1809	if (err < 0)
1810	return err;
1811
1812	return 0;
1813	}
1814
1815	static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1816	{
1817	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1818	}
1819
1820	static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1821	{
1822	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1823	}
1824
1825	static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1826	u8 lane_count)
1827	{
1828	u8 i;
1829
1830	for (i = 0; i < lane_count; i++) {
1831	if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1832	return true;
1833	}
1834
1835	return false;
1836	}
1837
1838	static bool
1839	step_train_lane_voltage_para_set(struct it6505 *it6505,
1840	struct it6505_step_train_para
1841	*lane_voltage_pre_emphasis,
1842	u8 *lane_voltage_pre_emphasis_set)
1843	{
1844	u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1845	u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1846	u8 i;
1847
1848	for (i = 0; i < it6505->lane_count; i++) {
1849	voltage_swing[i] &= 0x03;
1850	lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1851	if (it6505_check_voltage_swing_max(lane_voltage_swing_pre_emphasis: voltage_swing[i]))
1852	lane_voltage_pre_emphasis_set[i] |=
1853	DP_TRAIN_MAX_SWING_REACHED;
1854
1855	pre_emphasis[i] &= 0x03;
1856	lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1857	<< DP_TRAIN_PRE_EMPHASIS_SHIFT;
1858	if (it6505_check_pre_emphasis_max(lane_voltage_swing_pre_emphasis: pre_emphasis[i]))
1859	lane_voltage_pre_emphasis_set[i] |=
1860	DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1861	it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1862	datain: lane_voltage_pre_emphasis_set[i]);
1863
1864	if (lane_voltage_pre_emphasis_set[i] !=
1865	it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1866	return false;
1867	}
1868
1869	return true;
1870	}
1871
1872	static bool
1873	it6505_step_cr_train(struct it6505 *it6505,
1874	struct it6505_step_train_para *lane_voltage_pre_emphasis)
1875	{
1876	u8 loop_count = 0, i = 0, j;
1877	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1878	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1879	int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1880	const struct drm_dp_aux *aux = &it6505->aux;
1881
1882	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1883	datain: it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1884	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1885	DP_TRAINING_PATTERN_1);
1886
1887	while (loop_count < 5 && i < 10) {
1888	i++;
1889	if (!step_train_lane_voltage_para_set(it6505,
1890	lane_voltage_pre_emphasis,
1891	lane_voltage_pre_emphasis_set: lane_level_config))
1892	continue;
1893	drm_dp_link_train_clock_recovery_delay(aux, dpcd: it6505->dpcd);
1894	drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
1895
1896	if (drm_dp_clock_recovery_ok(link_status, lane_count: it6505->lane_count)) {
1897	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1898	FORCE_CR_DONE);
1899	return true;
1900	}
1901	DRM_DEV_DEBUG_DRIVER(it6505->dev, "cr not done");
1902
1903	if (it6505_check_max_voltage_swing_reached(lane_voltage_swing: lane_level_config,
1904	lane_count: it6505->lane_count))
1905	goto cr_train_fail;
1906
1907	for (j = 0; j < it6505->lane_count; j++) {
1908	lane_voltage_pre_emphasis->voltage_swing[j] =
1909	drm_dp_get_adjust_request_voltage(link_status,
1910	lane: j) >>
1911	DP_TRAIN_VOLTAGE_SWING_SHIFT;
1912	lane_voltage_pre_emphasis->pre_emphasis[j] =
1913	drm_dp_get_adjust_request_pre_emphasis(link_status,
1914	lane: j) >>
1915	DP_TRAIN_PRE_EMPHASIS_SHIFT;
1916	if (voltage_swing_adjust ==
1917	lane_voltage_pre_emphasis->voltage_swing[j] &&
1918	pre_emphasis_adjust ==
1919	lane_voltage_pre_emphasis->pre_emphasis[j]) {
1920	loop_count++;
1921	continue;
1922	}
1923
1924	voltage_swing_adjust =
1925	lane_voltage_pre_emphasis->voltage_swing[j];
1926	pre_emphasis_adjust =
1927	lane_voltage_pre_emphasis->pre_emphasis[j];
1928	loop_count = 0;
1929
1930	if (voltage_swing_adjust + pre_emphasis_adjust >
1931	MAX_EQ_LEVEL)
1932	lane_voltage_pre_emphasis->voltage_swing[j] =
1933	MAX_EQ_LEVEL -
1934	lane_voltage_pre_emphasis
1935	->pre_emphasis[j];
1936	}
1937	}
1938
1939	cr_train_fail:
1940	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1941	DP_TRAINING_PATTERN_DISABLE);
1942
1943	return false;
1944	}
1945
1946	static bool
1947	it6505_step_eq_train(struct it6505 *it6505,
1948	struct it6505_step_train_para *lane_voltage_pre_emphasis)
1949	{
1950	u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1951	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1952	const struct drm_dp_aux *aux = &it6505->aux;
1953
1954	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1955	DP_TRAINING_PATTERN_2);
1956
1957	while (loop_count < 6) {
1958	loop_count++;
1959
1960	if (!step_train_lane_voltage_para_set(it6505,
1961	lane_voltage_pre_emphasis,
1962	lane_voltage_pre_emphasis_set: lane_level_config))
1963	continue;
1964
1965	drm_dp_link_train_channel_eq_delay(aux, dpcd: it6505->dpcd);
1966	drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
1967
1968	if (!drm_dp_clock_recovery_ok(link_status, lane_count: it6505->lane_count))
1969	goto eq_train_fail;
1970
1971	if (drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count)) {
1972	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1973	DP_TRAINING_PATTERN_DISABLE);
1974	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1975	FORCE_EQ_DONE);
1976	return true;
1977	}
1978	DRM_DEV_DEBUG_DRIVER(it6505->dev, "eq not done");
1979
1980	for (i = 0; i < it6505->lane_count; i++) {
1981	lane_voltage_pre_emphasis->voltage_swing[i] =
1982	drm_dp_get_adjust_request_voltage(link_status,
1983	lane: i) >>
1984	DP_TRAIN_VOLTAGE_SWING_SHIFT;
1985	lane_voltage_pre_emphasis->pre_emphasis[i] =
1986	drm_dp_get_adjust_request_pre_emphasis(link_status,
1987	lane: i) >>
1988	DP_TRAIN_PRE_EMPHASIS_SHIFT;
1989
1990	if (lane_voltage_pre_emphasis->voltage_swing[i] +
1991	lane_voltage_pre_emphasis->pre_emphasis[i] >
1992	MAX_EQ_LEVEL)
1993	lane_voltage_pre_emphasis->voltage_swing[i] =
1994	0x03 - lane_voltage_pre_emphasis
1995	->pre_emphasis[i];
1996	}
1997	}
1998
1999	eq_train_fail:
2000	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
2001	DP_TRAINING_PATTERN_DISABLE);
2002	return false;
2003	}
2004
2005	static bool it6505_link_start_step_train(struct it6505 *it6505)
2006	{
2007	int err;
2008	struct it6505_step_train_para lane_voltage_pre_emphasis = {
2009	.voltage_swing = { 0 },
2010	.pre_emphasis = { 0 },
2011	};
2012
2013	DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2014	err = it6505_drm_dp_link_configure(it6505);
2015
2016	if (err < 0)
2017	return false;
2018	if (!it6505_step_cr_train(it6505, lane_voltage_pre_emphasis: &lane_voltage_pre_emphasis))
2019	return false;
2020	if (!it6505_step_eq_train(it6505, lane_voltage_pre_emphasis: &lane_voltage_pre_emphasis))
2021	return false;
2022	return true;
2023	}
2024
2025	static bool it6505_get_video_status(struct it6505 *it6505)
2026	{
2027	int reg_0d;
2028
2029	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
2030
2031	if (reg_0d < 0)
2032	return false;
2033
2034	return reg_0d & VIDEO_STB;
2035	}
2036
2037	static void it6505_reset_hdcp(struct it6505 *it6505)
2038	{
2039	it6505->hdcp_status = HDCP_AUTH_IDLE;
2040	/* Disable CP_Desired */
2041	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, value: 0x00);
2042	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
2043	}
2044
2045	static void it6505_start_hdcp(struct it6505 *it6505)
2046	{
2047	struct device *dev = it6505->dev;
2048
2049	DRM_DEV_DEBUG_DRIVER(dev, "start");
2050	it6505_reset_hdcp(it6505);
2051	queue_delayed_work(wq: system_wq, dwork: &it6505->hdcp_work,
2052	delay: msecs_to_jiffies(m: 2400));
2053	}
2054
2055	static void it6505_stop_hdcp(struct it6505 *it6505)
2056	{
2057	it6505_reset_hdcp(it6505);
2058	cancel_delayed_work(dwork: &it6505->hdcp_work);
2059	}
2060
2061	static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
2062	{
2063	int i, ones = 0;
2064
2065	/* KSV has 20 1's and 20 0's */
2066	for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
2067	ones += hweight8(ksv[i]);
2068	if (ones != 20)
2069	return false;
2070	return true;
2071	}
2072
2073	static void it6505_hdcp_part1_auth(struct it6505 *it6505)
2074	{
2075	struct device *dev = it6505->dev;
2076	u8 hdcp_bcaps;
2077
2078	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, value: 0x00);
2079	/* Disable CP_Desired */
2080	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, value: 0x00);
2081
2082	usleep_range(min: 1000, max: 1500);
2083	hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
2084	DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
2085	hdcp_bcaps);
2086
2087	if (!hdcp_bcaps)
2088	return;
2089
2090	/* clear the repeater List Chk Done and fail bit */
2091	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2092	HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2093	value: 0x00);
2094
2095	/* Enable An Generator */
2096	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
2097	/* delay1ms(10);*/
2098	usleep_range(min: 10000, max: 15000);
2099	/* Stop An Generator */
2100	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, value: 0x00);
2101
2102	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
2103
2104	it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
2105	HDCP_TRIGGER_START);
2106
2107	it6505->hdcp_status = HDCP_AUTH_GOING;
2108	}
2109
2110	static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
2111	{
2112	struct device *dev = it6505->dev;
2113	u8 binfo[2];
2114	int down_stream_count, err, msg_count = 0;
2115
2116	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, dpcd: binfo,
2117	ARRAY_SIZE(binfo));
2118
2119	if (err < 0) {
2120	dev_err(dev, "Read binfo value Fail");
2121	return err;
2122	}
2123
2124	down_stream_count = binfo[0] & 0x7F;
2125	DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
2126	binfo);
2127
2128	if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
2129	dev_err(dev, "HDCP max cascade device exceed");
2130	return 0;
2131	}
2132
2133	if (!down_stream_count ||
2134	down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
2135	dev_err(dev, "HDCP down stream count Error %d",
2136	down_stream_count);
2137	return 0;
2138	}
2139	err = it6505_get_ksvlist(it6505, buf: sha1_input, len: down_stream_count * 5);
2140	if (err < 0)
2141	return err;
2142
2143	msg_count += down_stream_count * 5;
2144
2145	it6505->hdcp_down_stream_count = down_stream_count;
2146	sha1_input[msg_count++] = binfo[0];
2147	sha1_input[msg_count++] = binfo[1];
2148
2149	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
2150	HDCP_EN_M0_READ);
2151
2152	err = regmap_bulk_read(map: it6505->regmap, REG_M0_0_7,
2153	val: sha1_input + msg_count, val_count: 8);
2154
2155	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, value: 0x00);
2156
2157	if (err < 0) {
2158	dev_err(dev, " Warning, Read M value Fail");
2159	return err;
2160	}
2161
2162	msg_count += 8;
2163
2164	return msg_count;
2165	}
2166
2167	static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2168	{
2169	struct device *dev = it6505->dev;
2170	u8 av[5][4], bv[5][4];
2171	int i, err, retry;
2172
2173	i = it6505_setup_sha1_input(it6505, sha1_input: it6505->sha1_input);
2174	if (i <= 0) {
2175	dev_err(dev, "SHA-1 Input length error %d", i);
2176	return false;
2177	}
2178
2179	sha1(data: it6505->sha1_input, len: i, out: (u8 *)av);
2180	/*1B-05 V' must retry 3 times */
2181	for (retry = 0; retry < 3; retry++) {
2182	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), dpcd: (u8 *)bv,
2183	num: sizeof(bv));
2184
2185	if (err < 0) {
2186	dev_err(dev, "Read V' value Fail %d", retry);
2187	continue;
2188	}
2189
2190	for (i = 0; i < 5; i++)
2191	if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2192	bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2193	break;
2194
2195	if (i == 5) {
2196	DRM_DEV_DEBUG_DRIVER(dev, "V' all match!! %d", retry);
2197	return true;
2198	}
2199	}
2200
2201	DRM_DEV_DEBUG_DRIVER(dev, "V' NOT match!! %d", retry);
2202	return false;
2203	}
2204
2205	static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2206	{
2207	struct it6505 *it6505 = container_of(work, struct it6505,
2208	hdcp_wait_ksv_list);
2209	struct device *dev = it6505->dev;
2210	u8 bstatus;
2211	bool ksv_list_check;
2212	/* 1B-04 wait ksv list for 5s */
2213	unsigned long timeout = jiffies +
2214	msecs_to_jiffies(m: 5000) + 1;
2215
2216	for (;;) {
2217	if (!it6505_get_sink_hpd_status(it6505))
2218	return;
2219
2220	bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2221
2222	if (bstatus & DP_BSTATUS_READY)
2223	break;
2224
2225	if (time_after(jiffies, timeout)) {
2226	DRM_DEV_DEBUG_DRIVER(dev, "KSV list wait timeout");
2227	goto timeout;
2228	}
2229
2230	msleep(msecs: 20);
2231	}
2232
2233	ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2234	DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2235	ksv_list_check ? "pass" : "fail");
2236
2237	if (ksv_list_check)
2238	return;
2239
2240	timeout:
2241	it6505_start_hdcp(it6505);
2242	}
2243
2244	static void it6505_hdcp_work(struct work_struct *work)
2245	{
2246	struct it6505 *it6505 = container_of(work, struct it6505,
2247	hdcp_work.work);
2248	struct device *dev = it6505->dev;
2249	int ret;
2250	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2251
2252	DRM_DEV_DEBUG_DRIVER(dev, "start");
2253
2254	if (!it6505_get_sink_hpd_status(it6505))
2255	return;
2256
2257	ret = drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
2258	DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2259	(int)sizeof(link_status), link_status);
2260
2261	if (ret < 0 || !drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count) ||
2262	!it6505_get_video_status(it6505)) {
2263	DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2264	return;
2265	}
2266
2267	ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, dpcd: it6505->bksvs,
2268	ARRAY_SIZE(it6505->bksvs));
2269	if (ret < 0) {
2270	dev_err(dev, "fail to get bksv ret: %d", ret);
2271	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2272	HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2273	}
2274
2275	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2276	(int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2277
2278	if (!it6505_hdcp_is_ksv_valid(ksv: it6505->bksvs)) {
2279	dev_err(dev, "Display Port bksv not valid");
2280	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2281	HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2282	}
2283
2284	it6505_hdcp_part1_auth(it6505);
2285	}
2286
2287	static void it6505_show_hdcp_info(struct it6505 *it6505)
2288	{
2289	struct device *dev = it6505->dev;
2290	int i;
2291	u8 *sha1 = it6505->sha1_input;
2292
2293	DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2294	it6505->hdcp_status, it6505->is_repeater);
2295	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2296	(int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2297
2298	if (it6505->is_repeater) {
2299	DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2300	it6505->hdcp_down_stream_count);
2301	DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2302	(int)ARRAY_SIZE(it6505->sha1_input),
2303	it6505->sha1_input);
2304	for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2305	DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2306	DRM_HDCP_KSV_LEN, sha1);
2307	sha1 += DRM_HDCP_KSV_LEN;
2308	}
2309	DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2310	sha1, sha1 + 2);
2311	}
2312	}
2313
2314	static void it6505_stop_link_train(struct it6505 *it6505)
2315	{
2316	it6505->link_state = LINK_IDLE;
2317	cancel_work_sync(work: &it6505->link_works);
2318	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2319	}
2320
2321	static void it6505_link_train_ok(struct it6505 *it6505)
2322	{
2323	struct device *dev = it6505->dev;
2324
2325	it6505->link_state = LINK_OK;
2326	/* disalbe mute enable avi info frame */
2327	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, value: 0x00);
2328	it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2329	EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2330
2331	if (it6505_audio_input(it6505)) {
2332	DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2333	it6505_enable_audio(it6505);
2334	}
2335
2336	if (it6505->hdcp_desired)
2337	it6505_start_hdcp(it6505);
2338	}
2339
2340	static void it6505_link_step_train_process(struct it6505 *it6505)
2341	{
2342	struct device *dev = it6505->dev;
2343	int ret, i, step_retry = 3;
2344
2345	DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2346
2347	if (it6505->sink_count == 0) {
2348	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2349	it6505->sink_count);
2350	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2351	FORCE_EQ_DONE);
2352	return;
2353	}
2354
2355	if (!it6505->step_train) {
2356	DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2357	return;
2358	}
2359
2360	/* step training start here */
2361	for (i = 0; i < step_retry; i++) {
2362	it6505_link_reset_step_train(it6505);
2363	ret = it6505_link_start_step_train(it6505);
2364	DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2365	ret ? "pass" : "failed", i + 1);
2366	if (ret) {
2367	it6505_link_train_ok(it6505);
2368	return;
2369	}
2370	}
2371
2372	DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2373	it6505->link_state = LINK_IDLE;
2374	it6505_video_reset(it6505);
2375	}
2376
2377	static void it6505_link_training_work(struct work_struct *work)
2378	{
2379	struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2380	struct device *dev = it6505->dev;
2381	int ret;
2382
2383	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2384	it6505->sink_count);
2385
2386	if (!it6505_get_sink_hpd_status(it6505))
2387	return;
2388
2389	it6505_link_training_setup(it6505);
2390	it6505_reset_hdcp(it6505);
2391	it6505_aux_reset(it6505);
2392
2393	if (it6505->auto_train_retry < 1) {
2394	it6505_link_step_train_process(it6505);
2395	return;
2396	}
2397
2398	ret = it6505_link_start_auto_train(it6505);
2399	DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2400	ret ? "pass" : "failed", it6505->auto_train_retry);
2401
2402	if (ret) {
2403	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2404	it6505_link_train_ok(it6505);
2405	} else {
2406	it6505->auto_train_retry--;
2407	it6505_dump(it6505);
2408	}
2409
2410	}
2411
2412	static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2413	{
2414	enum drm_connector_status status = it6505->connector_status;
2415
2416	if (it6505->plugged_cb && it6505->codec_dev)
2417	it6505->plugged_cb(it6505->codec_dev,
2418	status == connector_status_connected);
2419	}
2420
2421	static void it6505_remove_edid(struct it6505 *it6505)
2422	{
2423	drm_edid_free(drm_edid: it6505->cached_edid);
2424	it6505->cached_edid = NULL;
2425	}
2426
2427	static int it6505_process_hpd_irq(struct it6505 *it6505)
2428	{
2429	struct device *dev = it6505->dev;
2430	int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2431	u8 link_status[DP_LINK_STATUS_SIZE];
2432
2433	if (!it6505_get_sink_hpd_status(it6505)) {
2434	DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2435	it6505->sink_count = 0;
2436	return 0;
2437	}
2438
2439	ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2440	if (ret < 0)
2441	return ret;
2442
2443	dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2444	DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2445	dpcd_sink_count, it6505->sink_count);
2446
2447	if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2448	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2449	it6505->sink_count = dpcd_sink_count;
2450	it6505_reset_logic(it6505);
2451	it6505_int_mask_enable(it6505);
2452	it6505_init(it6505);
2453	it6505_remove_edid(it6505);
2454	return 0;
2455	}
2456
2457	dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2458	if (dp_irq_vector < 0)
2459	return dp_irq_vector;
2460
2461	DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2462
2463	if (dp_irq_vector & DP_CP_IRQ) {
2464	bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2465	if (bstatus < 0)
2466	return bstatus;
2467
2468	DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2469
2470	/*Check BSTATUS when recive CP_IRQ */
2471	if (bstatus & DP_BSTATUS_R0_PRIME_READY &&
2472	it6505->hdcp_status == HDCP_AUTH_GOING)
2473	it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2474	HDCP_TRIGGER_CPIRQ);
2475	else if (bstatus & (DP_BSTATUS_REAUTH_REQ | DP_BSTATUS_LINK_FAILURE) &&
2476	it6505->hdcp_status == HDCP_AUTH_DONE)
2477	it6505_start_hdcp(it6505);
2478	}
2479
2480	ret = drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
2481	if (ret < 0) {
2482	dev_err(dev, "Fail to read link status ret: %d", ret);
2483	return ret;
2484	}
2485
2486	DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2487	(int)ARRAY_SIZE(link_status), link_status);
2488
2489	if (!drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count)) {
2490	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2491	it6505_video_reset(it6505);
2492	}
2493
2494	return 0;
2495	}
2496
2497	static void it6505_irq_hpd(struct it6505 *it6505)
2498	{
2499	struct device *dev = it6505->dev;
2500	int dp_sink_count;
2501
2502	it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2503	DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2504	it6505->hpd_state ? "high" : "low");
2505
2506	if (it6505->hpd_state) {
2507	wait_for_completion_timeout(x: &it6505->extcon_completion,
2508	timeout: msecs_to_jiffies(m: 1000));
2509	it6505_aux_on(it6505);
2510	if (it6505->dpcd[0] == 0) {
2511	it6505_get_dpcd(it6505, DP_DPCD_REV, dpcd: it6505->dpcd,
2512	ARRAY_SIZE(it6505->dpcd));
2513	it6505_variable_config(it6505);
2514	it6505_parse_link_capabilities(it6505);
2515	}
2516	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2517
2518	drm_dp_link_power_up(aux: &it6505->aux, revision: it6505->link.revision);
2519	dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2520	it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2521
2522	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2523	it6505->sink_count);
2524
2525	it6505_lane_termination_on(it6505);
2526	it6505_lane_power_on(it6505);
2527
2528	/*
2529	* for some dongle which issue HPD_irq
2530	* when sink count change from 0->1
2531	* it6505 not able to receive HPD_IRQ
2532	* if HW never go into trainig done
2533	*/
2534
2535	if (it6505->branch_device && it6505->sink_count == 0)
2536	schedule_work(work: &it6505->link_works);
2537
2538	if (!it6505_get_video_status(it6505))
2539	it6505_video_reset(it6505);
2540	} else {
2541	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2542	it6505_remove_edid(it6505);
2543
2544	if (it6505->hdcp_desired)
2545	it6505_stop_hdcp(it6505);
2546
2547	it6505_video_disable(it6505);
2548	it6505_disable_audio(it6505);
2549	it6505_stop_link_train(it6505);
2550	it6505_lane_off(it6505);
2551	it6505_link_reset_step_train(it6505);
2552	}
2553
2554	if (it6505->bridge.dev)
2555	drm_helper_hpd_irq_event(dev: it6505->bridge.dev);
2556	}
2557
2558	static void it6505_irq_hpd_irq(struct it6505 *it6505)
2559	{
2560	struct device *dev = it6505->dev;
2561
2562	DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2563
2564	if (it6505_process_hpd_irq(it6505) < 0)
2565	DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2566	}
2567
2568	static void it6505_irq_scdt(struct it6505 *it6505)
2569	{
2570	struct device *dev = it6505->dev;
2571	bool data;
2572
2573	data = it6505_get_video_status(it6505);
2574	DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2575	data ? "stable" : "unstable");
2576	it6505_calc_video_info(it6505);
2577	it6505_link_reset_step_train(it6505);
2578
2579	if (data)
2580	schedule_work(work: &it6505->link_works);
2581	}
2582
2583	static void it6505_irq_hdcp_done(struct it6505 *it6505)
2584	{
2585	struct device *dev = it6505->dev;
2586
2587	DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2588	it6505->hdcp_status = HDCP_AUTH_DONE;
2589	it6505_show_hdcp_info(it6505);
2590	}
2591
2592	static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2593	{
2594	struct device *dev = it6505->dev;
2595
2596	DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2597	it6505->hdcp_status = HDCP_AUTH_IDLE;
2598	it6505_show_hdcp_info(it6505);
2599	it6505_start_hdcp(it6505);
2600	}
2601
2602	static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2603	{
2604	struct device *dev = it6505->dev;
2605
2606	DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2607	}
2608
2609	static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2610	{
2611	struct device *dev = it6505->dev;
2612
2613	DRM_DEV_DEBUG_DRIVER(dev, "HDCP repeater R0 event Interrupt");
2614	/* 1B01 HDCP encription should start when R0 is ready*/
2615	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2616	HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2617
2618	schedule_work(work: &it6505->hdcp_wait_ksv_list);
2619	}
2620
2621	static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2622	{
2623	struct device *dev = it6505->dev;
2624
2625	DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2626
2627	if (it6505_audio_input(it6505))
2628	it6505_enable_audio(it6505);
2629	}
2630
2631	static void it6505_irq_link_train_fail(struct it6505 *it6505)
2632	{
2633	struct device *dev = it6505->dev;
2634
2635	DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2636	schedule_work(work: &it6505->link_works);
2637	}
2638
2639	static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2640	{
2641	return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2642	}
2643
2644	static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status)
2645	{
2646	struct device *dev = it6505->dev;
2647	int reg_0d, reg_int03;
2648
2649	/*
2650	* When video SCDT change with video not stable,
2651	* Or video FIFO error, need video reset
2652	*/
2653
2654	if ((!it6505_get_video_status(it6505) &&
2655	(it6505_test_bit(INT_SCDT_CHANGE, addr: (unsigned int *)int_status))) ||
2656	(it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW,
2657	addr: (unsigned int *)int_status)) ||
2658	(it6505_test_bit(BIT_INT_VID_FIFO_ERROR,
2659	addr: (unsigned int *)int_status))) {
2660	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2661	flush_work(work: &it6505->link_works);
2662	it6505_stop_hdcp(it6505);
2663	it6505_video_reset(it6505);
2664
2665	usleep_range(min: 10000, max: 11000);
2666
2667	/*
2668	* Clear FIFO error IRQ to prevent fifo error -> reset loop
2669	* HW will trigger SCDT change IRQ again when video stable
2670	*/
2671
2672	reg_int03 = it6505_read(it6505, INT_STATUS_03);
2673	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
2674
2675	reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
2676	it6505_write(it6505, INT_STATUS_03, reg_val: reg_int03);
2677
2678	DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03);
2679	DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d);
2680
2681	return;
2682	}
2683
2684	if (it6505_test_bit(INT_SCDT_CHANGE, addr: (unsigned int *)int_status))
2685	it6505_irq_scdt(it6505);
2686	}
2687
2688	static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2689	{
2690	struct it6505 *it6505 = data;
2691	struct device *dev = it6505->dev;
2692	static const struct {
2693	int bit;
2694	void (*handler)(struct it6505 *it6505);
2695	} irq_vec[] = {
2696	{ BIT_INT_HPD, it6505_irq_hpd },
2697	{ BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2698	{ BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2699	{ BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2700	{ BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2701	{ BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2702	{ BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2703	{ BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2704	};
2705	int int_status[3], i;
2706
2707	if (it6505->enable_drv_hold || !it6505->powered)
2708	return IRQ_HANDLED;
2709
2710	pm_runtime_get_sync(dev);
2711
2712	int_status[0] = it6505_read(it6505, INT_STATUS_01);
2713	int_status[1] = it6505_read(it6505, INT_STATUS_02);
2714	int_status[2] = it6505_read(it6505, INT_STATUS_03);
2715
2716	it6505_write(it6505, INT_STATUS_01, reg_val: int_status[0]);
2717	it6505_write(it6505, INT_STATUS_02, reg_val: int_status[1]);
2718	it6505_write(it6505, INT_STATUS_03, reg_val: int_status[2]);
2719
2720	DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2721	DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2722	DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2723	it6505_debug_print(it6505, REG_SYSTEM_STS, prefix: "");
2724
2725	if (it6505_test_bit(bit: irq_vec[0].bit, addr: (unsigned int *)int_status))
2726	irq_vec[0].handler(it6505);
2727
2728	if (it6505->hpd_state) {
2729	for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2730	if (it6505_test_bit(bit: irq_vec[i].bit, addr: (unsigned int *)int_status))
2731	irq_vec[i].handler(it6505);
2732	}
2733	it6505_irq_video_handler(it6505, int_status: (unsigned int *)int_status);
2734	}
2735
2736	pm_runtime_put_sync(dev);
2737
2738	return IRQ_HANDLED;
2739	}
2740
2741	static int it6505_poweron(struct it6505 *it6505)
2742	{
2743	struct device *dev = it6505->dev;
2744	struct it6505_platform_data *pdata = &it6505->pdata;
2745	int err;
2746
2747	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2748
2749	if (it6505->powered) {
2750	DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2751	return 0;
2752	}
2753
2754	if (pdata->pwr18) {
2755	err = regulator_enable(regulator: pdata->pwr18);
2756	if (err) {
2757	DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2758	err);
2759	return err;
2760	}
2761	}
2762
2763	if (pdata->ovdd) {
2764	/* time interval between IVDD and OVDD at least be 1ms */
2765	usleep_range(min: 1000, max: 2000);
2766	err = regulator_enable(regulator: pdata->ovdd);
2767	if (err) {
2768	regulator_disable(regulator: pdata->pwr18);
2769	return err;
2770	}
2771	}
2772	/* time interval between OVDD and SYSRSTN at least be 10ms */
2773	if (pdata->gpiod_reset) {
2774	usleep_range(min: 10000, max: 20000);
2775	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 1);
2776	usleep_range(min: 1000, max: 2000);
2777	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 0);
2778	usleep_range(min: 25000, max: 35000);
2779	}
2780
2781	it6505->powered = true;
2782	it6505_reset_logic(it6505);
2783	it6505_int_mask_enable(it6505);
2784	it6505_init(it6505);
2785	it6505_lane_off(it6505);
2786
2787	enable_irq(irq: it6505->irq);
2788
2789	return 0;
2790	}
2791
2792	static int it6505_poweroff(struct it6505 *it6505)
2793	{
2794	struct device *dev = it6505->dev;
2795	struct it6505_platform_data *pdata = &it6505->pdata;
2796	int err;
2797
2798	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2799
2800	if (!it6505->powered) {
2801	DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2802	return 0;
2803	}
2804
2805	disable_irq_nosync(irq: it6505->irq);
2806
2807	if (pdata->gpiod_reset)
2808	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 1);
2809
2810	if (pdata->pwr18) {
2811	err = regulator_disable(regulator: pdata->pwr18);
2812	if (err)
2813	return err;
2814	}
2815
2816	if (pdata->ovdd) {
2817	err = regulator_disable(regulator: pdata->ovdd);
2818	if (err)
2819	return err;
2820	}
2821
2822	it6505->powered = false;
2823	it6505->sink_count = 0;
2824
2825	return 0;
2826	}
2827
2828	static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2829	{
2830	struct device *dev = it6505->dev;
2831	enum drm_connector_status status = connector_status_disconnected;
2832	int dp_sink_count;
2833
2834	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2835	it6505->sink_count, it6505->powered);
2836
2837	mutex_lock(&it6505->mode_lock);
2838
2839	if (!it6505->powered)
2840	goto unlock;
2841
2842	if (it6505->enable_drv_hold) {
2843	status = it6505->hpd_state ? connector_status_connected :
2844	connector_status_disconnected;
2845	goto unlock;
2846	}
2847
2848	if (it6505->hpd_state) {
2849	drm_dp_link_power_up(aux: &it6505->aux, revision: it6505->link.revision);
2850	dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2851	it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2852	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2853	it6505->sink_count, it6505->branch_device);
2854
2855	if (it6505->branch_device) {
2856	status = (it6505->sink_count != 0) ?
2857	connector_status_connected :
2858	connector_status_disconnected;
2859	} else {
2860	status = connector_status_connected;
2861	}
2862	} else {
2863	it6505->sink_count = 0;
2864	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2865	}
2866
2867	unlock:
2868	if (it6505->connector_status != status) {
2869	it6505->connector_status = status;
2870	it6505_plugged_status_to_codec(it6505);
2871	}
2872
2873	mutex_unlock(lock: &it6505->mode_lock);
2874
2875	return status;
2876	}
2877
2878	static int it6505_extcon_notifier(struct notifier_block *self,
2879	unsigned long event, void *ptr)
2880	{
2881	struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2882
2883	schedule_work(work: &it6505->extcon_wq);
2884	return NOTIFY_DONE;
2885	}
2886
2887	static void it6505_extcon_work(struct work_struct *work)
2888	{
2889	struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2890	struct device *dev = it6505->dev;
2891	int state, ret;
2892
2893	if (it6505->enable_drv_hold)
2894	return;
2895
2896	mutex_lock(&it6505->extcon_lock);
2897
2898	state = extcon_get_state(edev: it6505->extcon, EXTCON_DISP_DP);
2899	DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2900
2901	if (state == it6505->extcon_state || unlikely(state < 0))
2902	goto unlock;
2903	it6505->extcon_state = state;
2904	if (state) {
2905	DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2906	msleep(msecs: 100);
2907	ret = pm_runtime_get_sync(dev);
2908
2909	/*
2910	* On system resume, extcon_work can be triggered before
2911	* pm_runtime_force_resume re-enables runtime power management.
2912	* Handling the error here to make sure the bridge is powered on.
2913	*/
2914	if (ret < 0)
2915	it6505_poweron(it6505);
2916
2917	complete_all(&it6505->extcon_completion);
2918	} else {
2919	DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2920	pm_runtime_put_sync(dev);
2921	reinit_completion(x: &it6505->extcon_completion);
2922
2923	drm_helper_hpd_irq_event(dev: it6505->bridge.dev);
2924	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2925	DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2926	}
2927
2928	unlock:
2929	mutex_unlock(lock: &it6505->extcon_lock);
2930	}
2931
2932	static int it6505_use_notifier_module(struct it6505 *it6505)
2933	{
2934	int ret;
2935	struct device *dev = it6505->dev;
2936
2937	it6505->event_nb.notifier_call = it6505_extcon_notifier;
2938	INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2939	ret = devm_extcon_register_notifier(dev: it6505->dev,
2940	edev: it6505->extcon, EXTCON_DISP_DP,
2941	nb: &it6505->event_nb);
2942	if (ret) {
2943	dev_err(dev, "failed to register notifier for DP");
2944	return ret;
2945	}
2946
2947	schedule_work(work: &it6505->extcon_wq);
2948
2949	return 0;
2950	}
2951
2952	static void it6505_remove_notifier_module(struct it6505 *it6505)
2953	{
2954	if (it6505->extcon) {
2955	devm_extcon_unregister_notifier(dev: it6505->dev,
2956	edev: it6505->extcon, EXTCON_DISP_DP,
2957	nb: &it6505->event_nb);
2958
2959	flush_work(work: &it6505->extcon_wq);
2960	}
2961	}
2962
2963	static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2964	{
2965	struct it6505 *it6505 = container_of(work, struct it6505,
2966	delayed_audio.work);
2967
2968	DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2969
2970	if (!it6505->powered)
2971	return;
2972
2973	if (!it6505->enable_drv_hold)
2974	it6505_enable_audio(it6505);
2975	}
2976
2977	static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2978	struct hdmi_codec_params
2979	*params)
2980	{
2981	struct device *dev = it6505->dev;
2982	int i = 0;
2983
2984	DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2985	params->sample_rate, params->sample_width,
2986	params->cea.channels);
2987
2988	if (!it6505->bridge.encoder)
2989	return -ENODEV;
2990
2991	if (params->cea.channels <= 1 || params->cea.channels > 8) {
2992	DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2993	it6505->audio.channel_count);
2994	return -EINVAL;
2995	}
2996
2997	it6505->audio.channel_count = params->cea.channels;
2998
2999	while (i < ARRAY_SIZE(audio_sample_rate_map) &&
3000	params->sample_rate !=
3001	audio_sample_rate_map[i].sample_rate_value) {
3002	i++;
3003	}
3004	if (i == ARRAY_SIZE(audio_sample_rate_map)) {
3005	DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
3006	params->sample_rate);
3007	return -EINVAL;
3008	}
3009	it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
3010
3011	switch (params->sample_width) {
3012	case 16:
3013	it6505->audio.word_length = WORD_LENGTH_16BIT;
3014	break;
3015	case 18:
3016	it6505->audio.word_length = WORD_LENGTH_18BIT;
3017	break;
3018	case 20:
3019	it6505->audio.word_length = WORD_LENGTH_20BIT;
3020	break;
3021	case 24:
3022	case 32:
3023	it6505->audio.word_length = WORD_LENGTH_24BIT;
3024	break;
3025	default:
3026	DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
3027	params->sample_width);
3028	return -EINVAL;
3029	}
3030
3031	return 0;
3032	}
3033
3034	static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
3035	{
3036	struct it6505 *it6505 = dev_get_drvdata(dev);
3037
3038	if (it6505->powered)
3039	it6505_disable_audio(it6505);
3040	}
3041
3042	static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
3043	void *data,
3044	hdmi_codec_plugged_cb fn,
3045	struct device *codec_dev)
3046	{
3047	struct it6505 *it6505 = data;
3048
3049	it6505->plugged_cb = fn;
3050	it6505->codec_dev = codec_dev;
3051	it6505_plugged_status_to_codec(it6505);
3052
3053	return 0;
3054	}
3055
3056	static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
3057	{
3058	return container_of(bridge, struct it6505, bridge);
3059	}
3060
3061	static int it6505_bridge_attach(struct drm_bridge *bridge,
3062	struct drm_encoder *encoder,
3063	enum drm_bridge_attach_flags flags)
3064	{
3065	struct it6505 *it6505 = bridge_to_it6505(bridge);
3066	struct device *dev = it6505->dev;
3067	int ret;
3068
3069	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
3070	DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
3071	return -EINVAL;
3072	}
3073
3074	/* Register aux channel */
3075	it6505->aux.drm_dev = bridge->dev;
3076
3077	ret = drm_dp_aux_register(aux: &it6505->aux);
3078
3079	if (ret < 0) {
3080	dev_err(dev, "Failed to register aux: %d", ret);
3081	return ret;
3082	}
3083
3084	if (it6505->extcon) {
3085	ret = it6505_use_notifier_module(it6505);
3086	if (ret < 0) {
3087	dev_err(dev, "use notifier module failed");
3088	return ret;
3089	}
3090	}
3091
3092	return 0;
3093	}
3094
3095	static void it6505_bridge_detach(struct drm_bridge *bridge)
3096	{
3097	struct it6505 *it6505 = bridge_to_it6505(bridge);
3098
3099	flush_work(work: &it6505->link_works);
3100	it6505_remove_notifier_module(it6505);
3101	}
3102
3103	static enum drm_mode_status
3104	it6505_bridge_mode_valid(struct drm_bridge *bridge,
3105	const struct drm_display_info *info,
3106	const struct drm_display_mode *mode)
3107	{
3108	struct it6505 *it6505 = bridge_to_it6505(bridge);
3109
3110	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3111	return MODE_NO_INTERLACE;
3112
3113	if (mode->clock > it6505->max_dpi_pixel_clock)
3114	return MODE_CLOCK_HIGH;
3115
3116	it6505->video_info.clock = mode->clock;
3117
3118	return MODE_OK;
3119	}
3120
3121	static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
3122	struct drm_atomic_state *state)
3123	{
3124	struct it6505 *it6505 = bridge_to_it6505(bridge);
3125	struct device *dev = it6505->dev;
3126	struct hdmi_avi_infoframe frame;
3127	struct drm_crtc_state *crtc_state;
3128	struct drm_connector_state *conn_state;
3129	struct drm_display_mode *mode;
3130	struct drm_connector *connector;
3131	int ret;
3132
3133	DRM_DEV_DEBUG_DRIVER(dev, "start");
3134
3135	connector = drm_atomic_get_new_connector_for_encoder(state,
3136	encoder: bridge->encoder);
3137
3138	if (WARN_ON(!connector))
3139	return;
3140
3141	conn_state = drm_atomic_get_new_connector_state(state, connector);
3142
3143	if (WARN_ON(!conn_state))
3144	return;
3145
3146	crtc_state = drm_atomic_get_new_crtc_state(state, crtc: conn_state->crtc);
3147
3148	if (WARN_ON(!crtc_state))
3149	return;
3150
3151	mode = &crtc_state->adjusted_mode;
3152
3153	if (WARN_ON(!mode))
3154	return;
3155
3156	ret = drm_hdmi_avi_infoframe_from_display_mode(frame: &frame,
3157	connector,
3158	mode);
3159	if (ret)
3160	dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
3161
3162	it6505_update_video_parameter(it6505, mode);
3163
3164	ret = it6505_send_video_infoframe(it6505, frame: &frame);
3165
3166	if (ret)
3167	dev_err(dev, "Failed to send AVI infoframe: %d", ret);
3168
3169	it6505_int_mask_enable(it6505);
3170	it6505_video_reset(it6505);
3171
3172	drm_dp_link_power_up(aux: &it6505->aux, revision: it6505->link.revision);
3173	}
3174
3175	static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
3176	struct drm_atomic_state *state)
3177	{
3178	struct it6505 *it6505 = bridge_to_it6505(bridge);
3179	struct device *dev = it6505->dev;
3180
3181	DRM_DEV_DEBUG_DRIVER(dev, "start");
3182
3183	if (it6505->powered) {
3184	drm_dp_link_power_down(aux: &it6505->aux, revision: it6505->link.revision);
3185	it6505_video_disable(it6505);
3186	}
3187	}
3188
3189	static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
3190	struct drm_atomic_state *state)
3191	{
3192	struct it6505 *it6505 = bridge_to_it6505(bridge);
3193	struct device *dev = it6505->dev;
3194
3195	DRM_DEV_DEBUG_DRIVER(dev, "start");
3196
3197	pm_runtime_get_sync(dev);
3198	}
3199
3200	static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3201	struct drm_atomic_state *state)
3202	{
3203	struct it6505 *it6505 = bridge_to_it6505(bridge);
3204	struct device *dev = it6505->dev;
3205
3206	DRM_DEV_DEBUG_DRIVER(dev, "start");
3207
3208	pm_runtime_put_sync(dev);
3209	}
3210
3211	static enum drm_connector_status
3212	it6505_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
3213	{
3214	struct it6505 *it6505 = bridge_to_it6505(bridge);
3215
3216	return it6505_detect(it6505);
3217	}
3218
3219	static const struct drm_edid *it6505_bridge_edid_read(struct drm_bridge *bridge,
3220	struct drm_connector *connector)
3221	{
3222	struct it6505 *it6505 = bridge_to_it6505(bridge);
3223	struct device *dev = it6505->dev;
3224
3225	if (!it6505->cached_edid) {
3226	it6505->cached_edid = drm_edid_read_custom(connector,
3227	read_block: it6505_get_edid_block,
3228	context: it6505);
3229
3230	if (!it6505->cached_edid) {
3231	DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3232	return NULL;
3233	}
3234	}
3235
3236	return drm_edid_dup(drm_edid: it6505->cached_edid);
3237	}
3238
3239	static const struct drm_bridge_funcs it6505_bridge_funcs = {
3240	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3241	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3242	.atomic_reset = drm_atomic_helper_bridge_reset,
3243	.attach = it6505_bridge_attach,
3244	.detach = it6505_bridge_detach,
3245	.mode_valid = it6505_bridge_mode_valid,
3246	.atomic_enable = it6505_bridge_atomic_enable,
3247	.atomic_disable = it6505_bridge_atomic_disable,
3248	.atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3249	.atomic_post_disable = it6505_bridge_atomic_post_disable,
3250	.detect = it6505_bridge_detect,
3251	.edid_read = it6505_bridge_edid_read,
3252	};
3253
3254	static __maybe_unused int it6505_bridge_resume(struct device *dev)
3255	{
3256	struct it6505 *it6505 = dev_get_drvdata(dev);
3257
3258	return it6505_poweron(it6505);
3259	}
3260
3261	static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3262	{
3263	struct it6505 *it6505 = dev_get_drvdata(dev);
3264
3265	it6505_remove_edid(it6505);
3266
3267	return it6505_poweroff(it6505);
3268	}
3269
3270	static const struct dev_pm_ops it6505_bridge_pm_ops = {
3271	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3272	SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3273	};
3274
3275	static int it6505_init_pdata(struct it6505 *it6505)
3276	{
3277	struct it6505_platform_data *pdata = &it6505->pdata;
3278	struct device *dev = it6505->dev;
3279
3280	/* 1.0V digital core power regulator */
3281	pdata->pwr18 = devm_regulator_get(dev, id: "pwr18");
3282	if (IS_ERR(ptr: pdata->pwr18)) {
3283	dev_err(dev, "pwr18 regulator not found");
3284	return PTR_ERR(ptr: pdata->pwr18);
3285	}
3286
3287	pdata->ovdd = devm_regulator_get(dev, id: "ovdd");
3288	if (IS_ERR(ptr: pdata->ovdd)) {
3289	dev_err(dev, "ovdd regulator not found");
3290	return PTR_ERR(ptr: pdata->ovdd);
3291	}
3292
3293	pdata->gpiod_reset = devm_gpiod_get(dev, con_id: "reset", flags: GPIOD_OUT_HIGH);
3294	if (IS_ERR(ptr: pdata->gpiod_reset)) {
3295	dev_err(dev, "gpiod_reset gpio not found");
3296	return PTR_ERR(ptr: pdata->gpiod_reset);
3297	}
3298
3299	return 0;
3300	}
3301
3302	static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3303	const unsigned int min,
3304	const unsigned int max)
3305	{
3306	int ret;
3307
3308	ret = of_property_count_u32_elems(np: endpoint, propname: "data-lanes");
3309	if (ret < 0)
3310	return ret;
3311
3312	if (ret < min || ret > max)
3313	return -EINVAL;
3314
3315	return ret;
3316	}
3317
3318	static void it6505_parse_dt(struct it6505 *it6505)
3319	{
3320	struct device *dev = it6505->dev;
3321	struct device_node *np = dev->of_node, *ep = NULL;
3322	int len;
3323	u64 link_frequencies;
3324	u32 data_lanes[4];
3325	u32 *afe_setting = &it6505->afe_setting;
3326	u32 *max_lane_count = &it6505->max_lane_count;
3327	u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3328
3329	it6505->lane_swap_disabled =
3330	device_property_read_bool(dev, propname: "no-laneswap");
3331
3332	if (it6505->lane_swap_disabled)
3333	it6505->lane_swap = false;
3334
3335	if (device_property_read_u32(dev, propname: "afe-setting", val: afe_setting) == 0) {
3336	if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3337	dev_err(dev, "afe setting error, use default");
3338	*afe_setting = 0;
3339	}
3340	} else {
3341	*afe_setting = 0;
3342	}
3343
3344	ep = of_graph_get_endpoint_by_regs(parent: np, port_reg: 1, reg: 0);
3345	of_node_put(node: ep);
3346
3347	if (ep) {
3348	len = it6505_get_data_lanes_count(endpoint: ep, min: 1, max: 4);
3349
3350	if (len > 0 && len != 3) {
3351	of_property_read_u32_array(np: ep, propname: "data-lanes",
3352	out_values: data_lanes, sz: len);
3353	*max_lane_count = len;
3354	} else {
3355	*max_lane_count = MAX_LANE_COUNT;
3356	dev_err(dev, "error data-lanes, use default");
3357	}
3358	} else {
3359	*max_lane_count = MAX_LANE_COUNT;
3360	dev_err(dev, "error endpoint, use default");
3361	}
3362
3363	ep = of_graph_get_endpoint_by_regs(parent: np, port_reg: 0, reg: 0);
3364	of_node_put(node: ep);
3365
3366	if (ep) {
3367	len = of_property_read_variable_u64_array(np: ep,
3368	propname: "link-frequencies",
3369	out_values: &link_frequencies, sz_min: 0,
3370	sz_max: 1);
3371	if (len >= 0) {
3372	do_div(link_frequencies, 1000);
3373	if (link_frequencies > 297000) {
3374	dev_err(dev,
3375	"max pixel clock error, use default");
3376	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3377	} else {
3378	*max_dpi_pixel_clock = link_frequencies;
3379	}
3380	} else {
3381	dev_err(dev, "error link frequencies, use default");
3382	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3383	}
3384	} else {
3385	dev_err(dev, "error endpoint, use default");
3386	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3387	}
3388
3389	DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3390	it6505->afe_setting, it6505->max_lane_count);
3391	DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3392	it6505->max_dpi_pixel_clock);
3393	}
3394
3395	static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3396	size_t len, loff_t *ppos)
3397	{
3398	struct it6505 *it6505 = file->private_data;
3399	struct drm_display_mode *vid;
3400	u8 read_buf[READ_BUFFER_SIZE];
3401	u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3402	ssize_t ret, count;
3403
3404	if (!it6505)
3405	return -ENODEV;
3406
3407	it6505_calc_video_info(it6505);
3408	vid = &it6505->video_info;
3409	str += scnprintf(buf: str, size: end - str, fmt: "---video timing---\n");
3410	str += scnprintf(buf: str, size: end - str, fmt: "PCLK:%d.%03dMHz\n",
3411	vid->clock / 1000, vid->clock % 1000);
3412	str += scnprintf(buf: str, size: end - str, fmt: "HTotal:%d\n", vid->htotal);
3413	str += scnprintf(buf: str, size: end - str, fmt: "HActive:%d\n", vid->hdisplay);
3414	str += scnprintf(buf: str, size: end - str, fmt: "HFrontPorch:%d\n",
3415	vid->hsync_start - vid->hdisplay);
3416	str += scnprintf(buf: str, size: end - str, fmt: "HSyncWidth:%d\n",
3417	vid->hsync_end - vid->hsync_start);
3418	str += scnprintf(buf: str, size: end - str, fmt: "HBackPorch:%d\n",
3419	vid->htotal - vid->hsync_end);
3420	str += scnprintf(buf: str, size: end - str, fmt: "VTotal:%d\n", vid->vtotal);
3421	str += scnprintf(buf: str, size: end - str, fmt: "VActive:%d\n", vid->vdisplay);
3422	str += scnprintf(buf: str, size: end - str, fmt: "VFrontPorch:%d\n",
3423	vid->vsync_start - vid->vdisplay);
3424	str += scnprintf(buf: str, size: end - str, fmt: "VSyncWidth:%d\n",
3425	vid->vsync_end - vid->vsync_start);
3426	str += scnprintf(buf: str, size: end - str, fmt: "VBackPorch:%d\n",
3427	vid->vtotal - vid->vsync_end);
3428
3429	count = str - read_buf;
3430	ret = simple_read_from_buffer(to: buf, count: len, ppos, from: read_buf, available: count);
3431
3432	return ret;
3433	}
3434
3435	static int force_power_on_off_debugfs_write(void *data, u64 value)
3436	{
3437	struct it6505 *it6505 = data;
3438
3439	if (!it6505)
3440	return -ENODEV;
3441
3442	if (value)
3443	it6505_poweron(it6505);
3444	else
3445	it6505_poweroff(it6505);
3446
3447	return 0;
3448	}
3449
3450	static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3451	{
3452	struct it6505 *it6505 = data;
3453
3454	if (!it6505)
3455	return -ENODEV;
3456
3457	*buf = it6505->enable_drv_hold;
3458
3459	return 0;
3460	}
3461
3462	static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3463	{
3464	struct it6505 *it6505 = data;
3465
3466	if (!it6505)
3467	return -ENODEV;
3468
3469	it6505->enable_drv_hold = drv_hold;
3470
3471	if (it6505->enable_drv_hold) {
3472	it6505_int_mask_disable(it6505);
3473	} else {
3474	it6505_clear_int(it6505);
3475	it6505_int_mask_enable(it6505);
3476
3477	if (it6505->powered) {
3478	it6505->connector_status =
3479	it6505_get_sink_hpd_status(it6505) ?
3480	connector_status_connected :
3481	connector_status_disconnected;
3482	} else {
3483	it6505->connector_status =
3484	connector_status_disconnected;
3485	}
3486	}
3487
3488	return 0;
3489	}
3490
3491	static const struct file_operations receive_timing_fops = {
3492	.owner = THIS_MODULE,
3493	.open = simple_open,
3494	.read = receive_timing_debugfs_show,
3495	.llseek = default_llseek,
3496	};
3497
3498	DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3499	force_power_on_off_debugfs_write, "%llu\n");
3500
3501	DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3502	enable_drv_hold_debugfs_write, "%llu\n");
3503
3504	static const struct debugfs_entries debugfs_entry[] = {
3505	{ "receive_timing", &receive_timing_fops },
3506	{ "force_power_on_off", &fops_force_power },
3507	{ "enable_drv_hold", &fops_enable_drv_hold },
3508	{ NULL, NULL },
3509	};
3510
3511	static void debugfs_create_files(struct it6505 *it6505)
3512	{
3513	int i = 0;
3514
3515	while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3516	debugfs_create_file(debugfs_entry[i].name, 0644,
3517	it6505->debugfs, it6505,
3518	debugfs_entry[i].fops);
3519	i++;
3520	}
3521	}
3522
3523	static void debugfs_init(struct it6505 *it6505)
3524	{
3525	struct device *dev = it6505->dev;
3526
3527	it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3528
3529	if (IS_ERR(ptr: it6505->debugfs)) {
3530	dev_err(dev, "failed to create debugfs root");
3531	return;
3532	}
3533
3534	debugfs_create_files(it6505);
3535	}
3536
3537	static void it6505_debugfs_remove(struct it6505 *it6505)
3538	{
3539	debugfs_remove_recursive(dentry: it6505->debugfs);
3540	}
3541
3542	static void it6505_shutdown(struct i2c_client *client)
3543	{
3544	struct it6505 *it6505 = dev_get_drvdata(dev: &client->dev);
3545
3546	if (it6505->powered)
3547	it6505_lane_off(it6505);
3548	}
3549
3550	static int it6505_i2c_probe(struct i2c_client *client)
3551	{
3552	struct it6505 *it6505;
3553	struct device *dev = &client->dev;
3554	struct extcon_dev *extcon;
3555	int err;
3556
3557	it6505 = devm_drm_bridge_alloc(&client->dev, struct it6505, bridge,
3558	&it6505_bridge_funcs);
3559	if (IS_ERR(ptr: it6505))
3560	return PTR_ERR(ptr: it6505);
3561
3562	mutex_init(&it6505->extcon_lock);
3563	mutex_init(&it6505->mode_lock);
3564	mutex_init(&it6505->aux_lock);
3565
3566	it6505->bridge.of_node = client->dev.of_node;
3567	it6505->connector_status = connector_status_disconnected;
3568	it6505->dev = &client->dev;
3569	i2c_set_clientdata(client, data: it6505);
3570
3571	/* get extcon device from DTS */
3572	extcon = extcon_get_edev_by_phandle(dev, index: 0);
3573	if (PTR_ERR(ptr: extcon) == -EPROBE_DEFER)
3574	return -EPROBE_DEFER;
3575	if (IS_ERR(ptr: extcon)) {
3576	dev_err(dev, "can not get extcon device!");
3577	return PTR_ERR(ptr: extcon);
3578	}
3579
3580	it6505->extcon = extcon;
3581
3582	it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3583	if (IS_ERR(ptr: it6505->regmap)) {
3584	dev_err(dev, "regmap i2c init failed");
3585	err = PTR_ERR(ptr: it6505->regmap);
3586	return err;
3587	}
3588
3589	err = it6505_init_pdata(it6505);
3590	if (err) {
3591	dev_err(dev, "Failed to initialize pdata: %d", err);
3592	return err;
3593	}
3594
3595	it6505_parse_dt(it6505);
3596
3597	it6505->irq = client->irq;
3598
3599	if (!it6505->irq) {
3600	dev_err(dev, "Failed to get INTP IRQ");
3601	err = -ENODEV;
3602	return err;
3603	}
3604
3605	err = devm_request_threaded_irq(dev: &client->dev, irq: it6505->irq, NULL,
3606	thread_fn: it6505_int_threaded_handler,
3607	IRQF_TRIGGER_LOW | IRQF_ONESHOT |
3608	IRQF_NO_AUTOEN,
3609	devname: "it6505-intp", dev_id: it6505);
3610	if (err) {
3611	dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3612	return err;
3613	}
3614
3615	INIT_WORK(&it6505->link_works, it6505_link_training_work);
3616	INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3617	INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3618	init_completion(x: &it6505->extcon_completion);
3619	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3620	it6505->powered = false;
3621	it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3622
3623	if (DEFAULT_PWR_ON)
3624	it6505_poweron(it6505);
3625
3626	DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3627	debugfs_init(it6505);
3628	pm_runtime_enable(dev);
3629
3630	it6505->aux.name = "DP-AUX";
3631	it6505->aux.dev = dev;
3632	it6505->aux.transfer = it6505_aux_transfer;
3633	drm_dp_aux_init(aux: &it6505->aux);
3634
3635	it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3636	it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3637	DRM_BRIDGE_OP_HPD;
3638	drm_bridge_add(bridge: &it6505->bridge);
3639
3640	return 0;
3641	}
3642
3643	static void it6505_i2c_remove(struct i2c_client *client)
3644	{
3645	struct it6505 *it6505 = i2c_get_clientdata(client);
3646
3647	drm_bridge_remove(bridge: &it6505->bridge);
3648	drm_dp_aux_unregister(aux: &it6505->aux);
3649	it6505_debugfs_remove(it6505);
3650	it6505_poweroff(it6505);
3651	it6505_remove_edid(it6505);
3652	}
3653
3654	static const struct i2c_device_id it6505_id[] = {
3655	{ "it6505" },
3656	{ }
3657	};
3658
3659	MODULE_DEVICE_TABLE(i2c, it6505_id);
3660
3661	static const struct of_device_id it6505_of_match[] = {
3662	{ .compatible = "ite,it6505" },
3663	{ }
3664	};
3665	MODULE_DEVICE_TABLE(of, it6505_of_match);
3666
3667	static struct i2c_driver it6505_i2c_driver = {
3668	.driver = {
3669	.name = "it6505",
3670	.of_match_table = it6505_of_match,
3671	.pm = &it6505_bridge_pm_ops,
3672	},
3673	.probe = it6505_i2c_probe,
3674	.remove = it6505_i2c_remove,
3675	.shutdown = it6505_shutdown,
3676	.id_table = it6505_id,
3677	};
3678
3679	module_i2c_driver(it6505_i2c_driver);
3680
3681	MODULE_AUTHOR("Allen Chen <allen.chen@ite.com.tw>");
3682	MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3683	MODULE_LICENSE("GPL v2");
3684