1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/of_graph.h>
7
8#include "adv7511.h"
9
10static const struct reg_sequence adv7533_fixed_registers[] = {
11 { 0x16, 0x20 },
12 { 0x9a, 0xe0 },
13 { 0xba, 0x70 },
14 { 0xde, 0x82 },
15 { 0xe4, 0x40 },
16 { 0xe5, 0x80 },
17};
18
19static const struct reg_sequence adv7533_cec_fixed_registers[] = {
20 { 0x15, 0xd0 },
21 { 0x17, 0xd0 },
22 { 0x24, 0x20 },
23 { 0x57, 0x11 },
24 { 0x05, 0xc8 },
25};
26
27void adv7533_dsi_config_timing_gen(struct adv7511 *adv)
28{
29 struct mipi_dsi_device *dsi = adv->dsi;
30 struct drm_display_mode *mode = &adv->curr_mode;
31 unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
32 static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
33
34 hsw = mode->hsync_end - mode->hsync_start;
35 hfp = mode->hsync_start - mode->hdisplay;
36 hbp = mode->htotal - mode->hsync_end;
37 vsw = mode->vsync_end - mode->vsync_start;
38 vfp = mode->vsync_start - mode->vdisplay;
39 vbp = mode->vtotal - mode->vsync_end;
40
41 /* set pixel clock divider mode */
42 regmap_write(map: adv->regmap_cec, reg: 0x16,
43 val: clock_div_by_lanes[dsi->lanes - 2] << 3);
44
45 /* horizontal porch params */
46 regmap_write(map: adv->regmap_cec, reg: 0x28, val: mode->htotal >> 4);
47 regmap_write(map: adv->regmap_cec, reg: 0x29, val: (mode->htotal << 4) & 0xff);
48 regmap_write(map: adv->regmap_cec, reg: 0x2a, val: hsw >> 4);
49 regmap_write(map: adv->regmap_cec, reg: 0x2b, val: (hsw << 4) & 0xff);
50 regmap_write(map: adv->regmap_cec, reg: 0x2c, val: hfp >> 4);
51 regmap_write(map: adv->regmap_cec, reg: 0x2d, val: (hfp << 4) & 0xff);
52 regmap_write(map: adv->regmap_cec, reg: 0x2e, val: hbp >> 4);
53 regmap_write(map: adv->regmap_cec, reg: 0x2f, val: (hbp << 4) & 0xff);
54
55 /* vertical porch params */
56 regmap_write(map: adv->regmap_cec, reg: 0x30, val: mode->vtotal >> 4);
57 regmap_write(map: adv->regmap_cec, reg: 0x31, val: (mode->vtotal << 4) & 0xff);
58 regmap_write(map: adv->regmap_cec, reg: 0x32, val: vsw >> 4);
59 regmap_write(map: adv->regmap_cec, reg: 0x33, val: (vsw << 4) & 0xff);
60 regmap_write(map: adv->regmap_cec, reg: 0x34, val: vfp >> 4);
61 regmap_write(map: adv->regmap_cec, reg: 0x35, val: (vfp << 4) & 0xff);
62 regmap_write(map: adv->regmap_cec, reg: 0x36, val: vbp >> 4);
63 regmap_write(map: adv->regmap_cec, reg: 0x37, val: (vbp << 4) & 0xff);
64}
65
66void adv7533_dsi_power_on(struct adv7511 *adv)
67{
68 struct mipi_dsi_device *dsi = adv->dsi;
69
70 /* set number of dsi lanes */
71 regmap_write(map: adv->regmap_cec, reg: 0x1c, val: dsi->lanes << 4);
72
73 if (adv->use_timing_gen) {
74 /* reset internal timing generator */
75 regmap_write(map: adv->regmap_cec, reg: 0x27, val: 0xcb);
76 regmap_write(map: adv->regmap_cec, reg: 0x27, val: 0x8b);
77 regmap_write(map: adv->regmap_cec, reg: 0x27, val: 0xcb);
78 } else {
79 /* disable internal timing generator */
80 regmap_write(map: adv->regmap_cec, reg: 0x27, val: 0x0b);
81 }
82
83 /* enable hdmi */
84 regmap_write(map: adv->regmap_cec, reg: 0x03, val: 0x89);
85 /* disable test mode */
86 regmap_write(map: adv->regmap_cec, reg: 0x55, val: 0x00);
87
88 regmap_register_patch(map: adv->regmap_cec, regs: adv7533_cec_fixed_registers,
89 ARRAY_SIZE(adv7533_cec_fixed_registers));
90}
91
92void adv7533_dsi_power_off(struct adv7511 *adv)
93{
94 /* disable hdmi */
95 regmap_write(map: adv->regmap_cec, reg: 0x03, val: 0x0b);
96 /* disable internal timing generator */
97 regmap_write(map: adv->regmap_cec, reg: 0x27, val: 0x0b);
98}
99
100enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
101 const struct drm_display_mode *mode)
102{
103 struct mipi_dsi_device *dsi = adv->dsi;
104 u8 bpp = mipi_dsi_pixel_format_to_bpp(fmt: dsi->format);
105
106 /* Check max clock for each lane */
107 if (mode->clock * bpp > adv->info->max_lane_freq_khz * adv->num_dsi_lanes)
108 return MODE_CLOCK_HIGH;
109
110 return MODE_OK;
111}
112
113int adv7533_patch_registers(struct adv7511 *adv)
114{
115 return regmap_register_patch(map: adv->regmap,
116 regs: adv7533_fixed_registers,
117 ARRAY_SIZE(adv7533_fixed_registers));
118}
119
120int adv7533_patch_cec_registers(struct adv7511 *adv)
121{
122 return regmap_register_patch(map: adv->regmap_cec,
123 regs: adv7533_cec_fixed_registers,
124 ARRAY_SIZE(adv7533_cec_fixed_registers));
125}
126
127int adv7533_attach_dsi(struct adv7511 *adv)
128{
129 struct device *dev = &adv->i2c_main->dev;
130 struct mipi_dsi_host *host;
131 struct mipi_dsi_device *dsi;
132 int ret = 0;
133 const struct mipi_dsi_device_info info = { .type = "adv7533",
134 .channel = 0,
135 .node = NULL,
136 };
137
138 host = of_find_mipi_dsi_host_by_node(node: adv->host_node);
139 if (!host)
140 return dev_err_probe(dev, err: -EPROBE_DEFER,
141 fmt: "failed to find dsi host\n");
142
143 dsi = devm_mipi_dsi_device_register_full(dev, host, info: &info);
144 if (IS_ERR(ptr: dsi))
145 return dev_err_probe(dev, err: PTR_ERR(ptr: dsi),
146 fmt: "failed to create dsi device\n");
147
148 adv->dsi = dsi;
149
150 dsi->lanes = adv->num_dsi_lanes;
151 dsi->format = MIPI_DSI_FMT_RGB888;
152 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
153 MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
154
155 ret = devm_mipi_dsi_attach(dev, dsi);
156 if (ret < 0)
157 return dev_err_probe(dev, err: ret, fmt: "failed to attach dsi to host\n");
158
159 return 0;
160}
161
162int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv)
163{
164 u32 num_lanes;
165
166 of_property_read_u32(np, propname: "adi,dsi-lanes", out_value: &num_lanes);
167
168 if (num_lanes < 2 || num_lanes > 4)
169 return -EINVAL;
170
171 adv->num_dsi_lanes = num_lanes;
172
173 adv->host_node = of_graph_get_remote_node(node: np, port: 0, endpoint: 0);
174 if (!adv->host_node)
175 return -ENODEV;
176
177 adv->use_timing_gen = !of_property_read_bool(np,
178 propname: "adi,disable-timing-generator");
179
180 /* TODO: Check if these need to be parsed by DT or not */
181 adv->rgb = true;
182 adv->embedded_sync = false;
183
184 return 0;
185}
186

source code of linux/drivers/gpu/drm/bridge/adv7511/adv7533.c