1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2012 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/pci.h>
31
32#include <drm/drm_drv.h>
33
34#include "ast_drv.h"
35#include "ast_post.h"
36
37/*
38 * POST
39 */
40
41void ast_2000_set_def_ext_reg(struct ast_device *ast)
42{
43 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
44 u8 i, index, reg;
45 const u8 *ext_reg_info;
46
47 /* reset scratch */
48 for (i = 0x81; i <= 0x9f; i++)
49 ast_set_index_reg(ast, AST_IO_VGACRI, index: i, val: 0x00);
50
51 ext_reg_info = extreginfo;
52 index = 0xa0;
53 while (*ext_reg_info != 0xff) {
54 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, preserve_mask: 0x00, val: *ext_reg_info);
55 index++;
56 ext_reg_info++;
57 }
58
59 /* disable standard IO/MEM decode if secondary */
60 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
61
62 /* Set Ext. Default */
63 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index: 0x8c, preserve_mask: 0x00, val: 0x01);
64 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index: 0xb7, preserve_mask: 0x00, val: 0x00);
65
66 /* Enable RAMDAC for A1 */
67 reg = 0x04;
68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index: 0xb6, preserve_mask: 0xff, val: reg);
69}
70
71static const struct ast_dramstruct ast2000_dram_table_data[] = {
72 { 0x0108, 0x00000000 },
73 { 0x0120, 0x00004a21 },
74 AST_DRAMSTRUCT_UDELAY(67u),
75 { 0x0000, 0xFFFFFFFF },
76 AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000089),
77 { 0x0008, 0x22331353 },
78 { 0x000C, 0x0d07000b },
79 { 0x0010, 0x11113333 },
80 { 0x0020, 0x00110350 },
81 { 0x0028, 0x1e0828f0 },
82 { 0x0024, 0x00000001 },
83 { 0x001C, 0x00000000 },
84 { 0x0014, 0x00000003 },
85 AST_DRAMSTRUCT_UDELAY(67u),
86 { 0x0018, 0x00000131 },
87 { 0x0014, 0x00000001 },
88 AST_DRAMSTRUCT_UDELAY(67u),
89 { 0x0018, 0x00000031 },
90 { 0x0014, 0x00000001 },
91 AST_DRAMSTRUCT_UDELAY(67u),
92 { 0x0028, 0x1e0828f1 },
93 { 0x0024, 0x00000003 },
94 { 0x002C, 0x1f0f28fb },
95 { 0x0030, 0xFFFFFE01 },
96 AST_DRAMSTRUCT_INVALID,
97};
98
99static void ast_post_chip_2000(struct ast_device *ast)
100{
101 u8 j;
102 u32 temp, i;
103 const struct ast_dramstruct *dram_reg_info;
104
105 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, index: 0xd0, preserve_mask: 0xff);
106
107 if ((j & 0x80) == 0) { /* VGA only */
108 dram_reg_info = ast2000_dram_table_data;
109 ast_write32(ast, reg: 0xf004, val: 0x1e6e0000);
110 ast_write32(ast, reg: 0xf000, val: 0x1);
111 ast_write32(ast, reg: 0x10100, val: 0xa8);
112
113 do {
114 ;
115 } while (ast_read32(ast, reg: 0x10100) != 0xa8);
116
117 while (!AST_DRAMSTRUCT_IS(dram_reg_info, INVALID)) {
118 if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) {
119 for (i = 0; i < 15; i++)
120 udelay(usec: dram_reg_info->data);
121 } else {
122 ast_write32(ast, reg: 0x10000 + dram_reg_info->index,
123 val: dram_reg_info->data);
124 }
125 dram_reg_info++;
126 }
127
128 temp = ast_read32(ast, reg: 0x10140);
129 ast_write32(ast, reg: 0x10140, val: temp | 0x40);
130 }
131
132 /* wait ready */
133 do {
134 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, index: 0xd0, preserve_mask: 0xff);
135 } while ((j & 0x40) == 0);
136}
137
138int ast_2000_post(struct ast_device *ast)
139{
140 ast_2000_set_def_ext_reg(ast);
141
142 if (ast->config_mode == ast_use_p2a) {
143 ast_post_chip_2000(ast);
144 } else {
145 if (ast->tx_chip == AST_TX_SIL164) {
146 /* Enable DVO */
147 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index: 0xa3, preserve_mask: 0xcf, val: 0x80);
148 }
149 }
150
151 return 0;
152}
153
154/*
155 * Mode setting
156 */
157
158const struct ast_vbios_dclk_info ast_2000_dclk_table[] = {
159 {0x2c, 0xe7, 0x03}, /* 00: VCLK25_175 */
160 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */
161 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */
162 {0x76, 0x63, 0x01}, /* 03: VCLK36 */
163 {0xee, 0x67, 0x01}, /* 04: VCLK40 */
164 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */
165 {0xc6, 0x64, 0x01}, /* 06: VCLK50 */
166 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */
167 {0x80, 0x64, 0x00}, /* 08: VCLK65 */
168 {0x7b, 0x63, 0x00}, /* 09: VCLK75 */
169 {0x67, 0x62, 0x00}, /* 0a: VCLK78_75 */
170 {0x7c, 0x62, 0x00}, /* 0b: VCLK94_5 */
171 {0x8e, 0x62, 0x00}, /* 0c: VCLK108 */
172 {0x85, 0x24, 0x00}, /* 0d: VCLK135 */
173 {0x67, 0x22, 0x00}, /* 0e: VCLK157_5 */
174 {0x6a, 0x22, 0x00}, /* 0f: VCLK162 */
175 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */
176 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */
177 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
178 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
179 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
180 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
181 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
182 {0x77, 0x58, 0x80}, /* 17: VCLK119 */
183 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */
184 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */
185 {0x3b, 0x2c, 0x81}, /* 1a: VCLK118_25 */
186};
187
188/*
189 * Device initialization
190 */
191
192void ast_2000_detect_tx_chip(struct ast_device *ast, bool need_post)
193{
194 enum ast_tx_chip tx_chip = AST_TX_NONE;
195 u8 vgacra3;
196
197 /*
198 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
199 * enabled, in that case, assume we have a SIL164 TMDS transmitter
200 *
201 * Don't make that assumption if we the chip wasn't enabled and
202 * is at power-on reset, otherwise we'll incorrectly "detect" a
203 * SIL164 when there is none.
204 */
205 if (!need_post) {
206 vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, index: 0xa3, preserve_mask: 0xff);
207 if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
208 tx_chip = AST_TX_SIL164;
209 }
210
211 __ast_device_set_tx_chip(ast, tx_chip);
212}
213
214static const struct ast_device_quirks ast_2000_device_quirks = {
215 .crtc_mem_req_threshold_low = 31,
216 .crtc_mem_req_threshold_high = 47,
217};
218
219struct drm_device *ast_2000_device_create(struct pci_dev *pdev,
220 const struct drm_driver *drv,
221 enum ast_chip chip,
222 enum ast_config_mode config_mode,
223 void __iomem *regs,
224 void __iomem *ioregs,
225 bool need_post)
226{
227 struct drm_device *dev;
228 struct ast_device *ast;
229 int ret;
230
231 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_device, base);
232 if (IS_ERR(ptr: ast))
233 return ERR_CAST(ptr: ast);
234 dev = &ast->base;
235
236 ast_device_init(ast, chip, config_mode, regs, ioregs, quirks: &ast_2000_device_quirks);
237
238 ast->dclk_table = ast_2000_dclk_table;
239
240 ast_2000_detect_tx_chip(ast, need_post);
241
242 if (need_post) {
243 ret = ast_post_gpu(ast);
244 if (ret)
245 return ERR_PTR(error: ret);
246 }
247
248 ret = ast_mm_init(ast);
249 if (ret)
250 return ERR_PTR(error: ret);
251
252 ret = ast_mode_config_init(ast);
253 if (ret)
254 return ERR_PTR(error: ret);
255
256 return dev;
257}
258

source code of linux/drivers/gpu/drm/ast/ast_2000.c