1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24#include "ras.h"
25#include "ras_mp1.h"
26#include "ras_core_status.h"
27#include "ras_mp1_v13_0.h"
28
29#define RAS_MP1_MSG_QueryValidMcaCount 0x36
30#define RAS_MP1_MSG_McaBankDumpDW 0x37
31#define RAS_MP1_MSG_ClearMcaOnRead 0x39
32#define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A
33#define RAS_MP1_MSG_McaBankCeDumpDW 0x3B
34
35#define MAX_UE_BANKS_PER_QUERY 12
36#define MAX_CE_BANKS_PER_QUERY 12
37
38static int mp1_v13_0_get_bank_count(struct ras_core_context *ras_core,
39 enum ras_err_type type, u32 *count)
40{
41 struct ras_mp1 *mp1 = &ras_core->ras_mp1;
42 const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
43 uint32_t bank_count = 0;
44 u32 msg;
45 int ret;
46
47 if (!count)
48 return -EINVAL;
49
50 if (!sys_func || !sys_func->mp1_get_valid_bank_count)
51 return -RAS_CORE_NOT_SUPPORTED;
52
53 switch (type) {
54 case RAS_ERR_TYPE__UE:
55 msg = RAS_MP1_MSG_QueryValidMcaCount;
56 break;
57 case RAS_ERR_TYPE__CE:
58 case RAS_ERR_TYPE__DE:
59 msg = RAS_MP1_MSG_QueryValidMcaCeCount;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 ret = sys_func->mp1_get_valid_bank_count(ras_core, msg, &bank_count);
66 if (!ret) {
67 if (((type == RAS_ERR_TYPE__UE) && (bank_count >= MAX_UE_BANKS_PER_QUERY)) ||
68 ((type == RAS_ERR_TYPE__CE) && (bank_count >= MAX_CE_BANKS_PER_QUERY)))
69 return -EINVAL;
70
71 *count = bank_count;
72 }
73
74 return ret;
75}
76
77static int mp1_v13_0_dump_bank(struct ras_core_context *ras_core,
78 enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val)
79{
80 struct ras_mp1 *mp1 = &ras_core->ras_mp1;
81 const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
82 u32 msg;
83
84 if (!sys_func || !sys_func->mp1_dump_valid_bank)
85 return -RAS_CORE_NOT_SUPPORTED;
86
87 switch (type) {
88 case RAS_ERR_TYPE__UE:
89 msg = RAS_MP1_MSG_McaBankDumpDW;
90 break;
91 case RAS_ERR_TYPE__CE:
92 case RAS_ERR_TYPE__DE:
93 msg = RAS_MP1_MSG_McaBankCeDumpDW;
94 break;
95 default:
96 return -EINVAL;
97 }
98
99 return sys_func->mp1_dump_valid_bank(ras_core, msg, idx, reg_idx, val);
100}
101
102const struct ras_mp1_ip_func mp1_ras_func_v13_0 = {
103 .get_valid_bank_count = mp1_v13_0_get_bank_count,
104 .dump_valid_bank = mp1_v13_0_dump_bank,
105};
106

source code of linux/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c