1// SPDX-License-Identifier: MIT
2/*
3 * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_atomfirmware.h"
26#include "amdgpu_ras_eeprom.h"
27#include "amdgpu_ras_mgr.h"
28#include "amdgpu_ras_eeprom_i2c.h"
29#include "ras_eeprom.h"
30
31/* These are memory addresses as would be seen by one or more EEPROM
32 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
33 * set of EEPROM devices. They form a continuous memory space.
34 *
35 * The I2C device address includes the device type identifier, 1010b,
36 * which is a reserved value and indicates that this is an I2C EEPROM
37 * device. It also includes the top 3 bits of the 19 bit EEPROM memory
38 * address, namely bits 18, 17, and 16. This makes up the 7 bit
39 * address sent on the I2C bus with bit 0 being the direction bit,
40 * which is not represented here, and sent by the hardware directly.
41 *
42 * For instance,
43 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
44 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
45 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
46 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
47 * address memory in a device or a device on the I2C bus, depending on
48 * the status of pins 1-3. See top of amdgpu_eeprom.c.
49 *
50 * The RAS table lives either at address 0 or address 40000h of EEPROM.
51 */
52#define EEPROM_I2C_MADDR_0 0x0
53#define EEPROM_I2C_MADDR_4 0x40000
54
55#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF))
56#define to_amdgpu_ras(x) (container_of(x, struct amdgpu_ras, eeprom_control))
57
58#define EEPROM_PAGE_BITS 8
59#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)
60#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
61
62#define EEPROM_OFFSET_SIZE 2
63
64static int ras_eeprom_i2c_config(struct ras_core_context *ras_core)
65{
66 struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
67 struct ras_eeprom_control *control = &ras_core->ras_eeprom;
68 u8 i2c_addr;
69
70 if (amdgpu_atomfirmware_ras_rom_addr(adev, i2c_address: &i2c_addr)) {
71 /* The address given by VBIOS is an 8-bit, wire-format
72 * address, i.e. the most significant byte.
73 *
74 * Normalize it to a 19-bit EEPROM address. Remove the
75 * device type identifier and make it a 7-bit address;
76 * then make it a 19-bit EEPROM address. See top of
77 * amdgpu_eeprom.c.
78 */
79 i2c_addr = (i2c_addr & 0x0F) >> 1;
80 control->i2c_address = ((u32) i2c_addr) << 16;
81 return 0;
82 }
83
84 switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) {
85 case IP_VERSION(13, 0, 5):
86 case IP_VERSION(13, 0, 6):
87 case IP_VERSION(13, 0, 10):
88 case IP_VERSION(13, 0, 12):
89 case IP_VERSION(13, 0, 14):
90 control->i2c_address = EEPROM_I2C_MADDR_4;
91 return 0;
92 default:
93 return -ENODATA;
94 }
95 return -ENODATA;
96}
97
98static int ras_eeprom_i2c_xfer(struct ras_core_context *ras_core, u32 eeprom_addr,
99 u8 *eeprom_buf, u32 buf_size, bool read)
100{
101 struct i2c_adapter *i2c_adap = ras_core->ras_eeprom.i2c_adapter;
102 u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
103 struct i2c_msg msgs[] = {
104 {
105 .flags = 0,
106 .len = EEPROM_OFFSET_SIZE,
107 .buf = eeprom_offset_buf,
108 },
109 {
110 .flags = read ? I2C_M_RD : 0,
111 },
112 };
113 const u8 *p = eeprom_buf;
114 int r;
115 u16 len;
116
117 for (r = 0; buf_size > 0;
118 buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
119 /* Set the EEPROM address we want to write to/read from.
120 */
121 msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr);
122 msgs[1].addr = msgs[0].addr;
123 msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;
124 msgs[0].buf[1] = eeprom_addr & 0xff;
125
126 if (!read) {
127 /* Write the maximum amount of data, without
128 * crossing the device's page boundary, as per
129 * its spec. Partial page writes are allowed,
130 * starting at any location within the page,
131 * so long as the page boundary isn't crossed
132 * over (actually the page pointer rolls
133 * over).
134 *
135 * As per the AT24CM02 EEPROM spec, after
136 * writing into a page, the I2C driver should
137 * terminate the transfer, i.e. in
138 * "i2c_transfer()" below, with a STOP
139 * condition, so that the self-timed write
140 * cycle begins. This is implied for the
141 * "i2c_transfer()" abstraction.
142 */
143 len = min(EEPROM_PAGE_SIZE - (eeprom_addr & EEPROM_PAGE_MASK),
144 buf_size);
145 } else {
146 /* Reading from the EEPROM has no limitation
147 * on the number of bytes read from the EEPROM
148 * device--they are simply sequenced out.
149 * Keep in mind that i2c_msg.len is u16 type.
150 */
151 len = min(U16_MAX, buf_size);
152 }
153 msgs[1].len = len;
154 msgs[1].buf = eeprom_buf;
155
156
157 /* This constitutes a START-STOP transaction.
158 */
159 r = i2c_transfer(adap: i2c_adap, msgs, ARRAY_SIZE(msgs));
160 if (r != ARRAY_SIZE(msgs))
161 break;
162
163 if (!read) {
164 /* According to EEPROM specs the length of the
165 * self-writing cycle, tWR (tW), is 10 ms.
166 *
167 * TODO: Use polling on ACK, aka Acknowledge
168 * Polling, to minimize waiting for the
169 * internal write cycle to complete, as it is
170 * usually smaller than tWR (tW).
171 */
172 msleep(msecs: 10);
173 }
174 }
175
176 return r < 0 ? r : eeprom_buf - p;
177}
178
179const struct ras_eeprom_sys_func amdgpu_ras_eeprom_i2c_sys_func = {
180 .eeprom_i2c_xfer = ras_eeprom_i2c_xfer,
181 .update_eeprom_i2c_config = ras_eeprom_i2c_config,
182};
183

source code of linux/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c