| 1 | /* SPDX-License-Identifier: MIT */ |
|---|
| 2 | /* |
|---|
| 3 | * Copyright 2025 Advanced Micro Devices, Inc. |
|---|
| 4 | * |
|---|
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
|---|
| 6 | * copy of this software and associated documentation files (the "Software"), |
|---|
| 7 | * to deal in the Software without restriction, including without limitation |
|---|
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|---|
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
|---|
| 10 | * Software is furnished to do so, subject to the following conditions: |
|---|
| 11 | * |
|---|
| 12 | * The above copyright notice and this permission notice shall be included in |
|---|
| 13 | * all copies or substantial portions of the Software. |
|---|
| 14 | * |
|---|
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|---|
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|---|
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|---|
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
|---|
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
|---|
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
|---|
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
|---|
| 22 | */ |
|---|
| 23 | |
|---|
| 24 | #ifndef __AMDGPU_RAS_CMD_H__ |
|---|
| 25 | #define __AMDGPU_RAS_CMD_H__ |
|---|
| 26 | #include "ras.h" |
|---|
| 27 | |
|---|
| 28 | enum amdgpu_ras_cmd_id { |
|---|
| 29 | RAS_CMD__AMDGPU_BEGIN = RAS_CMD_ID_AMDGPU_START, |
|---|
| 30 | RAS_CMD__TRANSLATE_MEMORY_FD, |
|---|
| 31 | RAS_CMD__AMDGPU_SUPPORTED_MAX = RAS_CMD_ID_AMDGPU_END, |
|---|
| 32 | }; |
|---|
| 33 | |
|---|
| 34 | struct ras_cmd_translate_memory_fd_req { |
|---|
| 35 | struct ras_cmd_dev_handle dev; |
|---|
| 36 | uint32_t type; |
|---|
| 37 | uint32_t fd; |
|---|
| 38 | uint64_t address; |
|---|
| 39 | uint32_t reserved[4]; |
|---|
| 40 | }; |
|---|
| 41 | |
|---|
| 42 | struct ras_cmd_translate_memory_fd_rsp { |
|---|
| 43 | uint32_t version; |
|---|
| 44 | uint32_t padding; |
|---|
| 45 | uint64_t start; |
|---|
| 46 | uint64_t size; |
|---|
| 47 | uint32_t reserved[2]; |
|---|
| 48 | }; |
|---|
| 49 | |
|---|
| 50 | int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, |
|---|
| 51 | struct ras_cmd_ctx *cmd, void *data); |
|---|
| 52 | int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd); |
|---|
| 53 | |
|---|
| 54 | #endif |
|---|
| 55 | |
|---|
