| 1 | /* |
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| 2 | * Copyright 2019 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef SMU_12_0_PPSMC_H |
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| 25 | #define SMU_12_0_PPSMC_H |
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| 26 | |
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| 27 | // SMU Response Codes: |
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| 28 | #define PPSMC_Result_OK 0x1 |
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| 29 | #define PPSMC_Result_Failed 0xFF |
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| 30 | #define PPSMC_Result_UnknownCmd 0xFE |
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| 31 | #define PPSMC_Result_CmdRejectedPrereq 0xFD |
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| 32 | #define PPSMC_Result_CmdRejectedBusy 0xFC |
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| 33 | |
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| 34 | |
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| 35 | // Message Definitions: |
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| 36 | #define PPSMC_MSG_TestMessage 0x1 |
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| 37 | #define PPSMC_MSG_GetSmuVersion 0x2 |
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| 38 | #define PPSMC_MSG_GetDriverIfVersion 0x3 |
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| 39 | #define PPSMC_MSG_PowerUpGfx 0x6 |
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| 40 | #define PPSMC_MSG_EnableGfxOff 0x7 |
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| 41 | #define PPSMC_MSG_DisableGfxOff 0x8 |
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| 42 | #define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default |
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| 43 | #define PPSMC_MSG_PowerUpIspByTile 0xA |
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| 44 | #define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default |
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| 45 | #define PPSMC_MSG_PowerUpVcn 0xC |
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| 46 | #define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default |
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| 47 | #define PPSMC_MSG_PowerUpSdma 0xE |
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| 48 | #define PPSMC_MSG_SetHardMinIspclkByFreq 0xF |
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| 49 | #define PPSMC_MSG_SetHardMinVcn 0x10 // For wireless display |
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| 50 | #define PPSMC_MSG_spare1 0x11 |
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| 51 | #define PPSMC_MSG_spare2 0x12 |
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| 52 | #define PPSMC_MSG_SetAllowFclkSwitch 0x13 |
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| 53 | #define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14 |
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| 54 | #define PPSMC_MSG_ActiveProcessNotify 0x15 |
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| 55 | #define PPSMC_MSG_SetCustomPolicy 0x16 |
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| 56 | #define PPSMC_MSG_SetVideoFps 0x17 |
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| 57 | #define PPSMC_MSG_SetDisplayCount 0x18 // Moved to VBIOS |
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| 58 | #define PPSMC_MSG_QueryPowerLimit 0x19 //Driver to look up sustainable clocks for VQ |
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| 59 | #define PPSMC_MSG_SetDriverDramAddrHigh 0x1A |
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| 60 | #define PPSMC_MSG_SetDriverDramAddrLow 0x1B |
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| 61 | #define PPSMC_MSG_TransferTableSmu2Dram 0x1C |
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| 62 | #define PPSMC_MSG_TransferTableDram2Smu 0x1D |
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| 63 | #define PPSMC_MSG_GfxDeviceDriverReset 0x1E |
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| 64 | #define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F |
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| 65 | #define PPSMC_MSG_SetHardMinDcfclkByFreq 0x20 // Moved to VBIOS |
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| 66 | #define PPSMC_MSG_SetHardMinSocclkByFreq 0x21 |
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| 67 | #define PPSMC_MSG_ControlIgpuATS 0x22 |
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| 68 | #define PPSMC_MSG_SetMinVideoFclkFreq 0x23 |
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| 69 | #define PPSMC_MSG_SetMinDeepSleepDcfclk 0x24 // Moved to VBIOS |
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| 70 | #define PPSMC_MSG_ForcePowerDownGfx 0x25 |
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| 71 | #define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26 // Moved to VBIOS |
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| 72 | #define PPSMC_MSG_SetDppclkVoltageByFreq 0x27 // Moved to VBIOS and is SetDppclkFreq |
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| 73 | #define PPSMC_MSG_SetSoftMinVcn 0x28 |
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| 74 | #define PPSMC_MSG_EnablePostCode 0x29 |
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| 75 | #define PPSMC_MSG_GetGfxclkFrequency 0x2A |
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| 76 | #define PPSMC_MSG_GetFclkFrequency 0x2B |
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| 77 | #define PPSMC_MSG_GetMinGfxclkFrequency 0x2C |
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| 78 | #define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D |
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| 79 | #define PPSMC_MSG_SoftReset 0x2E // Not supported |
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| 80 | #define PPSMC_MSG_SetGfxCGPG 0x2F |
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| 81 | #define PPSMC_MSG_SetSoftMaxGfxClk 0x30 |
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| 82 | #define PPSMC_MSG_SetHardMinGfxClk 0x31 |
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| 83 | #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32 |
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| 84 | #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33 |
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| 85 | #define PPSMC_MSG_SetSoftMaxVcn 0x34 |
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| 86 | #define PPSMC_MSG_PowerGateMmHub 0x35 |
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| 87 | #define PPSMC_MSG_UpdatePmeRestore 0x36 // Moved to VBIOS |
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| 88 | #define PPSMC_MSG_GpuChangeState 0x37 |
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| 89 | #define PPSMC_MSG_SetPowerLimitPercentage 0x38 |
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| 90 | #define PPSMC_MSG_ForceGfxContentSave 0x39 |
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| 91 | #define PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x3A // Moved to VBIOS |
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| 92 | #define PPSMC_MSG_PowerDownJpeg 0x3B |
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| 93 | #define PPSMC_MSG_PowerUpJpeg 0x3C |
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| 94 | #define PPSMC_MSG_PowerGateAtHub 0x3D |
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| 95 | #define PPSMC_MSG_SetSoftMinJpeg 0x3E |
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| 96 | #define PPSMC_MSG_SetHardMinFclkByFreq 0x3F |
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| 97 | #define PPSMC_Message_Count 0x40 |
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| 98 | |
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| 99 | |
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| 100 | //Argument for PPSMC_MSG_GpuChangeState |
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| 101 | enum { |
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| 102 | eGpuChangeState_D0Entry = 1, |
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| 103 | eGpuChangeState_D3Entry, |
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| 104 | }; |
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| 105 | |
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| 106 | #endif |
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| 107 | |
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