1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __AMDGPU_SMU_H__
23#define __AMDGPU_SMU_H__
24
25#include <linux/acpi_amd_wbrf.h>
26#include <linux/units.h>
27
28#include "amdgpu.h"
29#include "kgd_pp_interface.h"
30#include "dm_pp_interface.h"
31#include "dm_pp_smu.h"
32#include "smu_types.h"
33#include "linux/firmware.h"
34
35#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
36#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
37#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
38#define SMU_FW_NAME_LEN 0x24
39
40#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
41#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1)
42#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2)
43
44// Power Throttlers
45#define SMU_THROTTLER_PPT0_BIT 0
46#define SMU_THROTTLER_PPT1_BIT 1
47#define SMU_THROTTLER_PPT2_BIT 2
48#define SMU_THROTTLER_PPT3_BIT 3
49#define SMU_THROTTLER_SPL_BIT 4
50#define SMU_THROTTLER_FPPT_BIT 5
51#define SMU_THROTTLER_SPPT_BIT 6
52#define SMU_THROTTLER_SPPT_APU_BIT 7
53
54// Current Throttlers
55#define SMU_THROTTLER_TDC_GFX_BIT 16
56#define SMU_THROTTLER_TDC_SOC_BIT 17
57#define SMU_THROTTLER_TDC_MEM_BIT 18
58#define SMU_THROTTLER_TDC_VDD_BIT 19
59#define SMU_THROTTLER_TDC_CVIP_BIT 20
60#define SMU_THROTTLER_EDC_CPU_BIT 21
61#define SMU_THROTTLER_EDC_GFX_BIT 22
62#define SMU_THROTTLER_APCC_BIT 23
63
64// Temperature
65#define SMU_THROTTLER_TEMP_GPU_BIT 32
66#define SMU_THROTTLER_TEMP_CORE_BIT 33
67#define SMU_THROTTLER_TEMP_MEM_BIT 34
68#define SMU_THROTTLER_TEMP_EDGE_BIT 35
69#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
70#define SMU_THROTTLER_TEMP_SOC_BIT 37
71#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
72#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
73#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
74#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
75#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
76#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
77#define SMU_THROTTLER_VRHOT0_BIT 44
78#define SMU_THROTTLER_VRHOT1_BIT 45
79#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
80#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
81
82// Other
83#define SMU_THROTTLER_PPM_BIT 56
84#define SMU_THROTTLER_FIT_BIT 57
85
86struct smu_hw_power_state {
87 unsigned int magic;
88};
89
90struct smu_power_state;
91
92enum smu_state_ui_label {
93 SMU_STATE_UI_LABEL_NONE,
94 SMU_STATE_UI_LABEL_BATTERY,
95 SMU_STATE_UI_TABEL_MIDDLE_LOW,
96 SMU_STATE_UI_LABEL_BALLANCED,
97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
98 SMU_STATE_UI_LABEL_PERFORMANCE,
99 SMU_STATE_UI_LABEL_BACO,
100};
101
102enum smu_state_classification_flag {
103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
124};
125
126struct smu_state_classification_block {
127 enum smu_state_ui_label ui_label;
128 enum smu_state_classification_flag flags;
129 int bios_index;
130 bool temporary_state;
131 bool to_be_deleted;
132};
133
134struct smu_state_pcie_block {
135 unsigned int lanes;
136};
137
138enum smu_refreshrate_source {
139 SMU_REFRESHRATE_SOURCE_EDID,
140 SMU_REFRESHRATE_SOURCE_EXPLICIT
141};
142
143struct smu_state_display_block {
144 bool disable_frame_modulation;
145 bool limit_refreshrate;
146 enum smu_refreshrate_source refreshrate_source;
147 int explicit_refreshrate;
148 int edid_refreshrate_index;
149 bool enable_vari_bright;
150};
151
152struct smu_state_memory_block {
153 bool dll_off;
154 uint8_t m3arb;
155 uint8_t unused[3];
156};
157
158struct smu_state_software_algorithm_block {
159 bool disable_load_balancing;
160 bool enable_sleep_for_timestamps;
161};
162
163struct smu_temperature_range {
164 int min;
165 int max;
166 int edge_emergency_max;
167 int hotspot_min;
168 int hotspot_crit_max;
169 int hotspot_emergency_max;
170 int mem_min;
171 int mem_crit_max;
172 int mem_emergency_max;
173 int software_shutdown_temp;
174 int software_shutdown_temp_offset;
175};
176
177struct smu_state_validation_block {
178 bool single_display_only;
179 bool disallow_on_dc;
180 uint8_t supported_power_levels;
181};
182
183struct smu_uvd_clocks {
184 uint32_t vclk;
185 uint32_t dclk;
186};
187
188/**
189* Structure to hold a SMU Power State.
190*/
191struct smu_power_state {
192 uint32_t id;
193 struct list_head ordered_list;
194 struct list_head all_states_list;
195
196 struct smu_state_classification_block classification;
197 struct smu_state_validation_block validation;
198 struct smu_state_pcie_block pcie;
199 struct smu_state_display_block display;
200 struct smu_state_memory_block memory;
201 struct smu_state_software_algorithm_block software;
202 struct smu_uvd_clocks uvd_clocks;
203 struct smu_hw_power_state hardware;
204};
205
206enum smu_power_src_type {
207 SMU_POWER_SOURCE_AC,
208 SMU_POWER_SOURCE_DC,
209 SMU_POWER_SOURCE_COUNT,
210};
211
212enum smu_ppt_limit_type {
213 SMU_DEFAULT_PPT_LIMIT = 0,
214 SMU_FAST_PPT_LIMIT,
215 SMU_LIMIT_TYPE_COUNT,
216};
217
218enum smu_ppt_limit_level {
219 SMU_PPT_LIMIT_MIN = -1,
220 SMU_PPT_LIMIT_CURRENT,
221 SMU_PPT_LIMIT_DEFAULT,
222 SMU_PPT_LIMIT_MAX,
223};
224
225enum smu_memory_pool_size {
226 SMU_MEMORY_POOL_SIZE_ZERO = 0,
227 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
228 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
229 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
230 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
231};
232
233struct smu_user_dpm_profile {
234 uint32_t fan_mode;
235 uint32_t power_limits[SMU_LIMIT_TYPE_COUNT];
236 uint32_t fan_speed_pwm;
237 uint32_t fan_speed_rpm;
238 uint32_t flags;
239 uint32_t user_od;
240
241 /* user clock state information */
242 uint32_t clk_mask[SMU_CLK_COUNT];
243 uint32_t clk_dependency;
244};
245
246#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
247 do { \
248 tables[table_id].size = s; \
249 tables[table_id].align = a; \
250 tables[table_id].domain = d; \
251 } while (0)
252
253struct smu_table_cache {
254 void *buffer;
255 size_t size;
256 /* interval in ms*/
257 uint32_t interval;
258 unsigned long last_cache_time;
259};
260
261struct smu_table {
262 uint64_t size;
263 uint32_t align;
264 uint8_t domain;
265 uint64_t mc_address;
266 void *cpu_addr;
267 struct amdgpu_bo *bo;
268 uint32_t version;
269 struct smu_table_cache cache;
270};
271
272enum smu_perf_level_designation {
273 PERF_LEVEL_ACTIVITY,
274 PERF_LEVEL_POWER_CONTAINMENT,
275};
276
277struct smu_performance_level {
278 uint32_t core_clock;
279 uint32_t memory_clock;
280 uint32_t vddc;
281 uint32_t vddci;
282 uint32_t non_local_mem_freq;
283 uint32_t non_local_mem_width;
284};
285
286struct smu_clock_info {
287 uint32_t min_mem_clk;
288 uint32_t max_mem_clk;
289 uint32_t min_eng_clk;
290 uint32_t max_eng_clk;
291 uint32_t min_bus_bandwidth;
292 uint32_t max_bus_bandwidth;
293};
294
295struct smu_bios_boot_up_values {
296 uint32_t revision;
297 uint32_t gfxclk;
298 uint32_t uclk;
299 uint32_t socclk;
300 uint32_t dcefclk;
301 uint32_t eclk;
302 uint32_t vclk;
303 uint32_t dclk;
304 uint16_t vddc;
305 uint16_t vddci;
306 uint16_t mvddc;
307 uint16_t vdd_gfx;
308 uint8_t cooling_id;
309 uint32_t pp_table_id;
310 uint32_t format_revision;
311 uint32_t content_revision;
312 uint32_t fclk;
313 uint32_t lclk;
314 uint32_t firmware_caps;
315};
316
317enum smu_table_id {
318 SMU_TABLE_PPTABLE = 0,
319 SMU_TABLE_WATERMARKS,
320 SMU_TABLE_CUSTOM_DPM,
321 SMU_TABLE_DPMCLOCKS,
322 SMU_TABLE_AVFS,
323 SMU_TABLE_AVFS_PSM_DEBUG,
324 SMU_TABLE_AVFS_FUSE_OVERRIDE,
325 SMU_TABLE_PMSTATUSLOG,
326 SMU_TABLE_SMU_METRICS,
327 SMU_TABLE_DRIVER_SMU_CONFIG,
328 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
329 SMU_TABLE_OVERDRIVE,
330 SMU_TABLE_I2C_COMMANDS,
331 SMU_TABLE_PACE,
332 SMU_TABLE_ECCINFO,
333 SMU_TABLE_COMBO_PPTABLE,
334 SMU_TABLE_WIFIBAND,
335 SMU_TABLE_GPUBOARD_TEMP_METRICS,
336 SMU_TABLE_BASEBOARD_TEMP_METRICS,
337 SMU_TABLE_PMFW_SYSTEM_METRICS,
338 SMU_TABLE_COUNT,
339};
340
341struct smu_table_context {
342 void *power_play_table;
343 uint32_t power_play_table_size;
344 void *hardcode_pptable;
345 unsigned long metrics_time;
346 void *metrics_table;
347 void *clocks_table;
348 void *watermarks_table;
349
350 void *max_sustainable_clocks;
351 struct smu_bios_boot_up_values boot_values;
352 void *driver_pptable;
353 void *combo_pptable;
354 void *ecc_table;
355 void *driver_smu_config_table;
356 struct smu_table tables[SMU_TABLE_COUNT];
357 /*
358 * The driver table is just a staging buffer for
359 * uploading/downloading content from the SMU.
360 *
361 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
362 * SMU_MSG_TransferTableDram2Smu instructs SMU
363 * which content driver is interested.
364 */
365 struct smu_table driver_table;
366 struct smu_table memory_pool;
367 struct smu_table dummy_read_1_table;
368 uint8_t thermal_controller_type;
369
370 void *overdrive_table;
371 void *boot_overdrive_table;
372 void *user_overdrive_table;
373
374 uint32_t gpu_metrics_table_size;
375 void *gpu_metrics_table;
376};
377
378struct smu_context;
379struct smu_dpm_policy;
380
381struct smu_dpm_policy_desc {
382 const char *name;
383 char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level);
384};
385
386struct smu_dpm_policy {
387 struct smu_dpm_policy_desc *desc;
388 enum pp_pm_policy policy_type;
389 unsigned long level_mask;
390 int current_level;
391 int (*set_policy)(struct smu_context *ctxt, int level);
392};
393
394struct smu_dpm_policy_ctxt {
395 struct smu_dpm_policy policies[PP_PM_POLICY_NUM];
396 unsigned long policy_mask;
397};
398
399struct smu_dpm_context {
400 uint32_t dpm_context_size;
401 void *dpm_context;
402 void *golden_dpm_context;
403 enum amd_dpm_forced_level dpm_level;
404 enum amd_dpm_forced_level saved_dpm_level;
405 enum amd_dpm_forced_level requested_dpm_level;
406 struct smu_power_state *dpm_request_power_state;
407 struct smu_power_state *dpm_current_power_state;
408 struct mclock_latency_table *mclk_latency_table;
409 struct smu_dpm_policy_ctxt *dpm_policies;
410};
411
412struct smu_temp_context {
413 const struct smu_temp_funcs *temp_funcs;
414};
415
416struct smu_power_gate {
417 bool uvd_gated;
418 bool vce_gated;
419 atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
420 atomic_t jpeg_gated;
421 atomic_t vpe_gated;
422 atomic_t isp_gated;
423 atomic_t umsch_mm_gated;
424};
425
426struct smu_power_context {
427 void *power_context;
428 uint32_t power_context_size;
429 struct smu_power_gate power_gate;
430};
431
432#define SMU_FEATURE_MAX (64)
433struct smu_feature {
434 uint32_t feature_num;
435 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
436 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
437};
438
439struct smu_clocks {
440 uint32_t engine_clock;
441 uint32_t memory_clock;
442 uint32_t bus_bandwidth;
443 uint32_t engine_clock_in_sr;
444 uint32_t dcef_clock;
445 uint32_t dcef_clock_in_sr;
446};
447
448#define MAX_REGULAR_DPM_NUM 16
449struct mclk_latency_entries {
450 uint32_t frequency;
451 uint32_t latency;
452};
453struct mclock_latency_table {
454 uint32_t count;
455 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
456};
457
458enum smu_reset_mode {
459 SMU_RESET_MODE_0,
460 SMU_RESET_MODE_1,
461 SMU_RESET_MODE_2,
462 SMU_RESET_MODE_3,
463 SMU_RESET_MODE_4,
464};
465
466enum smu_baco_state {
467 SMU_BACO_STATE_ENTER = 0,
468 SMU_BACO_STATE_EXIT,
469 SMU_BACO_STATE_NONE,
470};
471
472struct smu_baco_context {
473 uint32_t state;
474 bool platform_support;
475 bool maco_support;
476};
477
478struct smu_freq_info {
479 uint32_t min;
480 uint32_t max;
481 uint32_t freq_level;
482};
483
484struct pstates_clk_freq {
485 uint32_t min;
486 uint32_t standard;
487 uint32_t peak;
488 struct smu_freq_info custom;
489 struct smu_freq_info curr;
490};
491
492struct smu_umd_pstate_table {
493 struct pstates_clk_freq gfxclk_pstate;
494 struct pstates_clk_freq socclk_pstate;
495 struct pstates_clk_freq uclk_pstate;
496 struct pstates_clk_freq vclk_pstate;
497 struct pstates_clk_freq dclk_pstate;
498 struct pstates_clk_freq fclk_pstate;
499};
500
501struct cmn2asic_msg_mapping {
502 int valid_mapping;
503 int map_to;
504 uint32_t flags;
505};
506
507struct cmn2asic_mapping {
508 int valid_mapping;
509 int map_to;
510};
511
512struct stb_context {
513 uint32_t stb_buf_size;
514 bool enabled;
515 spinlock_t lock;
516};
517
518enum smu_fw_status {
519 SMU_FW_INIT = 0,
520 SMU_FW_RUNTIME,
521 SMU_FW_HANG,
522};
523
524#define WORKLOAD_POLICY_MAX 7
525
526/*
527 * Configure wbrf event handling pace as there can be only one
528 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms.
529 */
530#define SMU_WBRF_EVENT_HANDLING_PACE 10
531
532enum smu_feature_cap_id {
533 SMU_FEATURE_CAP_ID__LINK_RESET = 0,
534 SMU_FEATURE_CAP_ID__SDMA_RESET,
535 SMU_FEATURE_CAP_ID__VCN_RESET,
536 SMU_FEATURE_CAP_ID__COUNT,
537};
538
539struct smu_feature_cap {
540 DECLARE_BITMAP(cap_map, SMU_FEATURE_CAP_ID__COUNT);
541};
542
543struct smu_context {
544 struct amdgpu_device *adev;
545 struct amdgpu_irq_src irq_source;
546
547 const struct pptable_funcs *ppt_funcs;
548 const struct cmn2asic_msg_mapping *message_map;
549 const struct cmn2asic_mapping *clock_map;
550 const struct cmn2asic_mapping *feature_map;
551 const struct cmn2asic_mapping *table_map;
552 const struct cmn2asic_mapping *pwr_src_map;
553 const struct cmn2asic_mapping *workload_map;
554 struct mutex message_lock;
555 uint64_t pool_size;
556
557 struct smu_table_context smu_table;
558 struct smu_dpm_context smu_dpm;
559 struct smu_power_context smu_power;
560 struct smu_temp_context smu_temp;
561 struct smu_feature smu_feature;
562 struct amd_pp_display_configuration *display_config;
563 struct smu_baco_context smu_baco;
564 struct smu_temperature_range thermal_range;
565 struct smu_feature_cap fea_cap;
566 void *od_settings;
567
568 struct smu_umd_pstate_table pstate_table;
569 uint32_t pstate_sclk;
570 uint32_t pstate_mclk;
571
572 bool od_enabled;
573 uint32_t current_power_limit;
574 uint32_t default_power_limit;
575 uint32_t max_power_limit;
576 uint32_t min_power_limit;
577
578 /* soft pptable */
579 uint32_t ppt_offset_bytes;
580 uint32_t ppt_size_bytes;
581 uint8_t *ppt_start_addr;
582
583 bool support_power_containment;
584 bool disable_watermark;
585
586#define WATERMARKS_EXIST (1 << 0)
587#define WATERMARKS_LOADED (1 << 1)
588 uint32_t watermarks_bitmap;
589 uint32_t hard_min_uclk_req_from_dal;
590 bool disable_uclk_switch;
591
592 /* asic agnostic workload mask */
593 uint32_t workload_mask;
594 bool pause_workload;
595 /* default/user workload preference */
596 uint32_t power_profile_mode;
597 uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT];
598 /* backend specific custom workload settings */
599 long *custom_profile_params;
600 bool pm_enabled;
601 bool is_apu;
602
603 uint32_t smc_driver_if_version;
604 uint32_t smc_fw_if_version;
605 uint32_t smc_fw_version;
606 uint32_t smc_fw_caps;
607 uint8_t smc_fw_state;
608
609 bool uploading_custom_pp_table;
610 bool dc_controlled_by_gpio;
611
612 struct work_struct throttling_logging_work;
613 atomic64_t throttle_int_counter;
614 struct work_struct interrupt_work;
615
616 unsigned fan_max_rpm;
617 unsigned manual_fan_speed_pwm;
618
619 uint32_t gfx_default_hard_min_freq;
620 uint32_t gfx_default_soft_max_freq;
621 uint32_t gfx_actual_hard_min_freq;
622 uint32_t gfx_actual_soft_max_freq;
623
624 /* APU only */
625 uint32_t cpu_default_soft_min_freq;
626 uint32_t cpu_default_soft_max_freq;
627 uint32_t cpu_actual_soft_min_freq;
628 uint32_t cpu_actual_soft_max_freq;
629 uint32_t cpu_core_id_select;
630 uint16_t cpu_core_num;
631
632 struct smu_user_dpm_profile user_dpm_profile;
633
634 struct stb_context stb_context;
635
636 struct firmware pptable_firmware;
637
638 u32 param_reg;
639 u32 msg_reg;
640 u32 resp_reg;
641
642 u32 debug_param_reg;
643 u32 debug_msg_reg;
644 u32 debug_resp_reg;
645
646 struct delayed_work swctf_delayed_work;
647
648 /* data structures for wbrf feature support */
649 bool wbrf_supported;
650 struct notifier_block wbrf_notifier;
651 struct delayed_work wbrf_delayed_work;
652};
653
654struct i2c_adapter;
655
656/**
657 * struct smu_temp_funcs - Callbacks used to get temperature data.
658 */
659struct smu_temp_funcs {
660 /**
661 * @get_temp_metrics: Calibrate voltage/frequency curve to fit the system's
662 * power delivery and voltage margins. Required for adaptive
663 * @type Temperature metrics type(baseboard/gpuboard)
664 * Return: Size of &table
665 */
666 ssize_t (*get_temp_metrics)(struct smu_context *smu,
667 enum smu_temp_metric_type type, void *table);
668
669 /**
670 * @temp_metrics_is_support: Get if specific temperature metrics is supported
671 * @type Temperature metrics type(baseboard/gpuboard)
672 * Return: true if supported else false
673 */
674 bool (*temp_metrics_is_supported)(struct smu_context *smu, enum smu_temp_metric_type type);
675
676};
677
678/**
679 * struct pptable_funcs - Callbacks used to interact with the SMU.
680 */
681struct pptable_funcs {
682 /**
683 * @run_btc: Calibrate voltage/frequency curve to fit the system's
684 * power delivery and voltage margins. Required for adaptive
685 * voltage frequency scaling (AVFS).
686 */
687 int (*run_btc)(struct smu_context *smu);
688
689 /**
690 * @get_allowed_feature_mask: Get allowed feature mask.
691 * &feature_mask: Array to store feature mask.
692 * &num: Elements in &feature_mask.
693 */
694 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
695
696 /**
697 * @get_current_power_state: Get the current power state.
698 *
699 * Return: Current power state on success, negative errno on failure.
700 */
701 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
702
703 /**
704 * @set_default_dpm_table: Retrieve the default overdrive settings from
705 * the SMU.
706 */
707 int (*set_default_dpm_table)(struct smu_context *smu);
708
709 int (*set_power_state)(struct smu_context *smu);
710
711 /**
712 * @populate_umd_state_clk: Populate the UMD power state table with
713 * defaults.
714 */
715 int (*populate_umd_state_clk)(struct smu_context *smu);
716
717 /**
718 * @print_clk_levels: Print DPM clock levels for a clock domain
719 * to buffer. Star current level.
720 *
721 * Used for sysfs interfaces.
722 * Return: Number of characters written to the buffer
723 */
724 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
725
726 /**
727 * @emit_clk_levels: Print DPM clock levels for a clock domain
728 * to buffer using sysfs_emit_at. Star current level.
729 *
730 * Used for sysfs interfaces.
731 * &buf: sysfs buffer
732 * &offset: offset within buffer to start printing, which is updated by the
733 * function.
734 *
735 * Return: 0 on Success or Negative to indicate an error occurred.
736 */
737 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
738
739 /**
740 * @force_clk_levels: Set a range of allowed DPM levels for a clock
741 * domain.
742 * &clk_type: Clock domain.
743 * &mask: Range of allowed DPM levels.
744 */
745 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
746
747 /**
748 * @od_edit_dpm_table: Edit the custom overdrive DPM table.
749 * &type: Type of edit.
750 * &input: Edit parameters.
751 * &size: Size of &input.
752 */
753 int (*od_edit_dpm_table)(struct smu_context *smu,
754 enum PP_OD_DPM_TABLE_COMMAND type,
755 long *input, uint32_t size);
756
757 /**
758 * @restore_user_od_settings: Restore the user customized
759 * OD settings on S3/S4/Runpm resume.
760 */
761 int (*restore_user_od_settings)(struct smu_context *smu);
762
763 /**
764 * @get_clock_by_type_with_latency: Get the speed and latency of a clock
765 * domain.
766 */
767 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
768 enum smu_clk_type clk_type,
769 struct
770 pp_clock_levels_with_latency
771 *clocks);
772 /**
773 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
774 * domain.
775 */
776 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
777 enum amd_pp_clock_type type,
778 struct
779 pp_clock_levels_with_voltage
780 *clocks);
781
782 /**
783 * @get_power_profile_mode: Print all power profile modes to
784 * buffer. Star current mode.
785 */
786 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
787
788 /**
789 * @set_power_profile_mode: Set a power profile mode. Also used to
790 * create/set custom power profile modes.
791 * &input: Power profile mode parameters.
792 * &workload_mask: mask of workloads to enable
793 * &custom_params: custom profile parameters
794 * &custom_params_max_idx: max valid idx into custom_params
795 */
796 int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask,
797 long *custom_params, u32 custom_params_max_idx);
798
799 /**
800 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
801 * management.
802 */
803 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);
804
805 /**
806 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
807 * management.
808 */
809 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
810
811 /**
812 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
813 */
814 int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
815
816 /**
817 * @read_sensor: Read data from a sensor.
818 * &sensor: Sensor to read data from.
819 * &data: Sensor reading.
820 * &size: Size of &data.
821 */
822 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
823 void *data, uint32_t *size);
824
825 /**
826 * @get_apu_thermal_limit: get apu core limit from smu
827 * &limit: current limit temperature in millidegrees Celsius
828 */
829 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit);
830
831 /**
832 * @set_apu_thermal_limit: update all controllers with new limit
833 * &limit: limit temperature to be setted, in millidegrees Celsius
834 */
835 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit);
836
837 /**
838 * @pre_display_config_changed: Prepare GPU for a display configuration
839 * change.
840 *
841 * Disable display tracking and pin memory clock speed to maximum. Used
842 * in display component synchronization.
843 */
844 int (*pre_display_config_changed)(struct smu_context *smu);
845
846 /**
847 * @display_config_changed: Notify the SMU of the current display
848 * configuration.
849 *
850 * Allows SMU to properly track blanking periods for memory clock
851 * adjustment. Used in display component synchronization.
852 */
853 int (*display_config_changed)(struct smu_context *smu);
854
855 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
856
857 /**
858 * @notify_smc_display_config: Applies display requirements to the
859 * current power state.
860 *
861 * Optimize deep sleep DCEFclk and mclk for the current display
862 * configuration. Used in display component synchronization.
863 */
864 int (*notify_smc_display_config)(struct smu_context *smu);
865
866 /**
867 * @is_dpm_running: Check if DPM is running.
868 *
869 * Return: True if DPM is running, false otherwise.
870 */
871 bool (*is_dpm_running)(struct smu_context *smu);
872
873 /**
874 * @get_fan_speed_pwm: Get the current fan speed in PWM.
875 */
876 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
877
878 /**
879 * @get_fan_speed_rpm: Get the current fan speed in rpm.
880 */
881 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
882
883 /**
884 * @set_watermarks_table: Configure and upload the watermarks tables to
885 * the SMU.
886 */
887 int (*set_watermarks_table)(struct smu_context *smu,
888 struct pp_smu_wm_range_sets *clock_ranges);
889
890 /**
891 * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
892 */
893 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
894
895 /**
896 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
897 * &clocks_in_khz: Array of DPM levels.
898 * &num_states: Elements in &clocks_in_khz.
899 */
900 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
901
902 /**
903 * @set_default_od_settings: Set the overdrive tables to defaults.
904 */
905 int (*set_default_od_settings)(struct smu_context *smu);
906
907 /**
908 * @set_performance_level: Set a performance level.
909 */
910 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
911
912 /**
913 * @display_disable_memory_clock_switch: Enable/disable dynamic memory
914 * clock switching.
915 *
916 * Disabling this feature forces memory clock speed to maximum.
917 * Enabling sets the minimum memory clock capable of driving the
918 * current display configuration.
919 */
920 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
921
922 /**
923 * @get_power_limit: Get the device's power limits.
924 */
925 int (*get_power_limit)(struct smu_context *smu,
926 uint32_t *current_power_limit,
927 uint32_t *default_power_limit,
928 uint32_t *max_power_limit,
929 uint32_t *min_power_limit);
930
931 /**
932 * @get_ppt_limit: Get the device's ppt limits.
933 */
934 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
935 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
936
937 /**
938 * @set_df_cstate: Set data fabric cstate.
939 */
940 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
941
942 /**
943 * @update_pcie_parameters: Update and upload the system's PCIe
944 * capabilites to the SMU.
945 * &pcie_gen_cap: Maximum allowed PCIe generation.
946 * &pcie_width_cap: Maximum allowed PCIe width.
947 */
948 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);
949
950 /**
951 * @i2c_init: Initialize i2c.
952 *
953 * The i2c bus is used internally by the SMU voltage regulators and
954 * other devices. The i2c's EEPROM also stores bad page tables on boards
955 * with ECC.
956 */
957 int (*i2c_init)(struct smu_context *smu);
958
959 /**
960 * @i2c_fini: Tear down i2c.
961 */
962 void (*i2c_fini)(struct smu_context *smu);
963
964 /**
965 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
966 */
967 void (*get_unique_id)(struct smu_context *smu);
968
969 /**
970 * @get_dpm_clock_table: Get a copy of the DPM clock table.
971 *
972 * Used by display component in bandwidth and watermark calculations.
973 */
974 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
975
976 /**
977 * @init_microcode: Request the SMU's firmware from the kernel.
978 */
979 int (*init_microcode)(struct smu_context *smu);
980
981 /**
982 * @load_microcode: Load firmware onto the SMU.
983 */
984 int (*load_microcode)(struct smu_context *smu);
985
986 /**
987 * @fini_microcode: Release the SMU's firmware.
988 */
989 void (*fini_microcode)(struct smu_context *smu);
990
991 /**
992 * @init_smc_tables: Initialize the SMU tables.
993 */
994 int (*init_smc_tables)(struct smu_context *smu);
995
996 /**
997 * @fini_smc_tables: Release the SMU tables.
998 */
999 int (*fini_smc_tables)(struct smu_context *smu);
1000
1001 /**
1002 * @init_power: Initialize the power gate table context.
1003 */
1004 int (*init_power)(struct smu_context *smu);
1005
1006 /**
1007 * @fini_power: Release the power gate table context.
1008 */
1009 int (*fini_power)(struct smu_context *smu);
1010
1011 /**
1012 * @check_fw_status: Check the SMU's firmware status.
1013 *
1014 * Return: Zero if check passes, negative errno on failure.
1015 */
1016 int (*check_fw_status)(struct smu_context *smu);
1017
1018 /**
1019 * @set_mp1_state: put SMU into a correct state for comming
1020 * resume from runpm or gpu reset.
1021 */
1022 int (*set_mp1_state)(struct smu_context *smu,
1023 enum pp_mp1_state mp1_state);
1024
1025 /**
1026 * @setup_pptable: Initialize the power play table and populate it with
1027 * default values.
1028 */
1029 int (*setup_pptable)(struct smu_context *smu);
1030
1031 /**
1032 * @get_vbios_bootup_values: Get default boot values from the VBIOS.
1033 */
1034 int (*get_vbios_bootup_values)(struct smu_context *smu);
1035
1036 /**
1037 * @check_fw_version: Print driver and SMU interface versions to the
1038 * system log.
1039 *
1040 * Interface mismatch is not a critical failure.
1041 */
1042 int (*check_fw_version)(struct smu_context *smu);
1043
1044 /**
1045 * @powergate_sdma: Power up/down system direct memory access.
1046 */
1047 int (*powergate_sdma)(struct smu_context *smu, bool gate);
1048
1049 /**
1050 * @set_gfx_cgpg: Enable/disable graphics engine course grain power
1051 * gating.
1052 */
1053 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
1054
1055 /**
1056 * @write_pptable: Write the power play table to the SMU.
1057 */
1058 int (*write_pptable)(struct smu_context *smu);
1059
1060 /**
1061 * @set_driver_table_location: Send the location of the driver table to
1062 * the SMU.
1063 */
1064 int (*set_driver_table_location)(struct smu_context *smu);
1065
1066 /**
1067 * @set_tool_table_location: Send the location of the tool table to the
1068 * SMU.
1069 */
1070 int (*set_tool_table_location)(struct smu_context *smu);
1071
1072 /**
1073 * @notify_memory_pool_location: Send the location of the memory pool to
1074 * the SMU.
1075 */
1076 int (*notify_memory_pool_location)(struct smu_context *smu);
1077
1078 /**
1079 * @system_features_control: Enable/disable all SMU features.
1080 */
1081 int (*system_features_control)(struct smu_context *smu, bool en);
1082
1083 /**
1084 * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
1085 * &msg: Type of message.
1086 * &param: Message parameter.
1087 * &read_arg: SMU response (optional).
1088 */
1089 int (*send_smc_msg_with_param)(struct smu_context *smu,
1090 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
1091
1092 /**
1093 * @send_smc_msg: Send a message to the SMU.
1094 * &msg: Type of message.
1095 * &read_arg: SMU response (optional).
1096 */
1097 int (*send_smc_msg)(struct smu_context *smu,
1098 enum smu_message_type msg,
1099 uint32_t *read_arg);
1100
1101 /**
1102 * @init_display_count: Notify the SMU of the number of display
1103 * components in current display configuration.
1104 */
1105 int (*init_display_count)(struct smu_context *smu, uint32_t count);
1106
1107 /**
1108 * @set_allowed_mask: Notify the SMU of the features currently allowed
1109 * by the driver.
1110 */
1111 int (*set_allowed_mask)(struct smu_context *smu);
1112
1113 /**
1114 * @get_enabled_mask: Get a mask of features that are currently enabled
1115 * on the SMU.
1116 * &feature_mask: Enabled feature mask.
1117 */
1118 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
1119
1120 /**
1121 * @feature_is_enabled: Test if a feature is enabled.
1122 *
1123 * Return: One if enabled, zero if disabled.
1124 */
1125 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
1126
1127 /**
1128 * @disable_all_features_with_exception: Disable all features with
1129 * exception to those in &mask.
1130 */
1131 int (*disable_all_features_with_exception)(struct smu_context *smu,
1132 enum smu_feature_mask mask);
1133
1134 /**
1135 * @notify_display_change: General interface call to let SMU know about DC change
1136 */
1137 int (*notify_display_change)(struct smu_context *smu);
1138
1139 /**
1140 * @set_power_limit: Set power limit in watts.
1141 */
1142 int (*set_power_limit)(struct smu_context *smu,
1143 enum smu_ppt_limit_type limit_type,
1144 uint32_t limit);
1145
1146 /**
1147 * @init_max_sustainable_clocks: Populate max sustainable clock speed
1148 * table with values from the SMU.
1149 */
1150 int (*init_max_sustainable_clocks)(struct smu_context *smu);
1151
1152 /**
1153 * @enable_thermal_alert: Enable thermal alert interrupts.
1154 */
1155 int (*enable_thermal_alert)(struct smu_context *smu);
1156
1157 /**
1158 * @disable_thermal_alert: Disable thermal alert interrupts.
1159 */
1160 int (*disable_thermal_alert)(struct smu_context *smu);
1161
1162 /**
1163 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1164 * clock speed in MHz.
1165 */
1166 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1167
1168 /**
1169 * @display_clock_voltage_request: Set a hard minimum frequency
1170 * for a clock domain.
1171 */
1172 int (*display_clock_voltage_request)(struct smu_context *smu, struct
1173 pp_display_clock_request
1174 *clock_req);
1175
1176 /**
1177 * @get_fan_control_mode: Get the current fan control mode.
1178 */
1179 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1180
1181 /**
1182 * @set_fan_control_mode: Set the fan control mode.
1183 */
1184 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1185
1186 /**
1187 * @set_fan_speed_pwm: Set a static fan speed in PWM.
1188 */
1189 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
1190
1191 /**
1192 * @set_fan_speed_rpm: Set a static fan speed in rpm.
1193 */
1194 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
1195
1196 /**
1197 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1198 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1199 */
1200 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1201
1202 /**
1203 * @gfx_off_control: Enable/disable graphics engine poweroff.
1204 */
1205 int (*gfx_off_control)(struct smu_context *smu, bool enable);
1206
1207
1208 /**
1209 * @get_gfx_off_status: Get graphics engine poweroff status.
1210 *
1211 * Return:
1212 * 0 - GFXOFF(default).
1213 * 1 - Transition out of GFX State.
1214 * 2 - Not in GFXOFF.
1215 * 3 - Transition into GFXOFF.
1216 */
1217 uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1218
1219 /**
1220 * @gfx_off_entrycount: total GFXOFF entry count at the time of
1221 * query since system power-up
1222 */
1223 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount);
1224
1225 /**
1226 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging
1227 */
1228 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start);
1229
1230 /**
1231 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval
1232 */
1233 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency);
1234
1235 /**
1236 * @register_irq_handler: Register interupt request handlers.
1237 */
1238 int (*register_irq_handler)(struct smu_context *smu);
1239
1240 /**
1241 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1242 */
1243 int (*set_azalia_d3_pme)(struct smu_context *smu);
1244
1245 /**
1246 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1247 * clock speeds table.
1248 *
1249 * Provides a way for the display component (DC) to get the max
1250 * sustainable clocks from the SMU.
1251 */
1252 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1253
1254 /**
1255 * @get_bamaco_support: Check if GPU supports BACO/MACO
1256 * BACO: Bus Active, Chip Off
1257 * MACO: Memory Active, Chip Off
1258 */
1259 int (*get_bamaco_support)(struct smu_context *smu);
1260
1261 /**
1262 * @baco_get_state: Get the current BACO state.
1263 *
1264 * Return: Current BACO state.
1265 */
1266 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1267
1268 /**
1269 * @baco_set_state: Enter/exit BACO.
1270 */
1271 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1272
1273 /**
1274 * @baco_enter: Enter BACO.
1275 */
1276 int (*baco_enter)(struct smu_context *smu);
1277
1278 /**
1279 * @baco_exit: Exit Baco.
1280 */
1281 int (*baco_exit)(struct smu_context *smu);
1282
1283 /**
1284 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
1285 */
1286 bool (*mode1_reset_is_support)(struct smu_context *smu);
1287
1288 /**
1289 * @mode1_reset: Perform mode1 reset.
1290 *
1291 * Complete GPU reset.
1292 */
1293 int (*mode1_reset)(struct smu_context *smu);
1294
1295 /**
1296 * @mode2_reset: Perform mode2 reset.
1297 *
1298 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
1299 * IPs reset varies by asic.
1300 */
1301 int (*mode2_reset)(struct smu_context *smu);
1302 /* for gfx feature enablement after mode2 reset */
1303 int (*enable_gfx_features)(struct smu_context *smu);
1304
1305 /**
1306 * @link_reset: Perform link reset.
1307 *
1308 * The gfx device driver reset
1309 */
1310 int (*link_reset)(struct smu_context *smu);
1311
1312 /**
1313 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1314 * domain in MHz.
1315 */
1316 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1317
1318 /**
1319 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
1320 * domain in MHz.
1321 */
1322 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max,
1323 bool automatic);
1324
1325 /**
1326 * @set_power_source: Notify the SMU of the current power source.
1327 */
1328 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1329
1330 /**
1331 * @log_thermal_throttling_event: Print a thermal throttling warning to
1332 * the system's log.
1333 */
1334 void (*log_thermal_throttling_event)(struct smu_context *smu);
1335
1336 /**
1337 * @get_pp_feature_mask: Print a human readable table of enabled
1338 * features to buffer.
1339 */
1340 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1341
1342 /**
1343 * @set_pp_feature_mask: Request the SMU enable/disable features to
1344 * match those enabled in &new_mask.
1345 */
1346 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1347
1348 /**
1349 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1350 *
1351 * Return: Size of &table
1352 */
1353 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1354
1355 /**
1356 * @get_pm_metrics: Get one snapshot of power management metrics from
1357 * PMFW.
1358 *
1359 * Return: Size of the metrics sample
1360 */
1361 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics,
1362 size_t size);
1363
1364 /**
1365 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1366 */
1367 int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1368
1369 /**
1370 * @gfx_ulv_control: Enable/disable ultra low voltage.
1371 */
1372 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1373
1374 /**
1375 * @deep_sleep_control: Enable/disable deep sleep.
1376 */
1377 int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1378
1379 /**
1380 * @get_fan_parameters: Get fan parameters.
1381 *
1382 * Get maximum fan speed from the power play table.
1383 */
1384 int (*get_fan_parameters)(struct smu_context *smu);
1385
1386 /**
1387 * @post_init: Helper function for asic specific workarounds.
1388 */
1389 int (*post_init)(struct smu_context *smu);
1390
1391 /**
1392 * @interrupt_work: Work task scheduled from SMU interrupt handler.
1393 */
1394 void (*interrupt_work)(struct smu_context *smu);
1395
1396 /**
1397 * @gpo_control: Enable/disable graphics power optimization if supported.
1398 */
1399 int (*gpo_control)(struct smu_context *smu, bool enablement);
1400
1401 /**
1402 * @gfx_state_change_set: Send the current graphics state to the SMU.
1403 */
1404 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1405
1406 /**
1407 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1408 * parameters to defaults.
1409 */
1410 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1411
1412 /**
1413 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
1414 */
1415 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
1416
1417 /**
1418 * @wait_for_event: Wait for events from SMU.
1419 */
1420 int (*wait_for_event)(struct smu_context *smu,
1421 enum smu_event_type event, uint64_t event_arg);
1422
1423 /**
1424 * @sned_hbm_bad_pages_num: message SMU to update bad page number
1425 * of SMUBUS table.
1426 */
1427 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1428
1429 /**
1430 * @send_rma_reason: message rma reason event to SMU.
1431 */
1432 int (*send_rma_reason)(struct smu_context *smu);
1433
1434 /**
1435 * @reset_sdma: message SMU to soft reset sdma instance.
1436 */
1437 int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask);
1438
1439 /**
1440 * @reset_vcn: message SMU to soft reset vcn instance.
1441 */
1442 int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask);
1443
1444 /**
1445 * @get_ecc_table: message SMU to get ECC INFO table.
1446 */
1447 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
1448
1449
1450 /**
1451 * @stb_collect_info: Collects Smart Trace Buffers data.
1452 */
1453 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
1454
1455 /**
1456 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
1457 */
1458 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
1459
1460 /**
1461 * @set_config_table: Apply the input DriverSmuConfig table settings.
1462 */
1463 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
1464
1465 /**
1466 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info
1467 * of SMUBUS table.
1468 */
1469 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
1470
1471 /**
1472 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
1473 */
1474 int (*init_pptable_microcode)(struct smu_context *smu);
1475
1476 /**
1477 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power
1478 * management.
1479 */
1480 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable);
1481
1482 /**
1483 * @dpm_set_isp_enable: Enable/disable ISP engine dynamic power
1484 * management.
1485 */
1486 int (*dpm_set_isp_enable)(struct smu_context *smu, bool enable);
1487
1488 /**
1489 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power
1490 * management.
1491 */
1492 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
1493
1494 /**
1495 * @set_mall_enable: Init MALL power gating control.
1496 */
1497 int (*set_mall_enable)(struct smu_context *smu);
1498
1499 /**
1500 * @notify_rlc_state: Notify RLC power state to SMU.
1501 */
1502 int (*notify_rlc_state)(struct smu_context *smu, bool en);
1503
1504 /**
1505 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature
1506 */
1507 bool (*is_asic_wbrf_supported)(struct smu_context *smu);
1508
1509 /**
1510 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported
1511 */
1512 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);
1513
1514 /**
1515 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied
1516 */
1517 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu,
1518 struct freq_band_range *exclusion_ranges);
1519 /**
1520 * @get_xcp_metrics: Get a copy of the partition metrics table from SMU.
1521 * Return: Size of table
1522 */
1523 ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id,
1524 void *table);
1525 /**
1526 * @ras_send_msg: Send a message with a parameter from Ras
1527 * &msg: Type of message.
1528 * &param: Message parameter.
1529 * &read_arg: SMU response (optional).
1530 */
1531 int (*ras_send_msg)(struct smu_context *smu,
1532 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
1533
1534
1535 /**
1536 * @get_ras_smu_drv: Get RAS smu driver interface
1537 * Return: ras_smu_drv *
1538 */
1539 int (*get_ras_smu_drv)(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv);
1540};
1541
1542typedef enum {
1543 METRICS_CURR_GFXCLK,
1544 METRICS_CURR_SOCCLK,
1545 METRICS_CURR_UCLK,
1546 METRICS_CURR_VCLK,
1547 METRICS_CURR_VCLK1,
1548 METRICS_CURR_DCLK,
1549 METRICS_CURR_DCLK1,
1550 METRICS_CURR_FCLK,
1551 METRICS_CURR_DCEFCLK,
1552 METRICS_AVERAGE_CPUCLK,
1553 METRICS_AVERAGE_GFXCLK,
1554 METRICS_AVERAGE_SOCCLK,
1555 METRICS_AVERAGE_FCLK,
1556 METRICS_AVERAGE_UCLK,
1557 METRICS_AVERAGE_VCLK,
1558 METRICS_AVERAGE_DCLK,
1559 METRICS_AVERAGE_VCLK1,
1560 METRICS_AVERAGE_DCLK1,
1561 METRICS_AVERAGE_GFXACTIVITY,
1562 METRICS_AVERAGE_MEMACTIVITY,
1563 METRICS_AVERAGE_VCNACTIVITY,
1564 METRICS_AVERAGE_SOCKETPOWER,
1565 METRICS_TEMPERATURE_EDGE,
1566 METRICS_TEMPERATURE_HOTSPOT,
1567 METRICS_TEMPERATURE_MEM,
1568 METRICS_TEMPERATURE_VRGFX,
1569 METRICS_TEMPERATURE_VRSOC,
1570 METRICS_TEMPERATURE_VRMEM,
1571 METRICS_THROTTLER_STATUS,
1572 METRICS_CURR_FANSPEED,
1573 METRICS_VOLTAGE_VDDSOC,
1574 METRICS_VOLTAGE_VDDGFX,
1575 METRICS_SS_APU_SHARE,
1576 METRICS_SS_DGPU_SHARE,
1577 METRICS_UNIQUE_ID_UPPER32,
1578 METRICS_UNIQUE_ID_LOWER32,
1579 METRICS_PCIE_RATE,
1580 METRICS_PCIE_WIDTH,
1581 METRICS_CURR_FANPWM,
1582 METRICS_CURR_SOCKETPOWER,
1583 METRICS_AVERAGE_VPECLK,
1584 METRICS_AVERAGE_IPUCLK,
1585 METRICS_AVERAGE_MPIPUCLK,
1586 METRICS_THROTTLER_RESIDENCY_PROCHOT,
1587 METRICS_THROTTLER_RESIDENCY_SPL,
1588 METRICS_THROTTLER_RESIDENCY_FPPT,
1589 METRICS_THROTTLER_RESIDENCY_SPPT,
1590 METRICS_THROTTLER_RESIDENCY_THM_CORE,
1591 METRICS_THROTTLER_RESIDENCY_THM_GFX,
1592 METRICS_THROTTLER_RESIDENCY_THM_SOC,
1593} MetricsMember_t;
1594
1595enum smu_cmn2asic_mapping_type {
1596 CMN2ASIC_MAPPING_MSG,
1597 CMN2ASIC_MAPPING_CLK,
1598 CMN2ASIC_MAPPING_FEATURE,
1599 CMN2ASIC_MAPPING_TABLE,
1600 CMN2ASIC_MAPPING_PWR,
1601 CMN2ASIC_MAPPING_WORKLOAD,
1602};
1603
1604enum smu_baco_seq {
1605 BACO_SEQ_BACO = 0,
1606 BACO_SEQ_MSR,
1607 BACO_SEQ_BAMACO,
1608 BACO_SEQ_ULPS,
1609 BACO_SEQ_COUNT,
1610};
1611
1612#define MSG_MAP(msg, index, flags) \
1613 [SMU_MSG_##msg] = {1, (index), (flags)}
1614
1615#define CLK_MAP(clk, index) \
1616 [SMU_##clk] = {1, (index)}
1617
1618#define FEA_MAP(fea) \
1619 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1620
1621#define FEA_MAP_REVERSE(fea) \
1622 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1623
1624#define FEA_MAP_HALF_REVERSE(fea) \
1625 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1626
1627#define TAB_MAP(tab) \
1628 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1629
1630#define TAB_MAP_VALID(tab) \
1631 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1632
1633#define TAB_MAP_INVALID(tab) \
1634 [SMU_TABLE_##tab] = {0, TABLE_##tab}
1635
1636#define PWR_MAP(tab) \
1637 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1638
1639#define WORKLOAD_MAP(profile, workload) \
1640 [profile] = {1, (workload)}
1641
1642/**
1643 * smu_memcpy_trailing - Copy the end of one structure into the middle of another
1644 *
1645 * @dst: Pointer to destination struct
1646 * @first_dst_member: The member name in @dst where the overwrite begins
1647 * @last_dst_member: The member name in @dst where the overwrite ends after
1648 * @src: Pointer to the source struct
1649 * @first_src_member: The member name in @src where the copy begins
1650 *
1651 */
1652#define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \
1653 src, first_src_member) \
1654({ \
1655 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \
1656 size_t __src_size = sizeof(*(src)) - __src_offset; \
1657 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \
1658 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
1659 __dst_offset; \
1660 BUILD_BUG_ON(__src_size != __dst_size); \
1661 __builtin_memcpy((u8 *)(dst) + __dst_offset, \
1662 (u8 *)(src) + __src_offset, \
1663 __dst_size); \
1664})
1665
1666typedef struct {
1667 uint16_t LowFreq;
1668 uint16_t HighFreq;
1669} WifiOneBand_t;
1670
1671typedef struct {
1672 uint32_t WifiBandEntryNum;
1673 WifiOneBand_t WifiBandEntry[11];
1674 uint32_t MmHubPadding[8];
1675} WifiBandEntryTable_t;
1676
1677#define STR_SOC_PSTATE_POLICY "soc_pstate"
1678#define STR_XGMI_PLPD_POLICY "xgmi_plpd"
1679
1680struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
1681 enum pp_pm_policy p_type);
1682
1683static inline enum smu_table_id
1684smu_metrics_get_temp_table_id(enum smu_temp_metric_type type)
1685{
1686 switch (type) {
1687 case SMU_TEMP_METRIC_BASEBOARD:
1688 return SMU_TABLE_BASEBOARD_TEMP_METRICS;
1689 case SMU_TEMP_METRIC_GPUBOARD:
1690 return SMU_TABLE_GPUBOARD_TEMP_METRICS;
1691 default:
1692 return SMU_TABLE_COUNT;
1693 }
1694
1695 return SMU_TABLE_COUNT;
1696}
1697
1698static inline void smu_table_cache_update_time(struct smu_table *table,
1699 unsigned long time)
1700{
1701 table->cache.last_cache_time = time;
1702}
1703
1704static inline bool smu_table_cache_is_valid(struct smu_table *table)
1705{
1706 if (!table->cache.buffer || !table->cache.last_cache_time ||
1707 !table->cache.interval || !table->cache.size ||
1708 time_after(jiffies,
1709 table->cache.last_cache_time +
1710 msecs_to_jiffies(table->cache.interval)))
1711 return false;
1712
1713 return true;
1714}
1715
1716static inline int smu_table_cache_init(struct smu_context *smu,
1717 enum smu_table_id table_id, size_t size,
1718 uint32_t cache_interval)
1719{
1720 struct smu_table_context *smu_table = &smu->smu_table;
1721 struct smu_table *tables = smu_table->tables;
1722
1723 tables[table_id].cache.buffer = kzalloc(size, GFP_KERNEL);
1724 if (!tables[table_id].cache.buffer)
1725 return -ENOMEM;
1726
1727 tables[table_id].cache.last_cache_time = 0;
1728 tables[table_id].cache.interval = cache_interval;
1729 tables[table_id].cache.size = size;
1730
1731 return 0;
1732}
1733
1734static inline void smu_table_cache_fini(struct smu_context *smu,
1735 enum smu_table_id table_id)
1736{
1737 struct smu_table_context *smu_table = &smu->smu_table;
1738 struct smu_table *tables = smu_table->tables;
1739
1740 if (tables[table_id].cache.buffer) {
1741 kfree(objp: tables[table_id].cache.buffer);
1742 tables[table_id].cache.buffer = NULL;
1743 tables[table_id].cache.last_cache_time = 0;
1744 tables[table_id].cache.interval = 0;
1745 }
1746}
1747
1748#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1749int smu_get_power_limit(void *handle,
1750 uint32_t *limit,
1751 enum pp_power_limit_level pp_limit_level,
1752 enum pp_power_type pp_power_type);
1753
1754bool smu_mode1_reset_is_support(struct smu_context *smu);
1755bool smu_link_reset_is_support(struct smu_context *smu);
1756int smu_mode1_reset(struct smu_context *smu);
1757int smu_link_reset(struct smu_context *smu);
1758
1759extern const struct amd_ip_funcs smu_ip_funcs;
1760
1761bool is_support_sw_smu(struct amdgpu_device *adev);
1762bool is_support_cclk_dpm(struct amdgpu_device *adev);
1763int smu_write_watermarks_table(struct smu_context *smu);
1764
1765int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1766 uint32_t *min, uint32_t *max);
1767
1768int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,
1769 uint32_t min, uint32_t max);
1770
1771int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
1772
1773int smu_set_ac_dc(struct smu_context *smu);
1774
1775int smu_set_xgmi_plpd_mode(struct smu_context *smu,
1776 enum pp_xgmi_plpd_mode mode);
1777
1778int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value);
1779
1780int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value);
1781
1782int smu_set_residency_gfxoff(struct smu_context *smu, bool value);
1783
1784int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
1785
1786int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1787
1788int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1789 uint64_t event_arg);
1790int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
1791int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
1792void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
1793int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
1794int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
1795int smu_send_rma_reason(struct smu_context *smu);
1796int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask);
1797bool smu_reset_sdma_is_supported(struct smu_context *smu);
1798int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask);
1799bool smu_reset_vcn_is_supported(struct smu_context *smu);
1800int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
1801 int level);
1802ssize_t smu_get_pm_policy_info(struct smu_context *smu,
1803 enum pp_pm_policy p_type, char *sysbuf);
1804const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle);
1805
1806int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg,
1807 uint32_t param, uint32_t *readarg);
1808#endif
1809
1810void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);
1811bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id);
1812#endif
1813

source code of linux/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h