| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _vcn_1_0_OFFSET_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | |
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| 26 | // addressBlock: uvd_uvd_pg_dec |
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| 27 | // base address: 0x1fb00 |
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| 28 | #define mmUVD_PGFSM_CONFIG 0x00c0 |
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| 29 | #define mmUVD_PGFSM_CONFIG_BASE_IDX 1 |
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| 30 | #define mmUVD_PGFSM_STATUS 0x00c1 |
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| 31 | #define mmUVD_PGFSM_STATUS_BASE_IDX 1 |
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| 32 | #define mmUVD_POWER_STATUS 0x00c4 |
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| 33 | #define mmUVD_POWER_STATUS_BASE_IDX 1 |
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| 34 | #define mmCC_UVD_HARVESTING 0x00c7 |
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| 35 | #define mmCC_UVD_HARVESTING_BASE_IDX 1 |
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| 36 | #define mmUVD_DPG_LMA_CTL 0x00d1 |
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| 37 | #define mmUVD_DPG_LMA_CTL_BASE_IDX 1 |
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| 38 | #define mmUVD_DPG_LMA_DATA 0x00d2 |
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| 39 | #define mmUVD_DPG_LMA_DATA_BASE_IDX 1 |
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| 40 | #define mmUVD_DPG_LMA_MASK 0x00d3 |
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| 41 | #define mmUVD_DPG_LMA_MASK_BASE_IDX 1 |
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| 42 | #define mmUVD_DPG_PAUSE 0x00d4 |
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| 43 | #define mmUVD_DPG_PAUSE_BASE_IDX 1 |
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| 44 | #define mmUVD_SCRATCH1 0x00d5 |
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| 45 | #define mmUVD_SCRATCH1_BASE_IDX 1 |
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| 46 | #define mmUVD_SCRATCH2 0x00d6 |
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| 47 | #define mmUVD_SCRATCH2_BASE_IDX 1 |
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| 48 | #define mmUVD_SCRATCH3 0x00d7 |
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| 49 | #define mmUVD_SCRATCH3_BASE_IDX 1 |
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| 50 | #define mmUVD_SCRATCH4 0x00d8 |
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| 51 | #define mmUVD_SCRATCH4_BASE_IDX 1 |
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| 52 | #define mmUVD_SCRATCH5 0x00d9 |
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| 53 | #define mmUVD_SCRATCH5_BASE_IDX 1 |
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| 54 | #define mmUVD_SCRATCH6 0x00da |
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| 55 | #define mmUVD_SCRATCH6_BASE_IDX 1 |
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| 56 | #define mmUVD_SCRATCH7 0x00db |
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| 57 | #define mmUVD_SCRATCH7_BASE_IDX 1 |
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| 58 | #define mmUVD_SCRATCH8 0x00dc |
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| 59 | #define mmUVD_SCRATCH8_BASE_IDX 1 |
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| 60 | #define mmUVD_SCRATCH9 0x00dd |
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| 61 | #define mmUVD_SCRATCH9_BASE_IDX 1 |
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| 62 | #define mmUVD_SCRATCH10 0x00de |
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| 63 | #define mmUVD_SCRATCH10_BASE_IDX 1 |
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| 64 | #define mmUVD_SCRATCH11 0x00df |
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| 65 | #define mmUVD_SCRATCH11_BASE_IDX 1 |
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| 66 | #define mmUVD_SCRATCH12 0x00e0 |
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| 67 | #define mmUVD_SCRATCH12_BASE_IDX 1 |
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| 68 | #define mmUVD_SCRATCH13 0x00e1 |
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| 69 | #define mmUVD_SCRATCH13_BASE_IDX 1 |
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| 70 | #define mmUVD_SCRATCH14 0x00e2 |
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| 71 | #define mmUVD_SCRATCH14_BASE_IDX 1 |
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| 72 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5 |
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| 73 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
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| 74 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6 |
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| 75 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 76 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7 |
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| 77 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
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| 78 | |
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| 79 | |
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| 80 | // addressBlock: uvd_uvdgendec |
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| 81 | // base address: 0x1fc00 |
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| 82 | #define mmUVD_LCM_CGC_CNTRL 0x0123 |
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| 83 | #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 |
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| 84 | |
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| 85 | #define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184 |
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| 86 | #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 |
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| 87 | #define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185 |
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| 88 | #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 |
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| 89 | #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186 |
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| 90 | #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 |
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| 91 | #define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192 |
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| 92 | #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 |
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| 93 | #define mmUVD_MIF_REF_ADDR_CONFIG 0x0193 |
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| 94 | #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 |
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| 95 | #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5 |
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| 96 | #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 |
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| 97 | |
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| 98 | // addressBlock: uvd_uvdnpdec |
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| 99 | // base address: 0x20000 |
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| 100 | #define mmUVD_JPEG_CNTL 0x0200 |
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| 101 | #define mmUVD_JPEG_CNTL_BASE_IDX 1 |
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| 102 | #define mmUVD_JPEG_RB_BASE 0x0201 |
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| 103 | #define mmUVD_JPEG_RB_BASE_BASE_IDX 1 |
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| 104 | #define mmUVD_JPEG_RB_WPTR 0x0202 |
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| 105 | #define mmUVD_JPEG_RB_WPTR_BASE_IDX 1 |
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| 106 | #define mmUVD_JPEG_RB_RPTR 0x0203 |
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| 107 | #define mmUVD_JPEG_RB_RPTR_BASE_IDX 1 |
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| 108 | #define mmUVD_JPEG_RB_SIZE 0x0204 |
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| 109 | #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 |
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| 110 | #define mmUVD_JPEG_ADDR_CONFIG 0x021f |
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| 111 | #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 |
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| 112 | #define mmUVD_JPEG_PITCH 0x0222 |
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| 113 | #define mmUVD_JPEG_PITCH_BASE_IDX 1 |
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| 114 | #define mmUVD_JPEG_GPCOM_CMD 0x022c |
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| 115 | #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 1 |
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| 116 | #define mmUVD_JPEG_GPCOM_DATA0 0x022d |
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| 117 | #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 |
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| 118 | #define mmUVD_JPEG_GPCOM_DATA1 0x022e |
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| 119 | #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 |
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| 120 | #define mmUVD_JPEG_JRB_BASE_LO 0x022f |
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| 121 | #define mmUVD_JPEG_JRB_BASE_LO_BASE_IDX 1 |
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| 122 | #define mmUVD_JPEG_JRB_BASE_HI 0x0230 |
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| 123 | #define mmUVD_JPEG_JRB_BASE_HI_BASE_IDX 1 |
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| 124 | #define mmUVD_JPEG_JRB_SIZE 0x0232 |
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| 125 | #define mmUVD_JPEG_JRB_SIZE_BASE_IDX 1 |
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| 126 | #define mmUVD_JPEG_JRB_RPTR 0x0233 |
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| 127 | #define mmUVD_JPEG_JRB_RPTR_BASE_IDX 1 |
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| 128 | #define mmUVD_JPEG_JRB_WPTR 0x0234 |
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| 129 | #define mmUVD_JPEG_JRB_WPTR_BASE_IDX 1 |
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| 130 | #define mmUVD_JPEG_UV_ADDR_CONFIG 0x0238 |
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| 131 | #define mmUVD_JPEG_UV_ADDR_CONFIG_BASE_IDX 1 |
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| 132 | #define mmUVD_SEMA_ADDR_LOW 0x03c0 |
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| 133 | #define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 |
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| 134 | #define mmUVD_SEMA_ADDR_HIGH 0x03c1 |
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| 135 | #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 |
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| 136 | #define mmUVD_SEMA_CMD 0x03c2 |
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| 137 | #define mmUVD_SEMA_CMD_BASE_IDX 1 |
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| 138 | #define mmUVD_GPCOM_VCPU_CMD 0x03c3 |
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| 139 | #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 |
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| 140 | #define mmUVD_GPCOM_VCPU_DATA0 0x03c4 |
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| 141 | #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 |
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| 142 | #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 |
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| 143 | #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 |
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| 144 | #define mmUVD_ENGINE_CNTL 0x03c6 |
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| 145 | #define mmUVD_ENGINE_CNTL_BASE_IDX 1 |
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| 146 | #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2 |
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| 147 | #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1 |
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| 148 | #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 |
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| 149 | #define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1 |
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| 150 | #define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4 |
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| 151 | #define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1 |
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| 152 | #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 |
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| 153 | #define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1 |
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| 154 | #define mmUVD_SUVD_CGC_GATE 0x03e4 |
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| 155 | #define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 |
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| 156 | #define mmUVD_SUVD_CGC_STATUS 0x03e5 |
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| 157 | #define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 |
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| 158 | #define mmUVD_SUVD_CGC_CTRL 0x03e6 |
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| 159 | #define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 |
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| 160 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec |
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| 161 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 |
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| 162 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed |
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| 163 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 164 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0 |
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| 165 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 |
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| 166 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1 |
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| 167 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 168 | #define mmUVD_NO_OP 0x03ff |
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| 169 | #define mmUVD_NO_OP_BASE_IDX 1 |
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| 170 | #define mmUVD_JPEG_CNTL2 0x0404 |
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| 171 | #define mmUVD_JPEG_CNTL2_BASE_IDX 1 |
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| 172 | #define mmUVD_VERSION 0x0409 |
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| 173 | #define mmUVD_VERSION_BASE_IDX 1 |
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| 174 | #define mmUVD_GP_SCRATCH8 0x040a |
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| 175 | #define mmUVD_GP_SCRATCH8_BASE_IDX 1 |
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| 176 | #define mmUVD_GP_SCRATCH9 0x040b |
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| 177 | #define mmUVD_GP_SCRATCH9_BASE_IDX 1 |
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| 178 | #define mmUVD_GP_SCRATCH10 0x040c |
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| 179 | #define mmUVD_GP_SCRATCH10_BASE_IDX 1 |
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| 180 | #define mmUVD_GP_SCRATCH11 0x040d |
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| 181 | #define mmUVD_GP_SCRATCH11_BASE_IDX 1 |
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| 182 | #define mmUVD_GP_SCRATCH12 0x040e |
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| 183 | #define mmUVD_GP_SCRATCH12_BASE_IDX 1 |
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| 184 | #define mmUVD_GP_SCRATCH13 0x040f |
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| 185 | #define mmUVD_GP_SCRATCH13_BASE_IDX 1 |
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| 186 | #define mmUVD_GP_SCRATCH14 0x0410 |
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| 187 | #define mmUVD_GP_SCRATCH14_BASE_IDX 1 |
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| 188 | #define mmUVD_GP_SCRATCH15 0x0411 |
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| 189 | #define mmUVD_GP_SCRATCH15_BASE_IDX 1 |
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| 190 | #define mmUVD_GP_SCRATCH16 0x0412 |
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| 191 | #define mmUVD_GP_SCRATCH16_BASE_IDX 1 |
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| 192 | #define mmUVD_GP_SCRATCH17 0x0413 |
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| 193 | #define mmUVD_GP_SCRATCH17_BASE_IDX 1 |
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| 194 | #define mmUVD_GP_SCRATCH18 0x0414 |
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| 195 | #define mmUVD_GP_SCRATCH18_BASE_IDX 1 |
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| 196 | #define mmUVD_GP_SCRATCH19 0x0415 |
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| 197 | #define mmUVD_GP_SCRATCH19_BASE_IDX 1 |
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| 198 | #define mmUVD_GP_SCRATCH20 0x0416 |
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| 199 | #define mmUVD_GP_SCRATCH20_BASE_IDX 1 |
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| 200 | #define mmUVD_GP_SCRATCH21 0x0417 |
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| 201 | #define mmUVD_GP_SCRATCH21_BASE_IDX 1 |
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| 202 | #define mmUVD_GP_SCRATCH22 0x0418 |
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| 203 | #define mmUVD_GP_SCRATCH22_BASE_IDX 1 |
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| 204 | #define mmUVD_GP_SCRATCH23 0x0419 |
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| 205 | #define mmUVD_GP_SCRATCH23_BASE_IDX 1 |
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| 206 | #define mmUVD_RB_BASE_LO2 0x0421 |
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| 207 | #define mmUVD_RB_BASE_LO2_BASE_IDX 1 |
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| 208 | #define mmUVD_RB_BASE_HI2 0x0422 |
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| 209 | #define mmUVD_RB_BASE_HI2_BASE_IDX 1 |
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| 210 | #define mmUVD_RB_SIZE2 0x0423 |
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| 211 | #define mmUVD_RB_SIZE2_BASE_IDX 1 |
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| 212 | #define mmUVD_RB_RPTR2 0x0424 |
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| 213 | #define mmUVD_RB_RPTR2_BASE_IDX 1 |
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| 214 | #define mmUVD_RB_WPTR2 0x0425 |
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| 215 | #define mmUVD_RB_WPTR2_BASE_IDX 1 |
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| 216 | #define mmUVD_RB_BASE_LO 0x0426 |
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| 217 | #define mmUVD_RB_BASE_LO_BASE_IDX 1 |
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| 218 | #define mmUVD_RB_BASE_HI 0x0427 |
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| 219 | #define mmUVD_RB_BASE_HI_BASE_IDX 1 |
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| 220 | #define mmUVD_RB_SIZE 0x0428 |
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| 221 | #define mmUVD_RB_SIZE_BASE_IDX 1 |
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| 222 | #define mmUVD_RB_RPTR 0x0429 |
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| 223 | #define mmUVD_RB_RPTR_BASE_IDX 1 |
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| 224 | #define mmUVD_RB_WPTR 0x042a |
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| 225 | #define mmUVD_RB_WPTR_BASE_IDX 1 |
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| 226 | #define mmUVD_RB_WPTR4 0x0456 |
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| 227 | #define mmUVD_RB_WPTR4_BASE_IDX 1 |
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| 228 | #define mmUVD_JRBC_RB_RPTR 0x0457 |
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| 229 | #define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 |
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| 230 | #define mmUVD_LMI_JPEG_VMID 0x045d |
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| 231 | #define mmUVD_LMI_JPEG_VMID_BASE_IDX 1 |
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| 232 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e |
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| 233 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 234 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f |
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| 235 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
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| 236 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466 |
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| 237 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 238 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467 |
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| 239 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 240 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0468 |
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| 241 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 242 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0469 |
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| 243 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 244 | |
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| 245 | |
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| 246 | // addressBlock: uvd_uvddec |
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| 247 | // base address: 0x20c00 |
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| 248 | #define mmUVD_SEMA_CNTL 0x0500 |
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| 249 | #define mmUVD_SEMA_CNTL_BASE_IDX 1 |
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| 250 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 |
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| 251 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 252 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0504 |
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| 253 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 254 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0505 |
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| 255 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 256 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0506 |
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| 257 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 258 | #define mmUVD_LMI_JRBC_IB_VMID 0x0507 |
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| 259 | #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 |
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| 260 | #define mmUVD_LMI_JRBC_RB_VMID 0x0508 |
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| 261 | #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 |
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| 262 | #define mmUVD_JRBC_RB_WPTR 0x0509 |
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| 263 | #define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 |
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| 264 | #define mmUVD_JRBC_RB_CNTL 0x050a |
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| 265 | #define mmUVD_JRBC_RB_CNTL_BASE_IDX 1 |
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| 266 | #define mmUVD_JRBC_IB_SIZE 0x050b |
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| 267 | #define mmUVD_JRBC_IB_SIZE_BASE_IDX 1 |
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| 268 | #define mmUVD_JRBC_LMI_SWAP_CNTL 0x050d |
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| 269 | #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX 1 |
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| 270 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x050e |
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| 271 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 |
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| 272 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x050f |
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| 273 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 274 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0510 |
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| 275 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 |
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| 276 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0511 |
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| 277 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 278 | #define mmUVD_JRBC_RB_REF_DATA 0x0512 |
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| 279 | #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 1 |
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| 280 | #define mmUVD_JRBC_RB_COND_RD_TIMER 0x0513 |
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| 281 | #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 |
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| 282 | #define mmUVD_JRBC_EXTERNAL_REG_BASE 0x0517 |
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| 283 | #define mmUVD_JRBC_EXTERNAL_REG_BASE_BASE_IDX 1 |
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| 284 | #define mmUVD_JRBC_SOFT_RESET 0x0519 |
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| 285 | #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 1 |
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| 286 | #define mmUVD_JRBC_STATUS 0x051a |
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| 287 | #define mmUVD_JRBC_STATUS_BASE_IDX 1 |
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| 288 | #define mmUVD_RB_RPTR3 0x051b |
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| 289 | #define mmUVD_RB_RPTR3_BASE_IDX 1 |
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| 290 | #define mmUVD_RB_WPTR3 0x051c |
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| 291 | #define mmUVD_RB_WPTR3_BASE_IDX 1 |
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| 292 | #define mmUVD_RB_BASE_LO3 0x051d |
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| 293 | #define mmUVD_RB_BASE_LO3_BASE_IDX 1 |
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| 294 | #define mmUVD_RB_BASE_HI3 0x051e |
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| 295 | #define mmUVD_RB_BASE_HI3_BASE_IDX 1 |
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| 296 | #define mmUVD_RB_SIZE3 0x051f |
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| 297 | #define mmUVD_RB_SIZE3_BASE_IDX 1 |
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| 298 | #define mmJPEG_CGC_GATE 0x0526 |
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| 299 | #define mmJPEG_CGC_GATE_BASE_IDX 1 |
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| 300 | #define mmUVD_CTX_INDEX 0x0528 |
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| 301 | #define mmUVD_CTX_INDEX_BASE_IDX 1 |
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| 302 | #define mmUVD_CTX_DATA 0x0529 |
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| 303 | #define mmUVD_CTX_DATA_BASE_IDX 1 |
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| 304 | #define mmUVD_CGC_GATE 0x052a |
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| 305 | #define mmUVD_CGC_GATE_BASE_IDX 1 |
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| 306 | #define mmUVD_CGC_STATUS 0x052b |
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| 307 | #define mmUVD_CGC_STATUS_BASE_IDX 1 |
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| 308 | #define mmUVD_CGC_CTRL 0x052c |
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| 309 | #define mmUVD_CGC_CTRL_BASE_IDX 1 |
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| 310 | #define mmUVD_GP_SCRATCH0 0x0534 |
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| 311 | #define mmUVD_GP_SCRATCH0_BASE_IDX 1 |
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| 312 | #define mmUVD_GP_SCRATCH1 0x0535 |
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| 313 | #define mmUVD_GP_SCRATCH1_BASE_IDX 1 |
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| 314 | #define mmUVD_GP_SCRATCH2 0x0536 |
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| 315 | #define mmUVD_GP_SCRATCH2_BASE_IDX 1 |
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| 316 | #define mmUVD_GP_SCRATCH3 0x0537 |
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| 317 | #define mmUVD_GP_SCRATCH3_BASE_IDX 1 |
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| 318 | #define mmUVD_GP_SCRATCH4 0x0538 |
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| 319 | #define mmUVD_GP_SCRATCH4_BASE_IDX 1 |
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| 320 | #define mmUVD_GP_SCRATCH5 0x0539 |
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| 321 | #define mmUVD_GP_SCRATCH5_BASE_IDX 1 |
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| 322 | #define mmUVD_GP_SCRATCH6 0x053a |
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| 323 | #define mmUVD_GP_SCRATCH6_BASE_IDX 1 |
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| 324 | #define mmUVD_GP_SCRATCH7 0x053b |
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| 325 | #define mmUVD_GP_SCRATCH7_BASE_IDX 1 |
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| 326 | #define mmUVD_LMI_VCPU_CACHE_VMID 0x053c |
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| 327 | #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 |
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| 328 | #define mmUVD_LMI_CTRL2 0x053d |
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| 329 | #define mmUVD_LMI_CTRL2_BASE_IDX 1 |
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| 330 | #define mmUVD_MASTINT_EN 0x0540 |
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| 331 | #define mmUVD_MASTINT_EN_BASE_IDX 1 |
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| 332 | #define mmUVD_SYS_INT_EN 0x0541 |
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| 333 | #define mmUVD_SYS_INT_EN_BASE_IDX 1 |
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| 334 | #define mmJPEG_CGC_CTRL 0x0565 |
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| 335 | #define mmJPEG_CGC_CTRL_BASE_IDX 1 |
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| 336 | #define mmUVD_LMI_CTRL 0x0566 |
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| 337 | #define mmUVD_LMI_CTRL_BASE_IDX 1 |
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| 338 | #define mmUVD_LMI_STATUS 0x0567 |
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| 339 | #define mmUVD_LMI_STATUS_BASE_IDX 1 |
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| 340 | #define mmUVD_LMI_VM_CTRL 0x0568 |
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| 341 | #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 |
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| 342 | #define mmUVD_LMI_SWAP_CNTL 0x056d |
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| 343 | #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 |
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| 344 | #define mmUVD_MPC_CNTL 0x0577 |
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| 345 | #define mmUVD_MPC_CNTL_BASE_IDX 1 |
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| 346 | #define mmUVD_MPC_SET_MUXA0 0x0579 |
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| 347 | #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 |
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| 348 | #define mmUVD_MPC_SET_MUXA1 0x057a |
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| 349 | #define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 |
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| 350 | #define mmUVD_MPC_SET_MUXB0 0x057b |
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| 351 | #define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 |
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| 352 | #define mmUVD_MPC_SET_MUXB1 0x057c |
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| 353 | #define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 |
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| 354 | #define mmUVD_MPC_SET_MUX 0x057d |
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| 355 | #define mmUVD_MPC_SET_MUX_BASE_IDX 1 |
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| 356 | #define mmUVD_MPC_SET_ALU 0x057e |
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| 357 | #define mmUVD_MPC_SET_ALU_BASE_IDX 1 |
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| 358 | #define mmUVD_GPCOM_SYS_CMD 0x057f |
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| 359 | #define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 |
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| 360 | #define mmUVD_GPCOM_SYS_DATA0 0x0580 |
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| 361 | #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 |
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| 362 | #define mmUVD_GPCOM_SYS_DATA1 0x0581 |
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| 363 | #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 |
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| 364 | #define mmUVD_VCPU_CACHE_OFFSET0 0x0582 |
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| 365 | #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
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| 366 | #define mmUVD_VCPU_CACHE_SIZE0 0x0583 |
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| 367 | #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 |
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| 368 | #define mmUVD_VCPU_CACHE_OFFSET1 0x0584 |
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| 369 | #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 |
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| 370 | #define mmUVD_VCPU_CACHE_SIZE1 0x0585 |
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| 371 | #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 |
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| 372 | #define mmUVD_VCPU_CACHE_OFFSET2 0x0586 |
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| 373 | #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 |
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| 374 | #define mmUVD_VCPU_CACHE_SIZE2 0x0587 |
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| 375 | #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 |
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| 376 | #define mmUVD_VCPU_CNTL 0x0598 |
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| 377 | #define mmUVD_VCPU_CNTL_BASE_IDX 1 |
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| 378 | #define mmUVD_SOFT_RESET 0x05a0 |
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| 379 | #define mmUVD_SOFT_RESET_BASE_IDX 1 |
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| 380 | #define mmUVD_LMI_RBC_IB_VMID 0x05a1 |
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| 381 | #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 |
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| 382 | #define mmUVD_RBC_IB_SIZE 0x05a2 |
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| 383 | #define mmUVD_RBC_IB_SIZE_BASE_IDX 1 |
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| 384 | #define mmUVD_RBC_RB_RPTR 0x05a4 |
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| 385 | #define mmUVD_RBC_RB_RPTR_BASE_IDX 1 |
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| 386 | #define mmUVD_RBC_RB_WPTR 0x05a5 |
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| 387 | #define mmUVD_RBC_RB_WPTR_BASE_IDX 1 |
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| 388 | #define mmUVD_RBC_RB_WPTR_CNTL 0x05a6 |
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| 389 | #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 |
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| 390 | #define mmUVD_RBC_RB_CNTL 0x05a9 |
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| 391 | #define mmUVD_RBC_RB_CNTL_BASE_IDX 1 |
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| 392 | #define mmUVD_RBC_RB_RPTR_ADDR 0x05aa |
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| 393 | #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 |
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| 394 | #define mmUVD_STATUS 0x05af |
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| 395 | #define mmUVD_STATUS_BASE_IDX 1 |
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| 396 | #define mmUVD_SEMA_TIMEOUT_STATUS 0x05b0 |
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| 397 | #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 |
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| 398 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x05b1 |
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| 399 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
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| 400 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2 |
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| 401 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 |
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| 402 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x05b3 |
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| 403 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
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| 404 | #define mmUVD_CONTEXT_ID 0x05bd |
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| 405 | #define mmUVD_CONTEXT_ID_BASE_IDX 1 |
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| 406 | #define mmUVD_CONTEXT_ID2 0x05bf |
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| 407 | #define mmUVD_CONTEXT_ID2_BASE_IDX 1 |
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| 408 | #define mmUVD_RBC_WPTR_POLL_CNTL 0x05d8 |
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| 409 | #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 |
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| 410 | #define mmUVD_RBC_WPTR_POLL_ADDR 0x05d9 |
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| 411 | #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 |
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| 412 | #define mmUVD_RB_BASE_LO4 0x05df |
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| 413 | #define mmUVD_RB_BASE_LO4_BASE_IDX 1 |
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| 414 | #define mmUVD_RB_BASE_HI4 0x05e0 |
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| 415 | #define mmUVD_RB_BASE_HI4_BASE_IDX 1 |
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| 416 | #define mmUVD_RB_SIZE4 0x05e1 |
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| 417 | #define mmUVD_RB_SIZE4_BASE_IDX 1 |
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| 418 | #define mmUVD_RB_RPTR4 0x05e2 |
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| 419 | #define mmUVD_RB_RPTR4_BASE_IDX 1 |
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| 420 | |
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| 421 | |
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| 422 | #endif |
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| 423 | |
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