| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _uvd_7_0_OFFSET_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | |
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| 26 | // addressBlock: uvd0_uvd_pg_dec |
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| 27 | // base address: 0x1fb00 |
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| 28 | #define mmUVD_POWER_STATUS 0x00c4 |
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| 29 | #define mmUVD_POWER_STATUS_BASE_IDX 1 |
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| 30 | #define mmUVD_DPG_RBC_RB_CNTL 0x00cb |
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| 31 | #define mmUVD_DPG_RBC_RB_CNTL_BASE_IDX 1 |
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| 32 | #define mmUVD_DPG_RBC_RB_BASE_LOW 0x00cc |
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| 33 | #define mmUVD_DPG_RBC_RB_BASE_LOW_BASE_IDX 1 |
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| 34 | #define mmUVD_DPG_RBC_RB_BASE_HIGH 0x00cd |
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| 35 | #define mmUVD_DPG_RBC_RB_BASE_HIGH_BASE_IDX 1 |
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| 36 | #define mmUVD_DPG_RBC_RB_WPTR_CNTL 0x00ce |
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| 37 | #define mmUVD_DPG_RBC_RB_WPTR_CNTL_BASE_IDX 1 |
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| 38 | #define mmUVD_DPG_RBC_RB_RPTR 0x00cf |
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| 39 | #define mmUVD_DPG_RBC_RB_RPTR_BASE_IDX 1 |
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| 40 | #define mmUVD_DPG_RBC_RB_WPTR 0x00d0 |
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| 41 | #define mmUVD_DPG_RBC_RB_WPTR_BASE_IDX 1 |
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| 42 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5 |
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| 43 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
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| 44 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6 |
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| 45 | #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 46 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7 |
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| 47 | #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
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| 48 | |
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| 49 | |
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| 50 | // addressBlock: uvd0_uvdnpdec |
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| 51 | // base address: 0x20000 |
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| 52 | #define mmUVD_JPEG_ADDR_CONFIG 0x021f |
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| 53 | #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 |
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| 54 | #define mmUVD_GPCOM_VCPU_CMD 0x03c3 |
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| 55 | #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 |
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| 56 | #define mmUVD_GPCOM_VCPU_DATA0 0x03c4 |
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| 57 | #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 |
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| 58 | #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 |
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| 59 | #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 |
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| 60 | #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 |
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| 61 | #define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1 |
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| 62 | #define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4 |
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| 63 | #define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1 |
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| 64 | #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 |
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| 65 | #define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1 |
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| 66 | #define mmUVD_SUVD_CGC_GATE 0x03e4 |
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| 67 | #define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 |
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| 68 | #define mmUVD_SUVD_CGC_CTRL 0x03e6 |
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| 69 | #define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 |
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| 70 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec |
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| 71 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 |
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| 72 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed |
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| 73 | #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 74 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0 |
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| 75 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 |
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| 76 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1 |
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| 77 | #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 78 | #define mmUVD_POWER_STATUS_U 0x03fd |
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| 79 | #define mmUVD_POWER_STATUS_U_BASE_IDX 1 |
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| 80 | #define mmUVD_NO_OP 0x03ff |
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| 81 | #define mmUVD_NO_OP_BASE_IDX 1 |
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| 82 | #define mmUVD_GP_SCRATCH8 0x040a |
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| 83 | #define mmUVD_GP_SCRATCH8_BASE_IDX 1 |
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| 84 | #define mmUVD_RB_BASE_LO2 0x0421 |
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| 85 | #define mmUVD_RB_BASE_LO2_BASE_IDX 1 |
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| 86 | #define mmUVD_RB_BASE_HI2 0x0422 |
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| 87 | #define mmUVD_RB_BASE_HI2_BASE_IDX 1 |
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| 88 | #define mmUVD_RB_SIZE2 0x0423 |
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| 89 | #define mmUVD_RB_SIZE2_BASE_IDX 1 |
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| 90 | #define mmUVD_RB_RPTR2 0x0424 |
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| 91 | #define mmUVD_RB_RPTR2_BASE_IDX 1 |
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| 92 | #define mmUVD_RB_WPTR2 0x0425 |
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| 93 | #define mmUVD_RB_WPTR2_BASE_IDX 1 |
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| 94 | #define mmUVD_RB_BASE_LO 0x0426 |
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| 95 | #define mmUVD_RB_BASE_LO_BASE_IDX 1 |
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| 96 | #define mmUVD_RB_BASE_HI 0x0427 |
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| 97 | #define mmUVD_RB_BASE_HI_BASE_IDX 1 |
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| 98 | #define mmUVD_RB_SIZE 0x0428 |
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| 99 | #define mmUVD_RB_SIZE_BASE_IDX 1 |
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| 100 | #define mmUVD_RB_RPTR 0x0429 |
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| 101 | #define mmUVD_RB_RPTR_BASE_IDX 1 |
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| 102 | #define mmUVD_RB_WPTR 0x042a |
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| 103 | #define mmUVD_RB_WPTR_BASE_IDX 1 |
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| 104 | #define mmUVD_JRBC_RB_RPTR 0x0457 |
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| 105 | #define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 |
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| 106 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e |
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| 107 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 108 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f |
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| 109 | #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
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| 110 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466 |
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| 111 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 112 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467 |
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| 113 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 114 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0468 |
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| 115 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
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| 116 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0469 |
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| 117 | #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 118 | |
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| 119 | |
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| 120 | // addressBlock: uvd0_uvddec |
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| 121 | // base address: 0x20c00 |
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| 122 | #define mmUVD_SEMA_CNTL 0x0500 |
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| 123 | #define mmUVD_SEMA_CNTL_BASE_IDX 1 |
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| 124 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 |
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| 125 | #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
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| 126 | #define mmUVD_JRBC_RB_WPTR 0x0509 |
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| 127 | #define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 |
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| 128 | #define mmUVD_RB_RPTR3 0x051b |
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| 129 | #define mmUVD_RB_RPTR3_BASE_IDX 1 |
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| 130 | #define mmUVD_RB_WPTR3 0x051c |
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| 131 | #define mmUVD_RB_WPTR3_BASE_IDX 1 |
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| 132 | #define mmUVD_RB_BASE_LO3 0x051d |
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| 133 | #define mmUVD_RB_BASE_LO3_BASE_IDX 1 |
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| 134 | #define mmUVD_RB_BASE_HI3 0x051e |
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| 135 | #define mmUVD_RB_BASE_HI3_BASE_IDX 1 |
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| 136 | #define mmUVD_RB_SIZE3 0x051f |
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| 137 | #define mmUVD_RB_SIZE3_BASE_IDX 1 |
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| 138 | #define mmJPEG_CGC_GATE 0x0526 |
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| 139 | #define mmJPEG_CGC_GATE_BASE_IDX 1 |
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| 140 | #define mmUVD_CTX_INDEX 0x0528 |
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| 141 | #define mmUVD_CTX_INDEX_BASE_IDX 1 |
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| 142 | #define mmUVD_CTX_DATA 0x0529 |
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| 143 | #define mmUVD_CTX_DATA_BASE_IDX 1 |
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| 144 | #define mmUVD_CGC_GATE 0x052a |
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| 145 | #define mmUVD_CGC_GATE_BASE_IDX 1 |
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| 146 | #define mmUVD_CGC_CTRL 0x052c |
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| 147 | #define mmUVD_CGC_CTRL_BASE_IDX 1 |
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| 148 | #define mmUVD_GP_SCRATCH4 0x0538 |
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| 149 | #define mmUVD_GP_SCRATCH4_BASE_IDX 1 |
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| 150 | #define mmUVD_LMI_CTRL2 0x053d |
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| 151 | #define mmUVD_LMI_CTRL2_BASE_IDX 1 |
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| 152 | #define mmUVD_MASTINT_EN 0x0540 |
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| 153 | #define mmUVD_MASTINT_EN_BASE_IDX 1 |
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| 154 | #define mmUVD_FW_STATUS 0x0557 |
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| 155 | #define mmUVD_FW_STATUS_BASE_IDX 1 |
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| 156 | #define mmJPEG_CGC_CTRL 0x0565 |
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| 157 | #define mmJPEG_CGC_CTRL_BASE_IDX 1 |
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| 158 | #define mmUVD_LMI_CTRL 0x0566 |
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| 159 | #define mmUVD_LMI_CTRL_BASE_IDX 1 |
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| 160 | #define mmUVD_LMI_VM_CTRL 0x0568 |
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| 161 | #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 |
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| 162 | #define mmUVD_LMI_SWAP_CNTL 0x056d |
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| 163 | #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 |
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| 164 | #define mmUVD_MP_SWAP_CNTL 0x056f |
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| 165 | #define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 |
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| 166 | #define mmUVD_MPC_SET_MUXA0 0x0579 |
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| 167 | #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 |
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| 168 | #define mmUVD_MPC_SET_MUXA1 0x057a |
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| 169 | #define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 |
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| 170 | #define mmUVD_MPC_SET_MUXB0 0x057b |
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| 171 | #define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 |
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| 172 | #define mmUVD_MPC_SET_MUXB1 0x057c |
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| 173 | #define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 |
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| 174 | #define mmUVD_MPC_SET_MUX 0x057d |
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| 175 | #define mmUVD_MPC_SET_MUX_BASE_IDX 1 |
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| 176 | #define mmUVD_MPC_SET_ALU 0x057e |
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| 177 | #define mmUVD_MPC_SET_ALU_BASE_IDX 1 |
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| 178 | #define mmUVD_VCPU_CACHE_OFFSET0 0x0582 |
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| 179 | #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
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| 180 | #define mmUVD_VCPU_CACHE_SIZE0 0x0583 |
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| 181 | #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 |
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| 182 | #define mmUVD_VCPU_CACHE_OFFSET1 0x0584 |
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| 183 | #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 |
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| 184 | #define mmUVD_VCPU_CACHE_SIZE1 0x0585 |
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| 185 | #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 |
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| 186 | #define mmUVD_VCPU_CACHE_OFFSET2 0x0586 |
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| 187 | #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 |
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| 188 | #define mmUVD_VCPU_CACHE_SIZE2 0x0587 |
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| 189 | #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 |
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| 190 | #define mmUVD_VCPU_CNTL 0x0598 |
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| 191 | #define mmUVD_VCPU_CNTL_BASE_IDX 1 |
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| 192 | #define mmUVD_SOFT_RESET 0x05a0 |
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| 193 | #define mmUVD_SOFT_RESET_BASE_IDX 1 |
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| 194 | #define mmUVD_LMI_RBC_IB_VMID 0x05a1 |
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| 195 | #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 |
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| 196 | #define mmUVD_RBC_IB_SIZE 0x05a2 |
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| 197 | #define mmUVD_RBC_IB_SIZE_BASE_IDX 1 |
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| 198 | #define mmUVD_RBC_RB_RPTR 0x05a4 |
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| 199 | #define mmUVD_RBC_RB_RPTR_BASE_IDX 1 |
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| 200 | #define mmUVD_RBC_RB_WPTR 0x05a5 |
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| 201 | #define mmUVD_RBC_RB_WPTR_BASE_IDX 1 |
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| 202 | #define mmUVD_RBC_RB_WPTR_CNTL 0x05a6 |
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| 203 | #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 |
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| 204 | #define mmUVD_RBC_RB_CNTL 0x05a9 |
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| 205 | #define mmUVD_RBC_RB_CNTL_BASE_IDX 1 |
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| 206 | #define mmUVD_RBC_RB_RPTR_ADDR 0x05aa |
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| 207 | #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 |
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| 208 | #define mmUVD_STATUS 0x05af |
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| 209 | #define mmUVD_STATUS_BASE_IDX 1 |
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| 210 | #define mmUVD_SEMA_TIMEOUT_STATUS 0x05b0 |
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| 211 | #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 |
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| 212 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x05b1 |
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| 213 | #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
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| 214 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2 |
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| 215 | #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 |
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| 216 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x05b3 |
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| 217 | #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 |
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| 218 | #define mmUVD_CONTEXT_ID 0x05bd |
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| 219 | #define mmUVD_CONTEXT_ID_BASE_IDX 1 |
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| 220 | #define mmUVD_CONTEXT_ID2 0x05bf |
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| 221 | #define mmUVD_CONTEXT_ID2_BASE_IDX 1 |
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| 222 | |
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| 223 | |
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| 224 | |
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| 225 | #endif |
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| 226 | |
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