1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _hdp_4_0_OFFSET_HEADER
22#define _hdp_4_0_OFFSET_HEADER
23
24
25
26// addressBlock: hdp_hdpdec
27// base address: 0x3c80
28#define mmHDP_MMHUB_TLVL 0x0000
29#define mmHDP_MMHUB_TLVL_BASE_IDX 0
30#define mmHDP_MMHUB_UNITID 0x0001
31#define mmHDP_MMHUB_UNITID_BASE_IDX 0
32#define mmHDP_NONSURFACE_BASE 0x0040
33#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
34#define mmHDP_NONSURFACE_INFO 0x0041
35#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
36#define mmHDP_NONSURFACE_BASE_HI 0x0042
37#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
38#define mmHDP_NONSURF_FLAGS 0x00c8
39#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
40#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
41#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
42#define mmHDP_HOST_PATH_CNTL 0x00cc
43#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
44#define mmHDP_SW_SEMAPHORE 0x00cd
45#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
46#define mmHDP_DEBUG0 0x00ce
47#define mmHDP_DEBUG0_BASE_IDX 0
48#define mmHDP_LAST_SURFACE_HIT 0x00d0
49#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
50#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
51#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
52#define mmHDP_OUTSTANDING_REQ 0x00d2
53#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
54#define mmHDP_MISC_CNTL 0x00d3
55#define mmHDP_MISC_CNTL_BASE_IDX 0
56#define mmHDP_MEM_POWER_LS 0x00d4
57#define mmHDP_MEM_POWER_LS_BASE_IDX 0
58#define mmHDP_MMHUB_CNTL 0x00d5
59#define mmHDP_MMHUB_CNTL_BASE_IDX 0
60#define mmHDP_EDC_CNT 0x00d6
61#define mmHDP_EDC_CNT_BASE_IDX 0
62#define mmHDP_VERSION 0x00d7
63#define mmHDP_VERSION_BASE_IDX 0
64#define mmHDP_CLK_CNTL 0x00d8
65#define mmHDP_CLK_CNTL_BASE_IDX 0
66#define mmHDP_MEMIO_CNTL 0x00f6
67#define mmHDP_MEMIO_CNTL_BASE_IDX 0
68#define mmHDP_MEMIO_ADDR 0x00f7
69#define mmHDP_MEMIO_ADDR_BASE_IDX 0
70#define mmHDP_MEMIO_STATUS 0x00f8
71#define mmHDP_MEMIO_STATUS_BASE_IDX 0
72#define mmHDP_MEMIO_WR_DATA 0x00f9
73#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
74#define mmHDP_MEMIO_RD_DATA 0x00fa
75#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
76#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
77#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
78#define mmHDP_XDP_D2H_FLUSH 0x0101
79#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
80#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
81#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
82#define mmHDP_XDP_D2H_RSVD_3 0x0103
83#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
84#define mmHDP_XDP_D2H_RSVD_4 0x0104
85#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
86#define mmHDP_XDP_D2H_RSVD_5 0x0105
87#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
88#define mmHDP_XDP_D2H_RSVD_6 0x0106
89#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
90#define mmHDP_XDP_D2H_RSVD_7 0x0107
91#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
92#define mmHDP_XDP_D2H_RSVD_8 0x0108
93#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
94#define mmHDP_XDP_D2H_RSVD_9 0x0109
95#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
96#define mmHDP_XDP_D2H_RSVD_10 0x010a
97#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
98#define mmHDP_XDP_D2H_RSVD_11 0x010b
99#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
100#define mmHDP_XDP_D2H_RSVD_12 0x010c
101#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
102#define mmHDP_XDP_D2H_RSVD_13 0x010d
103#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
104#define mmHDP_XDP_D2H_RSVD_14 0x010e
105#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0
106#define mmHDP_XDP_D2H_RSVD_15 0x010f
107#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0
108#define mmHDP_XDP_D2H_RSVD_16 0x0110
109#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0
110#define mmHDP_XDP_D2H_RSVD_17 0x0111
111#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0
112#define mmHDP_XDP_D2H_RSVD_18 0x0112
113#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0
114#define mmHDP_XDP_D2H_RSVD_19 0x0113
115#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0
116#define mmHDP_XDP_D2H_RSVD_20 0x0114
117#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0
118#define mmHDP_XDP_D2H_RSVD_21 0x0115
119#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0
120#define mmHDP_XDP_D2H_RSVD_22 0x0116
121#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0
122#define mmHDP_XDP_D2H_RSVD_23 0x0117
123#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0
124#define mmHDP_XDP_D2H_RSVD_24 0x0118
125#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0
126#define mmHDP_XDP_D2H_RSVD_25 0x0119
127#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0
128#define mmHDP_XDP_D2H_RSVD_26 0x011a
129#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0
130#define mmHDP_XDP_D2H_RSVD_27 0x011b
131#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0
132#define mmHDP_XDP_D2H_RSVD_28 0x011c
133#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0
134#define mmHDP_XDP_D2H_RSVD_29 0x011d
135#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0
136#define mmHDP_XDP_D2H_RSVD_30 0x011e
137#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0
138#define mmHDP_XDP_D2H_RSVD_31 0x011f
139#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0
140#define mmHDP_XDP_D2H_RSVD_32 0x0120
141#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0
142#define mmHDP_XDP_D2H_RSVD_33 0x0121
143#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0
144#define mmHDP_XDP_D2H_RSVD_34 0x0122
145#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0
146#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123
147#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
148#define mmHDP_XDP_P2P_BAR_CFG 0x0124
149#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
150#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125
151#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
152#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126
153#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
154#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127
155#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
156#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128
157#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
158#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129
159#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
160#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a
161#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
162#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b
163#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
164#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c
165#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
166#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d
167#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
168#define mmHDP_XDP_HDP_MC_CFG 0x012e
169#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0
170#define mmHDP_XDP_HST_CFG 0x012f
171#define mmHDP_XDP_HST_CFG_BASE_IDX 0
172#define mmHDP_XDP_HDP_IPH_CFG 0x0131
173#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
174#define mmHDP_XDP_P2P_BAR0 0x0134
175#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0
176#define mmHDP_XDP_P2P_BAR1 0x0135
177#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0
178#define mmHDP_XDP_P2P_BAR2 0x0136
179#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0
180#define mmHDP_XDP_P2P_BAR3 0x0137
181#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0
182#define mmHDP_XDP_P2P_BAR4 0x0138
183#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0
184#define mmHDP_XDP_P2P_BAR5 0x0139
185#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0
186#define mmHDP_XDP_P2P_BAR6 0x013a
187#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0
188#define mmHDP_XDP_P2P_BAR7 0x013b
189#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0
190#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c
191#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
192#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d
193#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
194#define mmHDP_XDP_BUSY_STS 0x013e
195#define mmHDP_XDP_BUSY_STS_BASE_IDX 0
196#define mmHDP_XDP_STICKY 0x013f
197#define mmHDP_XDP_STICKY_BASE_IDX 0
198#define mmHDP_XDP_CHKN 0x0140
199#define mmHDP_XDP_CHKN_BASE_IDX 0
200#define mmHDP_XDP_BARS_ADDR_39_36 0x0144
201#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
202#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
203#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
204#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
205#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
206#define mmHDP_XDP_MMHUB_ERROR 0x0149
207#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0
208
209#endif
210

source code of linux/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h