1	/*
2	* DCE_11_0 Register documentation
3	*
4	* Copyright (C) 2014 Advanced Micro Devices, Inc.
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included
14	* in all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22	*/
23
24	#ifndef DCE_11_0_ENUM_H
25	#define DCE_11_0_ENUM_H
26
27	typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
28	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
29	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
30	} CRTC_CONTROL_CRTC_START_POINT_CNTL;
31	typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
32	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
33	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
34	} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
35	typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
36	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
37	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
38	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
39	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
40	} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
41	typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
42	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
43	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
44	} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
45	typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
46	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
47	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
48	} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
49	typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
50	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0,
51	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
52	} CRTC_CONTROL_CRTC_SOF_PULL_EN;
53	typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
54	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0,
55	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
56	} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
57	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
58	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0,
59	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
60	} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
61	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
62	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0,
63	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
64	} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
65	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
66	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
67	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
68	} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
69	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
70	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
71	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
72	} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
73	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
74	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
75	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
76	} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
77	typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
78	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
79	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
80	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
81	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
82	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
83	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
84	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
85	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
86	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
87	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
88	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
89	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
90	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
91	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
92	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
93	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
94	} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
95	typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
96	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
97	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
98	} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
99	typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
100	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
101	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
102	} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
103	typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
104	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0,
105	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1,
106	} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
107	typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
108	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0,
109	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1,
110	} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
111	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
112	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
113	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
114	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
115	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
116	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7,
117	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8,
118	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9,
119	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa,
120	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb,
121	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc,
122	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
123	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
124	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO = 0xf,
125	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10,
126	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11,
127	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12,
128	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13,
129	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
130	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
131	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
132	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
133	} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
134	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
135	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
136	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
137	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
138	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
139	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
140	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
141	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
142	} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
143	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
144	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
145	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
146	} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
147	typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
148	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0,
149	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1,
150	} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
151	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
152	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
153	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
154	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
155	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
156	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7,
157	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8,
158	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9,
159	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa,
160	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb,
161	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc,
162	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
163	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
164	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO = 0xf,
165	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10,
166	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11,
167	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12,
168	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13,
169	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
170	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
171	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
172	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
173	} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
174	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
175	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
176	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
177	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
178	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
179	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
180	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
181	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
182	} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
183	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
184	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
185	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
186	} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
187	typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
188	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0,
189	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1,
190	} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
191	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
192	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
193	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
194	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
195	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
196	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
197	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
198	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
199	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
200	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
201	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
202	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
203	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
204	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
205	typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
206	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
207	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
208	} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
209	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
210	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
211	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
212	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
213	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
214	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
215	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
216	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
217	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
218	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
219	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
220	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
221	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
222	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
223	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
224	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
225	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
226	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
227	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
228	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
229	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
230	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
231	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
232	typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
233	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
234	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
235	} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
236	typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
237	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
238	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
239	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
240	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
241	} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
242	typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
243	CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0,
244	CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1,
245	} CRTC_CONTROL_CRTC_MASTER_EN;
246	typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
247	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0,
248	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1,
249	} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
250	typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
251	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0,
252	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1,
253	} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
254	typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
255	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
256	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
257	} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
258	typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
259	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
260	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
261	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
262	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
263	} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
264	typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
265	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
266	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
267	} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
268	typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
269	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
270	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
271	} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
272	typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
273	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0,
274	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1,
275	} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
276	typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
277	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
278	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
279	} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
280	typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
281	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
282	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
283	} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
284	typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
285	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
286	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
287	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
288	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
289	} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
290	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
291	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
292	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
293	} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
294	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
295	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
296	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
297	} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
298	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
299	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
300	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
301	} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
302	typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
303	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0,
304	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1,
305	} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
306	typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
307	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0,
308	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1,
309	} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
310	typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
311	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
312	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
313	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
314	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
315	} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
316	typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
317	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
318	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
319	} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
320	typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
321	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
322	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
323	} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
324	typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
325	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
326	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
327	} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
328	typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
329	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0,
330	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1,
331	} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
332	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
333	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
334	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
335	} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
336	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
337	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
338	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
339	} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
340	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
341	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
342	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
343	} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
344	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
345	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
346	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
347	} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
348	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
349	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
350	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
351	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
352	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
353	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
354	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
355	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
356	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
357	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
358	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
359	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
360	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
361	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
362	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
363	} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
364	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
365	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0,
366	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1,
367	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
368	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
369	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
370	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1,
371	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
372	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
373	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0,
374	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1,
375	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
376	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
377	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
378	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1,
379	} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
380	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
381	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
382	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
383	} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
384	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
385	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
386	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
387	} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
388	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
389	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
390	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
391	} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
392	typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
393	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
394	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
395	} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
396	typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
397	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0,
398	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1,
399	} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
400	typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
401	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
402	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
403	} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
404	typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
405	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
406	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
407	} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
408	typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
409	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
410	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
411	} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
412	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
413	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
414	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
415	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
416	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
417	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
418	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
419	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
420	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
421	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
422	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
423	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
424	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
425	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
426	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
427	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
428	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
429	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
430	typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
431	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
432	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
433	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
434	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
435	} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
436	typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
437	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0,
438	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1,
439	} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
440	typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
441	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
442	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
443	} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
444	typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
445	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0,
446	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1,
447	} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
448	typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
449	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0,
450	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1,
451	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2,
452	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3,
453	} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
454	typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
455	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
456	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
457	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
458	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
459	} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
460	typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
461	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
462	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
463	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
464	} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
465	typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
466	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0,
467	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1,
468	} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
469	typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
470	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
471	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
472	} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
473	typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
474	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
475	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
476	} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
477	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
478	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
479	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
480	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
481	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
482	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
483	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
484	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
485	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
486	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
487	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
488	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
489	typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
490	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
491	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
492	} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
493	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
494	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
495	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
496	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
497	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
498	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
499	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
500	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
501	typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
502	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
503	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
504	} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
505	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
506	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
507	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
508	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
509	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
510	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
511	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
512	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
513	typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
514	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
515	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
516	} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
517	typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
518	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0,
519	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1,
520	} CRTC_CRC_CNTL_CRTC_CRC_EN;
521	typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
522	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0,
523	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1,
524	} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
525	typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
526	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0,
527	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1,
528	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2,
529	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3,
530	} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
531	typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
532	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0,
533	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1,
534	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
535	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
536	} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
537	typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
538	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
539	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
540	} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
541	typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
542	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0,
543	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1,
544	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2,
545	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3,
546	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4,
547	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5,
548	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6,
549	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7,
550	} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
551	typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
552	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0,
553	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1,
554	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2,
555	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3,
556	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4,
557	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5,
558	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6,
559	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7,
560	} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
561	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
562	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
563	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
564	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
565	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
566	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
567	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
568	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
569	typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
570	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
571	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
572	} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
573	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
574	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
575	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
576	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
577	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
578	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
579	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
580	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
581	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
582	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
583	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
584	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
585	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
586	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
587	typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
588	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
589	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
590	} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
591	typedef enum CRTC_V_SYNC_A_POL {
592	CRTC_V_SYNC_A_POL_HIGH = 0x0,
593	CRTC_V_SYNC_A_POL_LOW = 0x1,
594	} CRTC_V_SYNC_A_POL;
595	typedef enum CRTC_H_SYNC_A_POL {
596	CRTC_H_SYNC_A_POL_HIGH = 0x0,
597	CRTC_H_SYNC_A_POL_LOW = 0x1,
598	} CRTC_H_SYNC_A_POL;
599	typedef enum CRTC_HORZ_REPETITION_COUNT {
600	CRTC_HORZ_REPETITION_COUNT_0 = 0x0,
601	CRTC_HORZ_REPETITION_COUNT_1 = 0x1,
602	CRTC_HORZ_REPETITION_COUNT_2 = 0x2,
603	CRTC_HORZ_REPETITION_COUNT_3 = 0x3,
604	CRTC_HORZ_REPETITION_COUNT_4 = 0x4,
605	CRTC_HORZ_REPETITION_COUNT_5 = 0x5,
606	CRTC_HORZ_REPETITION_COUNT_6 = 0x6,
607	CRTC_HORZ_REPETITION_COUNT_7 = 0x7,
608	CRTC_HORZ_REPETITION_COUNT_8 = 0x8,
609	CRTC_HORZ_REPETITION_COUNT_9 = 0x9,
610	CRTC_HORZ_REPETITION_COUNT_10 = 0xa,
611	CRTC_HORZ_REPETITION_COUNT_11 = 0xb,
612	CRTC_HORZ_REPETITION_COUNT_12 = 0xc,
613	CRTC_HORZ_REPETITION_COUNT_13 = 0xd,
614	CRTC_HORZ_REPETITION_COUNT_14 = 0xe,
615	CRTC_HORZ_REPETITION_COUNT_15 = 0xf,
616	} CRTC_HORZ_REPETITION_COUNT;
617	typedef enum PERFCOUNTER_CVALUE_SEL {
618	PERFCOUNTER_CVALUE_SEL_47_0 = 0x0,
619	PERFCOUNTER_CVALUE_SEL_15_0 = 0x1,
620	PERFCOUNTER_CVALUE_SEL_31_16 = 0x2,
621	PERFCOUNTER_CVALUE_SEL_47_32 = 0x3,
622	PERFCOUNTER_CVALUE_SEL_11_0 = 0x4,
623	PERFCOUNTER_CVALUE_SEL_23_12 = 0x5,
624	PERFCOUNTER_CVALUE_SEL_35_24 = 0x6,
625	PERFCOUNTER_CVALUE_SEL_47_36 = 0x7,
626	} PERFCOUNTER_CVALUE_SEL;
627	typedef enum PERFCOUNTER_INC_MODE {
628	PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0,
629	PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1,
630	PERFCOUNTER_INC_MODE_LSB = 0x2,
631	PERFCOUNTER_INC_MODE_POS_EDGE = 0x3,
632	} PERFCOUNTER_INC_MODE;
633	typedef enum PERFCOUNTER_HW_CNTL_SEL {
634	PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0,
635	PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1,
636	} PERFCOUNTER_HW_CNTL_SEL;
637	typedef enum PERFCOUNTER_RUNEN_MODE {
638	PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0,
639	PERFCOUNTER_RUNEN_MODE_EDGE = 0x1,
640	} PERFCOUNTER_RUNEN_MODE;
641	typedef enum PERFCOUNTER_CNTOFF_START_DIS {
642	PERFCOUNTER_CNTOFF_START_ENABLE = 0x0,
643	PERFCOUNTER_CNTOFF_START_DISABLE = 0x1,
644	} PERFCOUNTER_CNTOFF_START_DIS;
645	typedef enum PERFCOUNTER_RESTART_EN {
646	PERFCOUNTER_RESTART_DISABLE = 0x0,
647	PERFCOUNTER_RESTART_ENABLE = 0x1,
648	} PERFCOUNTER_RESTART_EN;
649	typedef enum PERFCOUNTER_INT_EN {
650	PERFCOUNTER_INT_DISABLE = 0x0,
651	PERFCOUNTER_INT_ENABLE = 0x1,
652	} PERFCOUNTER_INT_EN;
653	typedef enum PERFCOUNTER_OFF_MASK {
654	PERFCOUNTER_OFF_MASK_DISABLE = 0x0,
655	PERFCOUNTER_OFF_MASK_ENABLE = 0x1,
656	} PERFCOUNTER_OFF_MASK;
657	typedef enum PERFCOUNTER_ACTIVE {
658	PERFCOUNTER_IS_IDLE = 0x0,
659	PERFCOUNTER_IS_ACTIVE = 0x1,
660	} PERFCOUNTER_ACTIVE;
661	typedef enum PERFCOUNTER_INT_TYPE {
662	PERFCOUNTER_INT_TYPE_LEVEL = 0x0,
663	PERFCOUNTER_INT_TYPE_PULSE = 0x1,
664	} PERFCOUNTER_INT_TYPE;
665	typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
666	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0,
667	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1,
668	} PERFCOUNTER_COUNTED_VALUE_TYPE;
669	typedef enum PERFCOUNTER_CNTL_SEL {
670	PERFCOUNTER_CNTL_SEL_0 = 0x0,
671	PERFCOUNTER_CNTL_SEL_1 = 0x1,
672	PERFCOUNTER_CNTL_SEL_2 = 0x2,
673	PERFCOUNTER_CNTL_SEL_3 = 0x3,
674	PERFCOUNTER_CNTL_SEL_4 = 0x4,
675	PERFCOUNTER_CNTL_SEL_5 = 0x5,
676	PERFCOUNTER_CNTL_SEL_6 = 0x6,
677	PERFCOUNTER_CNTL_SEL_7 = 0x7,
678	} PERFCOUNTER_CNTL_SEL;
679	typedef enum PERFCOUNTER_CNT0_STATE {
680	PERFCOUNTER_CNT0_STATE_RESET = 0x0,
681	PERFCOUNTER_CNT0_STATE_START = 0x1,
682	PERFCOUNTER_CNT0_STATE_FREEZE = 0x2,
683	PERFCOUNTER_CNT0_STATE_HW = 0x3,
684	} PERFCOUNTER_CNT0_STATE;
685	typedef enum PERFCOUNTER_STATE_SEL0 {
686	PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0,
687	PERFCOUNTER_STATE_SEL0_LOCAL = 0x1,
688	} PERFCOUNTER_STATE_SEL0;
689	typedef enum PERFCOUNTER_CNT1_STATE {
690	PERFCOUNTER_CNT1_STATE_RESET = 0x0,
691	PERFCOUNTER_CNT1_STATE_START = 0x1,
692	PERFCOUNTER_CNT1_STATE_FREEZE = 0x2,
693	PERFCOUNTER_CNT1_STATE_HW = 0x3,
694	} PERFCOUNTER_CNT1_STATE;
695	typedef enum PERFCOUNTER_STATE_SEL1 {
696	PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0,
697	PERFCOUNTER_STATE_SEL1_LOCAL = 0x1,
698	} PERFCOUNTER_STATE_SEL1;
699	typedef enum PERFCOUNTER_CNT2_STATE {
700	PERFCOUNTER_CNT2_STATE_RESET = 0x0,
701	PERFCOUNTER_CNT2_STATE_START = 0x1,
702	PERFCOUNTER_CNT2_STATE_FREEZE = 0x2,
703	PERFCOUNTER_CNT2_STATE_HW = 0x3,
704	} PERFCOUNTER_CNT2_STATE;
705	typedef enum PERFCOUNTER_STATE_SEL2 {
706	PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0,
707	PERFCOUNTER_STATE_SEL2_LOCAL = 0x1,
708	} PERFCOUNTER_STATE_SEL2;
709	typedef enum PERFCOUNTER_CNT3_STATE {
710	PERFCOUNTER_CNT3_STATE_RESET = 0x0,
711	PERFCOUNTER_CNT3_STATE_START = 0x1,
712	PERFCOUNTER_CNT3_STATE_FREEZE = 0x2,
713	PERFCOUNTER_CNT3_STATE_HW = 0x3,
714	} PERFCOUNTER_CNT3_STATE;
715	typedef enum PERFCOUNTER_STATE_SEL3 {
716	PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0,
717	PERFCOUNTER_STATE_SEL3_LOCAL = 0x1,
718	} PERFCOUNTER_STATE_SEL3;
719	typedef enum PERFCOUNTER_CNT4_STATE {
720	PERFCOUNTER_CNT4_STATE_RESET = 0x0,
721	PERFCOUNTER_CNT4_STATE_START = 0x1,
722	PERFCOUNTER_CNT4_STATE_FREEZE = 0x2,
723	PERFCOUNTER_CNT4_STATE_HW = 0x3,
724	} PERFCOUNTER_CNT4_STATE;
725	typedef enum PERFCOUNTER_STATE_SEL4 {
726	PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0,
727	PERFCOUNTER_STATE_SEL4_LOCAL = 0x1,
728	} PERFCOUNTER_STATE_SEL4;
729	typedef enum PERFCOUNTER_CNT5_STATE {
730	PERFCOUNTER_CNT5_STATE_RESET = 0x0,
731	PERFCOUNTER_CNT5_STATE_START = 0x1,
732	PERFCOUNTER_CNT5_STATE_FREEZE = 0x2,
733	PERFCOUNTER_CNT5_STATE_HW = 0x3,
734	} PERFCOUNTER_CNT5_STATE;
735	typedef enum PERFCOUNTER_STATE_SEL5 {
736	PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0,
737	PERFCOUNTER_STATE_SEL5_LOCAL = 0x1,
738	} PERFCOUNTER_STATE_SEL5;
739	typedef enum PERFCOUNTER_CNT6_STATE {
740	PERFCOUNTER_CNT6_STATE_RESET = 0x0,
741	PERFCOUNTER_CNT6_STATE_START = 0x1,
742	PERFCOUNTER_CNT6_STATE_FREEZE = 0x2,
743	PERFCOUNTER_CNT6_STATE_HW = 0x3,
744	} PERFCOUNTER_CNT6_STATE;
745	typedef enum PERFCOUNTER_STATE_SEL6 {
746	PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0,
747	PERFCOUNTER_STATE_SEL6_LOCAL = 0x1,
748	} PERFCOUNTER_STATE_SEL6;
749	typedef enum PERFCOUNTER_CNT7_STATE {
750	PERFCOUNTER_CNT7_STATE_RESET = 0x0,
751	PERFCOUNTER_CNT7_STATE_START = 0x1,
752	PERFCOUNTER_CNT7_STATE_FREEZE = 0x2,
753	PERFCOUNTER_CNT7_STATE_HW = 0x3,
754	} PERFCOUNTER_CNT7_STATE;
755	typedef enum PERFCOUNTER_STATE_SEL7 {
756	PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0,
757	PERFCOUNTER_STATE_SEL7_LOCAL = 0x1,
758	} PERFCOUNTER_STATE_SEL7;
759	typedef enum PERFMON_STATE {
760	PERFMON_STATE_RESET = 0x0,
761	PERFMON_STATE_START = 0x1,
762	PERFMON_STATE_FREEZE = 0x2,
763	PERFMON_STATE_HW = 0x3,
764	} PERFMON_STATE;
765	typedef enum PERFMON_CNTOFF_AND_OR {
766	PERFMON_CNTOFF_OR = 0x0,
767	PERFMON_CNTOFF_AND = 0x1,
768	} PERFMON_CNTOFF_AND_OR;
769	typedef enum PERFMON_CNTOFF_INT_EN {
770	PERFMON_CNTOFF_INT_DISABLE = 0x0,
771	PERFMON_CNTOFF_INT_ENABLE = 0x1,
772	} PERFMON_CNTOFF_INT_EN;
773	typedef enum PERFMON_CNTOFF_INT_TYPE {
774	PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0,
775	PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1,
776	} PERFMON_CNTOFF_INT_TYPE;
777	typedef enum LptNumBanks {
778	LPT_NUM_BANKS_2BANK = 0x0,
779	LPT_NUM_BANKS_4BANK = 0x1,
780	LPT_NUM_BANKS_8BANK = 0x2,
781	LPT_NUM_BANKS_16BANK = 0x3,
782	LPT_NUM_BANKS_32BANK = 0x4,
783	} LptNumBanks;
784	typedef enum DCIO_DC_GENERICA_SEL {
785	DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
786	DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
787	DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
788	DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
789	DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
790	DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
791	DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
792	DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
793	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
794	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
795	DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
796	DCIO_GENERICA_SEL_SYNCEN = 0xb,
797	DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
798	DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
799	DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
800	DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
801	DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
802	DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
803	} DCIO_DC_GENERICA_SEL;
804	typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
805	DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
806	DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
807	DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
808	DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
809	DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
810	DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
811	DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6,
812	DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7,
813	DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8,
814	} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
815	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
816	DCIO_UNIPHYA_FBDIV_CLK = 0x0,
817	DCIO_UNIPHYB_FBDIV_CLK = 0x1,
818	DCIO_UNIPHYC_FBDIV_CLK = 0x2,
819	DCIO_UNIPHYD_FBDIV_CLK = 0x3,
820	DCIO_UNIPHYE_FBDIV_CLK = 0x4,
821	DCIO_UNIPHYF_FBDIV_CLK = 0x5,
822	DCIO_UNIPHYG_FBDIV_CLK = 0x6,
823	DCIO_UNIPHYLPA_FBDIV_CLK = 0x7,
824	DCIO_UNIPHYLPB_FBDIV_CLK = 0x8,
825	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
826	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
827	DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
828	DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
829	DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
830	DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
831	DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
832	DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
833	DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6,
834	DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7,
835	DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8,
836	} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
837	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
838	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
839	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
840	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
841	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
842	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
843	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
844	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6,
845	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7,
846	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8,
847	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
848	typedef enum DCIO_DC_GENERICB_SEL {
849	DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
850	DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
851	DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
852	DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
853	DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
854	DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
855	DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
856	DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
857	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
858	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
859	DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
860	DCIO_GENERICB_SEL_SYNCEN = 0xb,
861	DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
862	DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
863	DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
864	DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
865	} DCIO_DC_GENERICB_SEL;
866	typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
867	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
868	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
869	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
870	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
871	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
872	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
873	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
874	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
875	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
876	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
877	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
878	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
879	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
880	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
881	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
882	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
883	} DCIO_DC_PAD_EXTERN_SIG_SEL;
884	typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
885	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
886	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
887	DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
888	DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
889	} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
890	typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
891	DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
892	DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
893	DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
894	DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
895	} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
896	typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
897	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
898	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
899	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
900	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
901	} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
902	typedef enum DCIO_DC_GPIO_VIP_DEBUG {
903	DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
904	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
905	} DCIO_DC_GPIO_VIP_DEBUG;
906	typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
907	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
908	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
909	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
910	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
911	} DCIO_DC_GPIO_MACRO_DEBUG;
912	typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
913	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
914	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
915	} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
916	typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
917	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
918	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
919	} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
920	typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
921	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
922	DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
923	} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
924	typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
925	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
926	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
927	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
928	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
929	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
930	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
931	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
932	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
933	} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
934	typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
935	DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
936	DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
937	} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
938	typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
939	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
940	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
941	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
942	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
943	} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
944	typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
945	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
946	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
947	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
948	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
949	} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
950	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
951	DCIO_VIP_MUX_EN_DVO = 0x0,
952	DCIO_VIP_MUX_EN_VIP = 0x1,
953	} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
954	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
955	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
956	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
957	} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
958	typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
959	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
960	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
961	} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
962	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
963	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
964	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
965	} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
966	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
967	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
968	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
969	} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
970	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
971	DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
972	DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
973	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
974	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
975	DCIO_LVTMA_DIGON_OFF = 0x0,
976	DCIO_LVTMA_DIGON_ON = 0x1,
977	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
978	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
979	DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
980	DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
981	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
982	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
983	DCIO_LVTMA_BLON_OFF = 0x0,
984	DCIO_LVTMA_BLON_ON = 0x1,
985	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
986	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
987	DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
988	DCIO_LVTMA_BLON_POL_INVERT = 0x1,
989	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
990	typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
991	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
992	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
993	} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
994	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
995	DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
996	DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
997	} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
998	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
999	DCIO_BL_PWM_DISABLE = 0x0,
1000	DCIO_BL_PWM_ENABLE = 0x1,
1001	} DCIO_BL_PWM_CNTL_BL_PWM_EN;
1002	typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
1003	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
1004	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
1005	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
1006	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
1007	} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
1008	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
1009	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
1010	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
1011	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
1012	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
1013	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
1014	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
1015	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
1016	typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
1017	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
1018	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
1019	} DCIO_BL_PWM_GRP1_REG_LOCK;
1020	typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
1021	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
1022	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
1023	} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
1024	typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
1025	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
1026	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
1027	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
1028	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
1029	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
1030	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
1031	} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
1032	typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
1033	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
1034	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
1035	} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
1036	typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
1037	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
1038	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
1039	} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
1040	typedef enum DCIO_GSL_SEL {
1041	DCIO_GSL_SEL_GROUP_0 = 0x0,
1042	DCIO_GSL_SEL_GROUP_1 = 0x1,
1043	DCIO_GSL_SEL_GROUP_2 = 0x2,
1044	} DCIO_GSL_SEL;
1045	typedef enum DCIO_GENLK_CLK_GSL_MASK {
1046	DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
1047	DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
1048	DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
1049	} DCIO_GENLK_CLK_GSL_MASK;
1050	typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
1051	DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
1052	DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
1053	DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
1054	} DCIO_GENLK_VSYNC_GSL_MASK;
1055	typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
1056	DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
1057	DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
1058	DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
1059	} DCIO_SWAPLOCK_A_GSL_MASK;
1060	typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
1061	DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
1062	DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
1063	DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
1064	} DCIO_SWAPLOCK_B_GSL_MASK;
1065	typedef enum DCIO_GSL_VSYNC_SEL {
1066	DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
1067	DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
1068	DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
1069	DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
1070	DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
1071	DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
1072	} DCIO_GSL_VSYNC_SEL;
1073	typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
1074	DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
1075	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
1076	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1077	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
1078	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
1079	} DCIO_GSL0_TIMING_SYNC_SEL;
1080	typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
1081	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
1082	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
1083	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1084	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
1085	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
1086	} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
1087	typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
1088	DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
1089	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
1090	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1091	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
1092	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
1093	} DCIO_GSL1_TIMING_SYNC_SEL;
1094	typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
1095	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
1096	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
1097	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1098	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
1099	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
1100	} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
1101	typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
1102	DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
1103	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
1104	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
1105	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
1106	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
1107	} DCIO_GSL2_TIMING_SYNC_SEL;
1108	typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
1109	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
1110	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
1111	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
1112	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
1113	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
1114	} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
1115	typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
1116	DCIO_GPU_TIMER_START_0_END_27 = 0x0,
1117	DCIO_GPU_TIMER_START_1_END_28 = 0x1,
1118	DCIO_GPU_TIMER_START_2_END_29 = 0x2,
1119	DCIO_GPU_TIMER_START_3_END_30 = 0x3,
1120	DCIO_GPU_TIMER_START_4_END_31 = 0x4,
1121	DCIO_GPU_TIMER_START_6_END_33 = 0x5,
1122	DCIO_GPU_TIMER_START_8_END_35 = 0x6,
1123	DCIO_GPU_TIMER_START_10_END_37 = 0x7,
1124	} DCIO_DC_GPU_TIMER_START_POSITION;
1125	typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
1126	DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
1127	DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
1128	DCIO_TEST_CLK_SEL_SCLK = 0x2,
1129	} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
1130	typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
1131	DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
1132	DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
1133	} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
1134	typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
1135	DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
1136	DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
1137	DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
1138	DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
1139	DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
1140	DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
1141	DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
1142	DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
1143	} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
1144	typedef enum DCIO_DCO_EXT_VSYNC_MASK {
1145	DCIO_EXT_VSYNC_MASK_NONE = 0x0,
1146	DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
1147	DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
1148	DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
1149	DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
1150	DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
1151	DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
1152	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
1153	} DCIO_DCO_EXT_VSYNC_MASK;
1154	typedef enum DCIO_DBG_OUT_PIN_SEL {
1155	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
1156	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
1157	} DCIO_DBG_OUT_PIN_SEL;
1158	typedef enum DCIO_DBG_OUT_12BIT_SEL {
1159	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
1160	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
1161	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
1162	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
1163	} DCIO_DBG_OUT_12BIT_SEL;
1164	typedef enum DCIO_DSYNC_SOFT_RESET {
1165	DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
1166	DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
1167	} DCIO_DSYNC_SOFT_RESET;
1168	typedef enum DCIO_DACA_SOFT_RESET {
1169	DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
1170	DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
1171	} DCIO_DACA_SOFT_RESET;
1172	typedef enum DCIO_DCRXPHY_SOFT_RESET {
1173	DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
1174	DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
1175	} DCIO_DCRXPHY_SOFT_RESET;
1176	typedef enum DCIO_DPHY_LANE_SEL {
1177	DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
1178	DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
1179	DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
1180	DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
1181	} DCIO_DPHY_LANE_SEL;
1182	typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
1183	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
1184	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
1185	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
1186	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
1187	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
1188	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
1189	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
1190	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
1191	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
1192	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
1193	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
1194	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
1195	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
1196	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
1197	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
1198	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
1199	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
1200	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
1201	DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP = 0x24,
1202	DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP = 0x25,
1203	} DCIO_DC_GPU_TIMER_READ_SELECT;
1204	typedef enum DCIO_IMPCAL_STEP_DELAY {
1205	DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
1206	DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
1207	DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
1208	DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
1209	DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
1210	DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
1211	DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
1212	DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
1213	DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
1214	DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
1215	DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
1216	DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
1217	DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
1218	DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
1219	DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
1220	DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
1221	} DCIO_IMPCAL_STEP_DELAY;
1222	typedef enum DCIO_UNIPHY_IMPCAL_SEL {
1223	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
1224	DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
1225	} DCIO_UNIPHY_IMPCAL_SEL;
1226	typedef enum DCIOCHIP_HPD_SEL {
1227	DCIOCHIP_HPD_SEL_ASYNC = 0x0,
1228	DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
1229	} DCIOCHIP_HPD_SEL;
1230	typedef enum DCIOCHIP_PAD_MODE {
1231	DCIOCHIP_PAD_MODE_DDC = 0x0,
1232	DCIOCHIP_PAD_MODE_DP = 0x1,
1233	} DCIOCHIP_PAD_MODE;
1234	typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
1235	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
1236	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
1237	} DCIOCHIP_AUXSLAVE_PAD_MODE;
1238	typedef enum DCIOCHIP_INVERT {
1239	DCIOCHIP_POL_NON_INVERT = 0x0,
1240	DCIOCHIP_POL_INVERT = 0x1,
1241	} DCIOCHIP_INVERT;
1242	typedef enum DCIOCHIP_PD_EN {
1243	DCIOCHIP_PD_EN_NOTALLOW = 0x0,
1244	DCIOCHIP_PD_EN_ALLOW = 0x1,
1245	} DCIOCHIP_PD_EN;
1246	typedef enum DCIOCHIP_GPIO_MASK_EN {
1247	DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
1248	DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
1249	} DCIOCHIP_GPIO_MASK_EN;
1250	typedef enum DCIOCHIP_MASK {
1251	DCIOCHIP_MASK_DISABLE = 0x0,
1252	DCIOCHIP_MASK_ENABLE = 0x1,
1253	} DCIOCHIP_MASK;
1254	typedef enum DCIOCHIP_GPIO_I2C_MASK {
1255	DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
1256	DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
1257	} DCIOCHIP_GPIO_I2C_MASK;
1258	typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
1259	DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
1260	DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
1261	} DCIOCHIP_GPIO_I2C_DRIVE;
1262	typedef enum DCIOCHIP_GPIO_I2C_EN {
1263	DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
1264	DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
1265	} DCIOCHIP_GPIO_I2C_EN;
1266	typedef enum DCIOCHIP_MASK_4BIT {
1267	DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
1268	DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
1269	} DCIOCHIP_MASK_4BIT;
1270	typedef enum DCIOCHIP_ENABLE_4BIT {
1271	DCIOCHIP_4BIT_DISABLE = 0x0,
1272	DCIOCHIP_4BIT_ENABLE = 0xf,
1273	} DCIOCHIP_ENABLE_4BIT;
1274	typedef enum DCIOCHIP_MASK_5BIT {
1275	DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
1276	DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
1277	} DCIOCHIP_MASK_5BIT;
1278	typedef enum DCIOCHIP_ENABLE_5BIT {
1279	DCIOCHIP_5BIT_DISABLE = 0x0,
1280	DCIOCHIP_5BIT_ENABLE = 0x1f,
1281	} DCIOCHIP_ENABLE_5BIT;
1282	typedef enum DCIOCHIP_MASK_2BIT {
1283	DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
1284	DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
1285	} DCIOCHIP_MASK_2BIT;
1286	typedef enum DCIOCHIP_ENABLE_2BIT {
1287	DCIOCHIP_2BIT_DISABLE = 0x0,
1288	DCIOCHIP_2BIT_ENABLE = 0x3,
1289	} DCIOCHIP_ENABLE_2BIT;
1290	typedef enum DCIOCHIP_REF_27_SRC_SEL {
1291	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
1292	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
1293	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
1294	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
1295	} DCIOCHIP_REF_27_SRC_SEL;
1296	typedef enum DCIOCHIP_DVO_VREFPON {
1297	DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
1298	DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
1299	} DCIOCHIP_DVO_VREFPON;
1300	typedef enum DCIOCHIP_DVO_VREFSEL {
1301	DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
1302	DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
1303	} DCIOCHIP_DVO_VREFSEL;
1304	typedef enum DCP_GRPH_ENABLE {
1305	DCP_GRPH_ENABLE_FALSE = 0x0,
1306	DCP_GRPH_ENABLE_TRUE = 0x1,
1307	} DCP_GRPH_ENABLE;
1308	typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
1309	DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0,
1310	DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1,
1311	} DCP_GRPH_KEYER_ALPHA_SEL;
1312	typedef enum DCP_GRPH_DEPTH {
1313	DCP_GRPH_DEPTH_8BPP = 0x0,
1314	DCP_GRPH_DEPTH_16BPP = 0x1,
1315	DCP_GRPH_DEPTH_32BPP = 0x2,
1316	DCP_GRPH_DEPTH_64BPP = 0x3,
1317	} DCP_GRPH_DEPTH;
1318	typedef enum DCP_GRPH_NUM_BANKS {
1319	DCP_GRPH_NUM_BANKS_2BANK = 0x0,
1320	DCP_GRPH_NUM_BANKS_4BANK = 0x1,
1321	DCP_GRPH_NUM_BANKS_8BANK = 0x2,
1322	DCP_GRPH_NUM_BANKS_16BANK = 0x3,
1323	} DCP_GRPH_NUM_BANKS;
1324	typedef enum DCP_GRPH_BANK_WIDTH {
1325	DCP_GRPH_BANK_WIDTH_1 = 0x0,
1326	DCP_GRPH_BANK_WIDTH_2 = 0x1,
1327	DCP_GRPH_BANK_WIDTH_4 = 0x2,
1328	DCP_GRPH_BANK_WIDTH_8 = 0x3,
1329	} DCP_GRPH_BANK_WIDTH;
1330	typedef enum DCP_GRPH_FORMAT {
1331	DCP_GRPH_FORMAT_8BPP = 0x0,
1332	DCP_GRPH_FORMAT_16BPP = 0x1,
1333	DCP_GRPH_FORMAT_32BPP = 0x2,
1334	DCP_GRPH_FORMAT_64BPP = 0x3,
1335	} DCP_GRPH_FORMAT;
1336	typedef enum DCP_GRPH_BANK_HEIGHT {
1337	DCP_GRPH_BANK_HEIGHT_1 = 0x0,
1338	DCP_GRPH_BANK_HEIGHT_2 = 0x1,
1339	DCP_GRPH_BANK_HEIGHT_4 = 0x2,
1340	DCP_GRPH_BANK_HEIGHT_8 = 0x3,
1341	} DCP_GRPH_BANK_HEIGHT;
1342	typedef enum DCP_GRPH_TILE_SPLIT {
1343	DCP_GRPH_TILE_SPLIT_64B = 0x0,
1344	DCP_GRPH_TILE_SPLIT_128B = 0x1,
1345	DCP_GRPH_TILE_SPLIT_256B = 0x2,
1346	DCP_GRPH_TILE_SPLIT_512B = 0x3,
1347	DCP_GRPH_TILE_SPLIT_1B = 0x4,
1348	DCP_GRPH_TILE_SPLIT_2B = 0x5,
1349	DCP_GRPH_TILE_SPLIT_4B = 0x6,
1350	} DCP_GRPH_TILE_SPLIT;
1351	typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
1352	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0,
1353	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1,
1354	} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
1355	typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
1356	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0,
1357	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1,
1358	} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
1359	typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
1360	DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0,
1361	DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1,
1362	DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2,
1363	DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3,
1364	} DCP_GRPH_MACRO_TILE_ASPECT;
1365	typedef enum DCP_GRPH_ARRAY_MODE {
1366	DCP_GRPH_ARRAY_MODE_0 = 0x0,
1367	DCP_GRPH_ARRAY_MODE_1 = 0x1,
1368	DCP_GRPH_ARRAY_MODE_2 = 0x2,
1369	DCP_GRPH_ARRAY_MODE_3 = 0x3,
1370	DCP_GRPH_ARRAY_MODE_4 = 0x4,
1371	DCP_GRPH_ARRAY_MODE_7 = 0x7,
1372	DCP_GRPH_ARRAY_MODE_12 = 0xc,
1373	DCP_GRPH_ARRAY_MODE_13 = 0xd,
1374	} DCP_GRPH_ARRAY_MODE;
1375	typedef enum DCP_GRPH_MICRO_TILE_MODE {
1376	DCP_GRPH_MICRO_TILE_MODE_0 = 0x0,
1377	DCP_GRPH_MICRO_TILE_MODE_1 = 0x1,
1378	DCP_GRPH_MICRO_TILE_MODE_2 = 0x2,
1379	DCP_GRPH_MICRO_TILE_MODE_3 = 0x3,
1380	} DCP_GRPH_MICRO_TILE_MODE;
1381	typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
1382	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0,
1383	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1,
1384	} DCP_GRPH_COLOR_EXPANSION_MODE;
1385	typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
1386	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0,
1387	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1,
1388	} DCP_GRPH_LUT_10BIT_BYPASS_EN;
1389	typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
1390	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0,
1391	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1,
1392	} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
1393	typedef enum DCP_GRPH_ENDIAN_SWAP {
1394	DCP_GRPH_ENDIAN_SWAP_NONE = 0x0,
1395	DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
1396	DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
1397	DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3,
1398	} DCP_GRPH_ENDIAN_SWAP;
1399	typedef enum DCP_GRPH_RED_CROSSBAR {
1400	DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0,
1401	DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1,
1402	DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2,
1403	DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3,
1404	} DCP_GRPH_RED_CROSSBAR;
1405	typedef enum DCP_GRPH_GREEN_CROSSBAR {
1406	DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0,
1407	DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1,
1408	DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2,
1409	DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3,
1410	} DCP_GRPH_GREEN_CROSSBAR;
1411	typedef enum DCP_GRPH_BLUE_CROSSBAR {
1412	DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0,
1413	DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1,
1414	DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2,
1415	DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3,
1416	} DCP_GRPH_BLUE_CROSSBAR;
1417	typedef enum DCP_GRPH_ALPHA_CROSSBAR {
1418	DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0,
1419	DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1,
1420	DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2,
1421	DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3,
1422	} DCP_GRPH_ALPHA_CROSSBAR;
1423	typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
1424	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0,
1425	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1,
1426	} DCP_GRPH_PRIMARY_DFQ_ENABLE;
1427	typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
1428	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0,
1429	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1,
1430	} DCP_GRPH_SECONDARY_DFQ_ENABLE;
1431	typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
1432	DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0,
1433	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1,
1434	} DCP_GRPH_INPUT_GAMMA_MODE;
1435	typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
1436	DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0,
1437	DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1,
1438	} DCP_GRPH_MODE_UPDATE_PENDING;
1439	typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
1440	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0,
1441	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1,
1442	} DCP_GRPH_MODE_UPDATE_TAKEN;
1443	typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
1444	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0,
1445	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1,
1446	} DCP_GRPH_SURFACE_UPDATE_PENDING;
1447	typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
1448	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0,
1449	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1,
1450	} DCP_GRPH_SURFACE_UPDATE_TAKEN;
1451	typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
1452	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0,
1453	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1,
1454	} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
1455	typedef enum DCP_GRPH_UPDATE_LOCK {
1456	DCP_GRPH_UPDATE_LOCK_FALSE = 0x0,
1457	DCP_GRPH_UPDATE_LOCK_TRUE = 0x1,
1458	} DCP_GRPH_UPDATE_LOCK;
1459	typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
1460	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0,
1461	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1,
1462	} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
1463	typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
1464	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
1465	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
1466	} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
1467	typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
1468	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
1469	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
1470	} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
1471	typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
1472	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0,
1473	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1,
1474	} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1475	typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
1476	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0,
1477	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1,
1478	} DCP_GRPH_XDMA_SUPER_AA_EN;
1479	typedef enum DCP_GRPH_DFQ_RESET {
1480	DCP_GRPH_DFQ_RESET_FALSE = 0x0,
1481	DCP_GRPH_DFQ_RESET_TRUE = 0x1,
1482	} DCP_GRPH_DFQ_RESET;
1483	typedef enum DCP_GRPH_DFQ_SIZE {
1484	DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0,
1485	DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1,
1486	DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2,
1487	DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3,
1488	DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4,
1489	DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5,
1490	DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6,
1491	DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7,
1492	} DCP_GRPH_DFQ_SIZE;
1493	typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
1494	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0,
1495	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1,
1496	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2,
1497	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3,
1498	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4,
1499	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5,
1500	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6,
1501	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7,
1502	} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
1503	typedef enum DCP_GRPH_DFQ_RESET_ACK {
1504	DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0,
1505	DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1,
1506	} DCP_GRPH_DFQ_RESET_ACK;
1507	typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
1508	DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0,
1509	DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1,
1510	} DCP_GRPH_PFLIP_INT_CLEAR;
1511	typedef enum DCP_GRPH_PFLIP_INT_MASK {
1512	DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0,
1513	DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1,
1514	} DCP_GRPH_PFLIP_INT_MASK;
1515	typedef enum DCP_GRPH_PFLIP_INT_TYPE {
1516	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0,
1517	DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1,
1518	} DCP_GRPH_PFLIP_INT_TYPE;
1519	typedef enum DCP_GRPH_PRESCALE_SELECT {
1520	DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0,
1521	DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1,
1522	} DCP_GRPH_PRESCALE_SELECT;
1523	typedef enum DCP_GRPH_PRESCALE_R_SIGN {
1524	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0,
1525	DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1,
1526	} DCP_GRPH_PRESCALE_R_SIGN;
1527	typedef enum DCP_GRPH_PRESCALE_G_SIGN {
1528	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0,
1529	DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1,
1530	} DCP_GRPH_PRESCALE_G_SIGN;
1531	typedef enum DCP_GRPH_PRESCALE_B_SIGN {
1532	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0,
1533	DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1,
1534	} DCP_GRPH_PRESCALE_B_SIGN;
1535	typedef enum DCP_GRPH_PRESCALE_BYPASS {
1536	DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0,
1537	DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1,
1538	} DCP_GRPH_PRESCALE_BYPASS;
1539	typedef enum DCP_INPUT_CSC_GRPH_MODE {
1540	DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0,
1541	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1,
1542	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2,
1543	DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3,
1544	} DCP_INPUT_CSC_GRPH_MODE;
1545	typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
1546	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0,
1547	DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1,
1548	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2,
1549	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3,
1550	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4,
1551	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5,
1552	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6,
1553	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7,
1554	} DCP_OUTPUT_CSC_GRPH_MODE;
1555	typedef enum DCP_DENORM_MODE {
1556	DCP_DENORM_MODE_UNITY = 0x0,
1557	DCP_DENORM_MODE_6BIT = 0x1,
1558	DCP_DENORM_MODE_8BIT = 0x2,
1559	DCP_DENORM_MODE_10BIT = 0x3,
1560	DCP_DENORM_MODE_11BIT = 0x4,
1561	DCP_DENORM_MODE_12BIT = 0x5,
1562	DCP_DENORM_MODE_RESERVED0 = 0x6,
1563	DCP_DENORM_MODE_RESERVED1 = 0x7,
1564	} DCP_DENORM_MODE;
1565	typedef enum DCP_DENORM_14BIT_OUT {
1566	DCP_DENORM_14BIT_OUT_FALSE = 0x0,
1567	DCP_DENORM_14BIT_OUT_TRUE = 0x1,
1568	} DCP_DENORM_14BIT_OUT;
1569	typedef enum DCP_OUT_ROUND_TRUNC_MODE {
1570	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0,
1571	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1,
1572	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2,
1573	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3,
1574	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4,
1575	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5,
1576	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6,
1577	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7,
1578	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8,
1579	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9,
1580	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa,
1581	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb,
1582	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc,
1583	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd,
1584	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe,
1585	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf,
1586	} DCP_OUT_ROUND_TRUNC_MODE;
1587	typedef enum DCP_KEY_MODE {
1588	DCP_KEY_MODE_ALPHA0 = 0x0,
1589	DCP_KEY_MODE_ALPHA1 = 0x1,
1590	DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2,
1591	DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3,
1592	} DCP_KEY_MODE;
1593	typedef enum DCP_GRPH_DEGAMMA_MODE {
1594	DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0,
1595	DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1,
1596	DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2,
1597	DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3,
1598	} DCP_GRPH_DEGAMMA_MODE;
1599	typedef enum DCP_CURSOR2_DEGAMMA_MODE {
1600	DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0,
1601	DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1,
1602	DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2,
1603	DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3,
1604	} DCP_CURSOR2_DEGAMMA_MODE;
1605	typedef enum DCP_CURSOR_DEGAMMA_MODE {
1606	DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0,
1607	DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1,
1608	DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2,
1609	DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3,
1610	} DCP_CURSOR_DEGAMMA_MODE;
1611	typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
1612	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0,
1613	DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1,
1614	DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2,
1615	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3,
1616	} DCP_GRPH_GAMUT_REMAP_MODE;
1617	typedef enum DCP_SPATIAL_DITHER_EN {
1618	DCP_SPATIAL_DITHER_EN_FALSE = 0x0,
1619	DCP_SPATIAL_DITHER_EN_TRUE = 0x1,
1620	} DCP_SPATIAL_DITHER_EN;
1621	typedef enum DCP_SPATIAL_DITHER_MODE {
1622	DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0,
1623	DCP_SPATIAL_DITHER_MODE_ROMA = 0x1,
1624	DCP_SPATIAL_DITHER_MODE_ROMB = 0x2,
1625	DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3,
1626	} DCP_SPATIAL_DITHER_MODE;
1627	typedef enum DCP_SPATIAL_DITHER_DEPTH {
1628	DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0,
1629	DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
1630	DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2,
1631	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3,
1632	} DCP_SPATIAL_DITHER_DEPTH;
1633	typedef enum DCP_FRAME_RANDOM_ENABLE {
1634	DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0,
1635	DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1,
1636	} DCP_FRAME_RANDOM_ENABLE;
1637	typedef enum DCP_RGB_RANDOM_ENABLE {
1638	DCP_RGB_RANDOM_ENABLE_FALSE = 0x0,
1639	DCP_RGB_RANDOM_ENABLE_TRUE = 0x1,
1640	} DCP_RGB_RANDOM_ENABLE;
1641	typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
1642	DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0,
1643	DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1,
1644	} DCP_HIGHPASS_RANDOM_ENABLE;
1645	typedef enum DCP_CURSOR_EN {
1646	DCP_CURSOR_EN_FALSE = 0x0,
1647	DCP_CURSOR_EN_TRUE = 0x1,
1648	} DCP_CURSOR_EN;
1649	typedef enum DCP_CUR_INV_TRANS_CLAMP {
1650	DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0,
1651	DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1,
1652	} DCP_CUR_INV_TRANS_CLAMP;
1653	typedef enum DCP_CURSOR_MODE {
1654	DCP_CURSOR_MODE_MONO_2BPP = 0x0,
1655	DCP_CURSOR_MODE_24BPP_1BIT = 0x1,
1656	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2,
1657	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
1658	} DCP_CURSOR_MODE;
1659	typedef enum DCP_CURSOR_2X_MAGNIFY {
1660	DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0,
1661	DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1,
1662	} DCP_CURSOR_2X_MAGNIFY;
1663	typedef enum DCP_CURSOR_FORCE_MC_ON {
1664	DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0,
1665	DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1,
1666	} DCP_CURSOR_FORCE_MC_ON;
1667	typedef enum DCP_CURSOR_URGENT_CONTROL {
1668	DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0,
1669	DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1,
1670	DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2,
1671	DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3,
1672	DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4,
1673	} DCP_CURSOR_URGENT_CONTROL;
1674	typedef enum DCP_CURSOR_UPDATE_PENDING {
1675	DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0,
1676	DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1,
1677	} DCP_CURSOR_UPDATE_PENDING;
1678	typedef enum DCP_CURSOR_UPDATE_TAKEN {
1679	DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0,
1680	DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1,
1681	} DCP_CURSOR_UPDATE_TAKEN;
1682	typedef enum DCP_CURSOR_UPDATE_LOCK {
1683	DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0,
1684	DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1,
1685	} DCP_CURSOR_UPDATE_LOCK;
1686	typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
1687	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
1688	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
1689	} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
1690	typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
1691	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0,
1692	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
1693	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
1694	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
1695	} DCP_CURSOR_UPDATE_STEREO_MODE;
1696	typedef enum DCP_CURSOR2_EN {
1697	DCP_CURSOR2_EN_FALSE = 0x0,
1698	DCP_CURSOR2_EN_TRUE = 0x1,
1699	} DCP_CURSOR2_EN;
1700	typedef enum DCP_CUR2_INV_TRANS_CLAMP {
1701	DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0,
1702	DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1,
1703	} DCP_CUR2_INV_TRANS_CLAMP;
1704	typedef enum DCP_CURSOR2_MODE {
1705	DCP_CURSOR2_MODE_MONO_2BPP = 0x0,
1706	DCP_CURSOR2_MODE_24BPP_1BIT = 0x1,
1707	DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2,
1708	DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
1709	} DCP_CURSOR2_MODE;
1710	typedef enum DCP_CURSOR2_2X_MAGNIFY {
1711	DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0,
1712	DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1,
1713	} DCP_CURSOR2_2X_MAGNIFY;
1714	typedef enum DCP_CURSOR2_FORCE_MC_ON {
1715	DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0,
1716	DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1,
1717	} DCP_CURSOR2_FORCE_MC_ON;
1718	typedef enum DCP_CURSOR2_URGENT_CONTROL {
1719	DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0,
1720	DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1,
1721	DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2,
1722	DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3,
1723	DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4,
1724	} DCP_CURSOR2_URGENT_CONTROL;
1725	typedef enum DCP_CURSOR2_UPDATE_PENDING {
1726	DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0,
1727	DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1,
1728	} DCP_CURSOR2_UPDATE_PENDING;
1729	typedef enum DCP_CURSOR2_UPDATE_TAKEN {
1730	DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0,
1731	DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1,
1732	} DCP_CURSOR2_UPDATE_TAKEN;
1733	typedef enum DCP_CURSOR2_UPDATE_LOCK {
1734	DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0,
1735	DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1,
1736	} DCP_CURSOR2_UPDATE_LOCK;
1737	typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
1738	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
1739	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
1740	} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
1741	typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
1742	DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0,
1743	DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
1744	DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
1745	DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
1746	} DCP_CURSOR2_UPDATE_STEREO_MODE;
1747	typedef enum DCP_CUR_REQUEST_FILTER_DIS {
1748	DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0,
1749	DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1,
1750	} DCP_CUR_REQUEST_FILTER_DIS;
1751	typedef enum DCP_CURSOR_STEREO_EN {
1752	DCP_CURSOR_STEREO_EN_FALSE = 0x0,
1753	DCP_CURSOR_STEREO_EN_TRUE = 0x1,
1754	} DCP_CURSOR_STEREO_EN;
1755	typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
1756	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0,
1757	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
1758	} DCP_CURSOR_STEREO_OFFSET_YNX;
1759	typedef enum DCP_CURSOR2_STEREO_EN {
1760	DCP_CURSOR2_STEREO_EN_FALSE = 0x0,
1761	DCP_CURSOR2_STEREO_EN_TRUE = 0x1,
1762	} DCP_CURSOR2_STEREO_EN;
1763	typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
1764	DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0,
1765	DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
1766	} DCP_CURSOR2_STEREO_OFFSET_YNX;
1767	typedef enum DCP_DC_LUT_RW_MODE {
1768	DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0,
1769	DCP_DC_LUT_RW_MODE_PWL = 0x1,
1770	} DCP_DC_LUT_RW_MODE;
1771	typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
1772	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0,
1773	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1,
1774	} DCP_DC_LUT_VGA_ACCESS_ENABLE;
1775	typedef enum DCP_DC_LUT_AUTOFILL {
1776	DCP_DC_LUT_AUTOFILL_FALSE = 0x0,
1777	DCP_DC_LUT_AUTOFILL_TRUE = 0x1,
1778	} DCP_DC_LUT_AUTOFILL;
1779	typedef enum DCP_DC_LUT_AUTOFILL_DONE {
1780	DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0,
1781	DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1,
1782	} DCP_DC_LUT_AUTOFILL_DONE;
1783	typedef enum DCP_DC_LUT_INC_B {
1784	DCP_DC_LUT_INC_B_NA = 0x0,
1785	DCP_DC_LUT_INC_B_2 = 0x1,
1786	DCP_DC_LUT_INC_B_4 = 0x2,
1787	DCP_DC_LUT_INC_B_8 = 0x3,
1788	DCP_DC_LUT_INC_B_16 = 0x4,
1789	DCP_DC_LUT_INC_B_32 = 0x5,
1790	DCP_DC_LUT_INC_B_64 = 0x6,
1791	DCP_DC_LUT_INC_B_128 = 0x7,
1792	DCP_DC_LUT_INC_B_256 = 0x8,
1793	DCP_DC_LUT_INC_B_512 = 0x9,
1794	} DCP_DC_LUT_INC_B;
1795	typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
1796	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0,
1797	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1,
1798	} DCP_DC_LUT_DATA_B_SIGNED_EN;
1799	typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
1800	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0,
1801	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1,
1802	} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
1803	typedef enum DCP_DC_LUT_DATA_B_FORMAT {
1804	DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0,
1805	DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1,
1806	DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2,
1807	DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3,
1808	} DCP_DC_LUT_DATA_B_FORMAT;
1809	typedef enum DCP_DC_LUT_INC_G {
1810	DCP_DC_LUT_INC_G_NA = 0x0,
1811	DCP_DC_LUT_INC_G_2 = 0x1,
1812	DCP_DC_LUT_INC_G_4 = 0x2,
1813	DCP_DC_LUT_INC_G_8 = 0x3,
1814	DCP_DC_LUT_INC_G_16 = 0x4,
1815	DCP_DC_LUT_INC_G_32 = 0x5,
1816	DCP_DC_LUT_INC_G_64 = 0x6,
1817	DCP_DC_LUT_INC_G_128 = 0x7,
1818	DCP_DC_LUT_INC_G_256 = 0x8,
1819	DCP_DC_LUT_INC_G_512 = 0x9,
1820	} DCP_DC_LUT_INC_G;
1821	typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
1822	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0,
1823	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1,
1824	} DCP_DC_LUT_DATA_G_SIGNED_EN;
1825	typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
1826	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0,
1827	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1,
1828	} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
1829	typedef enum DCP_DC_LUT_DATA_G_FORMAT {
1830	DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0,
1831	DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1,
1832	DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2,
1833	DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3,
1834	} DCP_DC_LUT_DATA_G_FORMAT;
1835	typedef enum DCP_DC_LUT_INC_R {
1836	DCP_DC_LUT_INC_R_NA = 0x0,
1837	DCP_DC_LUT_INC_R_2 = 0x1,
1838	DCP_DC_LUT_INC_R_4 = 0x2,
1839	DCP_DC_LUT_INC_R_8 = 0x3,
1840	DCP_DC_LUT_INC_R_16 = 0x4,
1841	DCP_DC_LUT_INC_R_32 = 0x5,
1842	DCP_DC_LUT_INC_R_64 = 0x6,
1843	DCP_DC_LUT_INC_R_128 = 0x7,
1844	DCP_DC_LUT_INC_R_256 = 0x8,
1845	DCP_DC_LUT_INC_R_512 = 0x9,
1846	} DCP_DC_LUT_INC_R;
1847	typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
1848	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0,
1849	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1,
1850	} DCP_DC_LUT_DATA_R_SIGNED_EN;
1851	typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
1852	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0,
1853	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1,
1854	} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
1855	typedef enum DCP_DC_LUT_DATA_R_FORMAT {
1856	DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0,
1857	DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1,
1858	DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2,
1859	DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3,
1860	} DCP_DC_LUT_DATA_R_FORMAT;
1861	typedef enum DCP_CRC_ENABLE {
1862	DCP_CRC_ENABLE_FALSE = 0x0,
1863	DCP_CRC_ENABLE_TRUE = 0x1,
1864	} DCP_CRC_ENABLE;
1865	typedef enum DCP_CRC_SOURCE_SEL {
1866	DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0,
1867	DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1,
1868	DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2,
1869	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4,
1870	} DCP_CRC_SOURCE_SEL;
1871	typedef enum DCP_CRC_LINE_SEL {
1872	DCP_CRC_LINE_SEL_RESERVED = 0x0,
1873	DCP_CRC_LINE_SEL_EVEN = 0x1,
1874	DCP_CRC_LINE_SEL_ODD = 0x2,
1875	DCP_CRC_LINE_SEL_BOTH = 0x3,
1876	} DCP_CRC_LINE_SEL;
1877	typedef enum DCP_GRPH_FLIP_RATE {
1878	DCP_GRPH_FLIP_RATE_1FRAME = 0x0,
1879	DCP_GRPH_FLIP_RATE_2FRAME = 0x1,
1880	DCP_GRPH_FLIP_RATE_3FRAME = 0x2,
1881	DCP_GRPH_FLIP_RATE_4FRAME = 0x3,
1882	DCP_GRPH_FLIP_RATE_5FRAME = 0x4,
1883	DCP_GRPH_FLIP_RATE_6FRAME = 0x5,
1884	DCP_GRPH_FLIP_RATE_7FRAME = 0x6,
1885	DCP_GRPH_FLIP_RATE_8FRAME = 0x7,
1886	} DCP_GRPH_FLIP_RATE;
1887	typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
1888	DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0,
1889	DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1,
1890	} DCP_GRPH_FLIP_RATE_ENABLE;
1891	typedef enum DCP_GSL0_EN {
1892	DCP_GSL0_EN_FALSE = 0x0,
1893	DCP_GSL0_EN_TRUE = 0x1,
1894	} DCP_GSL0_EN;
1895	typedef enum DCP_GSL1_EN {
1896	DCP_GSL1_EN_FALSE = 0x0,
1897	DCP_GSL1_EN_TRUE = 0x1,
1898	} DCP_GSL1_EN;
1899	typedef enum DCP_GSL2_EN {
1900	DCP_GSL2_EN_FALSE = 0x0,
1901	DCP_GSL2_EN_TRUE = 0x1,
1902	} DCP_GSL2_EN;
1903	typedef enum DCP_GSL_MASTER_EN {
1904	DCP_GSL_MASTER_EN_FALSE = 0x0,
1905	DCP_GSL_MASTER_EN_TRUE = 0x1,
1906	} DCP_GSL_MASTER_EN;
1907	typedef enum DCP_GSL_XDMA_GROUP {
1908	DCP_GSL_XDMA_GROUP_VSYNC = 0x0,
1909	DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1,
1910	DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2,
1911	DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3,
1912	} DCP_GSL_XDMA_GROUP;
1913	typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
1914	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0,
1915	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1,
1916	} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
1917	typedef enum DCP_GSL_SYNC_SOURCE {
1918	DCP_GSL_SYNC_SOURCE_FLIP = 0x0,
1919	DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1,
1920	DCP_GSL_SYNC_SOURCE_RESET = 0x2,
1921	DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3,
1922	} DCP_GSL_SYNC_SOURCE;
1923	typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
1924	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0,
1925	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1,
1926	} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
1927	typedef enum DCP_TEST_DEBUG_WRITE_EN {
1928	DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0,
1929	DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1,
1930	} DCP_TEST_DEBUG_WRITE_EN;
1931	typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
1932	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0,
1933	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1,
1934	} DCP_GRPH_STEREOSYNC_FLIP_EN;
1935	typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
1936	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0,
1937	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1,
1938	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2,
1939	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3,
1940	} DCP_GRPH_STEREOSYNC_FLIP_MODE;
1941	typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
1942	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0,
1943	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1,
1944	} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
1945	typedef enum DCP_GRPH_ROTATION_ANGLE {
1946	DCP_GRPH_ROTATION_ANGLE_0 = 0x0,
1947	DCP_GRPH_ROTATION_ANGLE_90 = 0x1,
1948	DCP_GRPH_ROTATION_ANGLE_180 = 0x2,
1949	DCP_GRPH_ROTATION_ANGLE_270 = 0x3,
1950	} DCP_GRPH_ROTATION_ANGLE;
1951	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
1952	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0,
1953	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1,
1954	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
1955	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
1956	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0,
1957	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
1958	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
1959	typedef enum DCP_GRPH_REGAMMA_MODE {
1960	DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0,
1961	DCP_GRPH_REGAMMA_MODE_SRGB = 0x1,
1962	DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2,
1963	DCP_GRPH_REGAMMA_MODE_PROGA = 0x3,
1964	DCP_GRPH_REGAMMA_MODE_PROGB = 0x4,
1965	} DCP_GRPH_REGAMMA_MODE;
1966	typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
1967	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0,
1968	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1,
1969	} DCP_ALPHA_ROUND_TRUNC_MODE;
1970	typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
1971	DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0,
1972	DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1,
1973	} DCP_CURSOR_ALPHA_BLND_ENA;
1974	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
1975	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0,
1976	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1,
1977	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
1978	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
1979	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0,
1980	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1,
1981	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
1982	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
1983	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0,
1984	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1,
1985	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
1986	typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
1987	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0,
1988	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1,
1989	} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
1990	typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
1991	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0,
1992	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1,
1993	} DCP_GRPH_SURFACE_COUNTER_EN;
1994	typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
1995	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0,
1996	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1,
1997	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2,
1998	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3,
1999	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4,
2000	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5,
2001	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6,
2002	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7,
2003	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8,
2004	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9,
2005	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa,
2006	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb,
2007	} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
2008	typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
2009	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0,
2010	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1,
2011	} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
2012	typedef enum HDMI_KEEPOUT_MODE {
2013	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0,
2014	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1,
2015	} HDMI_KEEPOUT_MODE;
2016	typedef enum HDMI_CLOCK_CHANNEL_RATE {
2017	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0,
2018	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1,
2019	} HDMI_CLOCK_CHANNEL_RATE;
2020	typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
2021	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0,
2022	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1,
2023	} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
2024	typedef enum HDMI_PACKET_GEN_VERSION {
2025	HDMI_PACKET_GEN_VERSION_OLD = 0x0,
2026	HDMI_PACKET_GEN_VERSION_NEW = 0x1,
2027	} HDMI_PACKET_GEN_VERSION;
2028	typedef enum HDMI_ERROR_ACK {
2029	HDMI_ERROR_ACK_INT = 0x0,
2030	HDMI_ERROR_NOT_ACK = 0x1,
2031	} HDMI_ERROR_ACK;
2032	typedef enum HDMI_ERROR_MASK {
2033	HDMI_ERROR_MASK_INT = 0x0,
2034	HDMI_ERROR_NOT_MASK = 0x1,
2035	} HDMI_ERROR_MASK;
2036	typedef enum HDMI_DEEP_COLOR_DEPTH {
2037	HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0,
2038	HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1,
2039	HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2,
2040	HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3,
2041	} HDMI_DEEP_COLOR_DEPTH;
2042	typedef enum HDMI_AUDIO_DELAY_EN {
2043	HDMI_AUDIO_DELAY_DISABLE = 0x0,
2044	HDMI_AUDIO_DELAY_58CLK = 0x1,
2045	HDMI_AUDIO_DELAY_56CLK = 0x2,
2046	HDMI_AUDIO_DELAY_RESERVED = 0x3,
2047	} HDMI_AUDIO_DELAY_EN;
2048	typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
2049	HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0,
2050	HDMI_SEND_MAX_AUDIO_PACKETS = 0x1,
2051	} HDMI_AUDIO_SEND_MAX_PACKETS;
2052	typedef enum HDMI_ACR_SEND {
2053	HDMI_ACR_NOT_SEND = 0x0,
2054	HDMI_ACR_PKT_SEND = 0x1,
2055	} HDMI_ACR_SEND;
2056	typedef enum HDMI_ACR_CONT {
2057	HDMI_ACR_CONT_DISABLE = 0x0,
2058	HDMI_ACR_CONT_ENABLE = 0x1,
2059	} HDMI_ACR_CONT;
2060	typedef enum HDMI_ACR_SELECT {
2061	HDMI_ACR_SELECT_HW = 0x0,
2062	HDMI_ACR_SELECT_32K = 0x1,
2063	HDMI_ACR_SELECT_44K = 0x2,
2064	HDMI_ACR_SELECT_48K = 0x3,
2065	} HDMI_ACR_SELECT;
2066	typedef enum HDMI_ACR_SOURCE {
2067	HDMI_ACR_SOURCE_HW = 0x0,
2068	HDMI_ACR_SOURCE_SW = 0x1,
2069	} HDMI_ACR_SOURCE;
2070	typedef enum HDMI_ACR_N_MULTIPLE {
2071	HDMI_ACR_0_MULTIPLE_RESERVED = 0x0,
2072	HDMI_ACR_1_MULTIPLE = 0x1,
2073	HDMI_ACR_2_MULTIPLE = 0x2,
2074	HDMI_ACR_3_MULTIPLE_RESERVED = 0x3,
2075	HDMI_ACR_4_MULTIPLE = 0x4,
2076	HDMI_ACR_5_MULTIPLE_RESERVED = 0x5,
2077	HDMI_ACR_6_MULTIPLE_RESERVED = 0x6,
2078	HDMI_ACR_7_MULTIPLE_RESERVED = 0x7,
2079	} HDMI_ACR_N_MULTIPLE;
2080	typedef enum HDMI_ACR_AUDIO_PRIORITY {
2081	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0,
2082	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1,
2083	} HDMI_ACR_AUDIO_PRIORITY;
2084	typedef enum HDMI_NULL_SEND {
2085	HDMI_NULL_NOT_SEND = 0x0,
2086	HDMI_NULL_PKT_SEND = 0x1,
2087	} HDMI_NULL_SEND;
2088	typedef enum HDMI_GC_SEND {
2089	HDMI_GC_NOT_SEND = 0x0,
2090	HDMI_GC_PKT_SEND = 0x1,
2091	} HDMI_GC_SEND;
2092	typedef enum HDMI_GC_CONT {
2093	HDMI_GC_CONT_DISABLE = 0x0,
2094	HDMI_GC_CONT_ENABLE = 0x1,
2095	} HDMI_GC_CONT;
2096	typedef enum HDMI_ISRC_SEND {
2097	HDMI_ISRC_NOT_SEND = 0x0,
2098	HDMI_ISRC_PKT_SEND = 0x1,
2099	} HDMI_ISRC_SEND;
2100	typedef enum HDMI_ISRC_CONT {
2101	HDMI_ISRC_CONT_DISABLE = 0x0,
2102	HDMI_ISRC_CONT_ENABLE = 0x1,
2103	} HDMI_ISRC_CONT;
2104	typedef enum HDMI_AVI_INFO_SEND {
2105	HDMI_AVI_INFO_NOT_SEND = 0x0,
2106	HDMI_AVI_INFO_PKT_SEND = 0x1,
2107	} HDMI_AVI_INFO_SEND;
2108	typedef enum HDMI_AVI_INFO_CONT {
2109	HDMI_AVI_INFO_CONT_DISABLE = 0x0,
2110	HDMI_AVI_INFO_CONT_ENABLE = 0x1,
2111	} HDMI_AVI_INFO_CONT;
2112	typedef enum HDMI_AUDIO_INFO_SEND {
2113	HDMI_AUDIO_INFO_NOT_SEND = 0x0,
2114	HDMI_AUDIO_INFO_PKT_SEND = 0x1,
2115	} HDMI_AUDIO_INFO_SEND;
2116	typedef enum HDMI_AUDIO_INFO_CONT {
2117	HDMI_AUDIO_INFO_CONT_DISABLE = 0x0,
2118	HDMI_AUDIO_INFO_CONT_ENABLE = 0x1,
2119	} HDMI_AUDIO_INFO_CONT;
2120	typedef enum HDMI_MPEG_INFO_SEND {
2121	HDMI_MPEG_INFO_NOT_SEND = 0x0,
2122	HDMI_MPEG_INFO_PKT_SEND = 0x1,
2123	} HDMI_MPEG_INFO_SEND;
2124	typedef enum HDMI_MPEG_INFO_CONT {
2125	HDMI_MPEG_INFO_CONT_DISABLE = 0x0,
2126	HDMI_MPEG_INFO_CONT_ENABLE = 0x1,
2127	} HDMI_MPEG_INFO_CONT;
2128	typedef enum HDMI_GENERIC0_SEND {
2129	HDMI_GENERIC0_NOT_SEND = 0x0,
2130	HDMI_GENERIC0_PKT_SEND = 0x1,
2131	} HDMI_GENERIC0_SEND;
2132	typedef enum HDMI_GENERIC0_CONT {
2133	HDMI_GENERIC0_CONT_DISABLE = 0x0,
2134	HDMI_GENERIC0_CONT_ENABLE = 0x1,
2135	} HDMI_GENERIC0_CONT;
2136	typedef enum HDMI_GENERIC1_SEND {
2137	HDMI_GENERIC1_NOT_SEND = 0x0,
2138	HDMI_GENERIC1_PKT_SEND = 0x1,
2139	} HDMI_GENERIC1_SEND;
2140	typedef enum HDMI_GENERIC1_CONT {
2141	HDMI_GENERIC1_CONT_DISABLE = 0x0,
2142	HDMI_GENERIC1_CONT_ENABLE = 0x1,
2143	} HDMI_GENERIC1_CONT;
2144	typedef enum HDMI_GC_AVMUTE_CONT {
2145	HDMI_GC_AVMUTE_CONT_DISABLE = 0x0,
2146	HDMI_GC_AVMUTE_CONT_ENABLE = 0x1,
2147	} HDMI_GC_AVMUTE_CONT;
2148	typedef enum HDMI_PACKING_PHASE_OVERRIDE {
2149	HDMI_PACKING_PHASE_SET_BY_HW = 0x0,
2150	HDMI_PACKING_PHASE_SET_BY_SW = 0x1,
2151	} HDMI_PACKING_PHASE_OVERRIDE;
2152	typedef enum HDMI_GENERIC2_SEND {
2153	HDMI_GENERIC2_NOT_SEND = 0x0,
2154	HDMI_GENERIC2_PKT_SEND = 0x1,
2155	} HDMI_GENERIC2_SEND;
2156	typedef enum HDMI_GENERIC2_CONT {
2157	HDMI_GENERIC2_CONT_DISABLE = 0x0,
2158	HDMI_GENERIC2_CONT_ENABLE = 0x1,
2159	} HDMI_GENERIC2_CONT;
2160	typedef enum HDMI_GENERIC3_SEND {
2161	HDMI_GENERIC3_NOT_SEND = 0x0,
2162	HDMI_GENERIC3_PKT_SEND = 0x1,
2163	} HDMI_GENERIC3_SEND;
2164	typedef enum HDMI_GENERIC3_CONT {
2165	HDMI_GENERIC3_CONT_DISABLE = 0x0,
2166	HDMI_GENERIC3_CONT_ENABLE = 0x1,
2167	} HDMI_GENERIC3_CONT;
2168	typedef enum TMDS_PIXEL_ENCODING {
2169	TMDS_PIXEL_ENCODING_444 = 0x0,
2170	TMDS_PIXEL_ENCODING_422 = 0x1,
2171	} TMDS_PIXEL_ENCODING;
2172	typedef enum TMDS_COLOR_FORMAT {
2173	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
2174	TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1,
2175	TMDS_COLOR_FORMAT_DUAL30BPP = 0x2,
2176	TMDS_COLOR_FORMAT_RESERVED = 0x3,
2177	} TMDS_COLOR_FORMAT;
2178	typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
2179	TMDS_STEREOSYNC_CTL0 = 0x0,
2180	TMDS_STEREOSYNC_CTL1 = 0x1,
2181	TMDS_STEREOSYNC_CTL2 = 0x2,
2182	TMDS_STEREOSYNC_CTL3 = 0x3,
2183	} TMDS_STEREOSYNC_CTL_SEL_REG;
2184	typedef enum TMDS_CTL0_DATA_SEL {
2185	TMDS_CTL0_DATA_SEL0_RESERVED = 0x0,
2186	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1,
2187	TMDS_CTL0_DATA_SEL2_VSYNC = 0x2,
2188	TMDS_CTL0_DATA_SEL3_RESERVED = 0x3,
2189	TMDS_CTL0_DATA_SEL4_HSYNC = 0x4,
2190	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5,
2191	TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6,
2192	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7,
2193	} TMDS_CTL0_DATA_SEL;
2194	typedef enum TMDS_CTL0_DATA_DELAY {
2195	TMDS_CTL0_DATA_DELAY_0PIX = 0x0,
2196	TMDS_CTL0_DATA_DELAY_1PIX = 0x1,
2197	TMDS_CTL0_DATA_DELAY_2PIX = 0x2,
2198	TMDS_CTL0_DATA_DELAY_3PIX = 0x3,
2199	TMDS_CTL0_DATA_DELAY_4PIX = 0x4,
2200	TMDS_CTL0_DATA_DELAY_5PIX = 0x5,
2201	TMDS_CTL0_DATA_DELAY_6PIX = 0x6,
2202	TMDS_CTL0_DATA_DELAY_7PIX = 0x7,
2203	} TMDS_CTL0_DATA_DELAY;
2204	typedef enum TMDS_CTL0_DATA_INVERT {
2205	TMDS_CTL0_DATA_NORMAL = 0x0,
2206	TMDS_CTL0_DATA_INVERT_EN = 0x1,
2207	} TMDS_CTL0_DATA_INVERT;
2208	typedef enum TMDS_CTL0_DATA_MODULATION {
2209	TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0,
2210	TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1,
2211	TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2,
2212	TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3,
2213	} TMDS_CTL0_DATA_MODULATION;
2214	typedef enum TMDS_CTL0_PATTERN_OUT_EN {
2215	TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0,
2216	TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1,
2217	} TMDS_CTL0_PATTERN_OUT_EN;
2218	typedef enum TMDS_CTL1_DATA_SEL {
2219	TMDS_CTL1_DATA_SEL0_RESERVED = 0x0,
2220	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1,
2221	TMDS_CTL1_DATA_SEL2_VSYNC = 0x2,
2222	TMDS_CTL1_DATA_SEL3_RESERVED = 0x3,
2223	TMDS_CTL1_DATA_SEL4_HSYNC = 0x4,
2224	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5,
2225	TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6,
2226	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7,
2227	} TMDS_CTL1_DATA_SEL;
2228	typedef enum TMDS_CTL1_DATA_DELAY {
2229	TMDS_CTL1_DATA_DELAY_0PIX = 0x0,
2230	TMDS_CTL1_DATA_DELAY_1PIX = 0x1,
2231	TMDS_CTL1_DATA_DELAY_2PIX = 0x2,
2232	TMDS_CTL1_DATA_DELAY_3PIX = 0x3,
2233	TMDS_CTL1_DATA_DELAY_4PIX = 0x4,
2234	TMDS_CTL1_DATA_DELAY_5PIX = 0x5,
2235	TMDS_CTL1_DATA_DELAY_6PIX = 0x6,
2236	TMDS_CTL1_DATA_DELAY_7PIX = 0x7,
2237	} TMDS_CTL1_DATA_DELAY;
2238	typedef enum TMDS_CTL1_DATA_INVERT {
2239	TMDS_CTL1_DATA_NORMAL = 0x0,
2240	TMDS_CTL1_DATA_INVERT_EN = 0x1,
2241	} TMDS_CTL1_DATA_INVERT;
2242	typedef enum TMDS_CTL1_DATA_MODULATION {
2243	TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0,
2244	TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1,
2245	TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2,
2246	TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3,
2247	} TMDS_CTL1_DATA_MODULATION;
2248	typedef enum TMDS_CTL1_PATTERN_OUT_EN {
2249	TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0,
2250	TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1,
2251	} TMDS_CTL1_PATTERN_OUT_EN;
2252	typedef enum TMDS_CTL2_DATA_SEL {
2253	TMDS_CTL2_DATA_SEL0_RESERVED = 0x0,
2254	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1,
2255	TMDS_CTL2_DATA_SEL2_VSYNC = 0x2,
2256	TMDS_CTL2_DATA_SEL3_RESERVED = 0x3,
2257	TMDS_CTL2_DATA_SEL4_HSYNC = 0x4,
2258	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5,
2259	TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6,
2260	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7,
2261	} TMDS_CTL2_DATA_SEL;
2262	typedef enum TMDS_CTL2_DATA_DELAY {
2263	TMDS_CTL2_DATA_DELAY_0PIX = 0x0,
2264	TMDS_CTL2_DATA_DELAY_1PIX = 0x1,
2265	TMDS_CTL2_DATA_DELAY_2PIX = 0x2,
2266	TMDS_CTL2_DATA_DELAY_3PIX = 0x3,
2267	TMDS_CTL2_DATA_DELAY_4PIX = 0x4,
2268	TMDS_CTL2_DATA_DELAY_5PIX = 0x5,
2269	TMDS_CTL2_DATA_DELAY_6PIX = 0x6,
2270	TMDS_CTL2_DATA_DELAY_7PIX = 0x7,
2271	} TMDS_CTL2_DATA_DELAY;
2272	typedef enum TMDS_CTL2_DATA_INVERT {
2273	TMDS_CTL2_DATA_NORMAL = 0x0,
2274	TMDS_CTL2_DATA_INVERT_EN = 0x1,
2275	} TMDS_CTL2_DATA_INVERT;
2276	typedef enum TMDS_CTL2_DATA_MODULATION {
2277	TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0,
2278	TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1,
2279	TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2,
2280	TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3,
2281	} TMDS_CTL2_DATA_MODULATION;
2282	typedef enum TMDS_CTL2_PATTERN_OUT_EN {
2283	TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0,
2284	TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1,
2285	} TMDS_CTL2_PATTERN_OUT_EN;
2286	typedef enum TMDS_CTL3_DATA_DELAY {
2287	TMDS_CTL3_DATA_DELAY_0PIX = 0x0,
2288	TMDS_CTL3_DATA_DELAY_1PIX = 0x1,
2289	TMDS_CTL3_DATA_DELAY_2PIX = 0x2,
2290	TMDS_CTL3_DATA_DELAY_3PIX = 0x3,
2291	TMDS_CTL3_DATA_DELAY_4PIX = 0x4,
2292	TMDS_CTL3_DATA_DELAY_5PIX = 0x5,
2293	TMDS_CTL3_DATA_DELAY_6PIX = 0x6,
2294	TMDS_CTL3_DATA_DELAY_7PIX = 0x7,
2295	} TMDS_CTL3_DATA_DELAY;
2296	typedef enum TMDS_CTL3_DATA_INVERT {
2297	TMDS_CTL3_DATA_NORMAL = 0x0,
2298	TMDS_CTL3_DATA_INVERT_EN = 0x1,
2299	} TMDS_CTL3_DATA_INVERT;
2300	typedef enum TMDS_CTL3_DATA_MODULATION {
2301	TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0,
2302	TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1,
2303	TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2,
2304	TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3,
2305	} TMDS_CTL3_DATA_MODULATION;
2306	typedef enum TMDS_CTL3_PATTERN_OUT_EN {
2307	TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0,
2308	TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1,
2309	} TMDS_CTL3_PATTERN_OUT_EN;
2310	typedef enum TMDS_CTL3_DATA_SEL {
2311	TMDS_CTL3_DATA_SEL0_RESERVED = 0x0,
2312	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1,
2313	TMDS_CTL3_DATA_SEL2_VSYNC = 0x2,
2314	TMDS_CTL3_DATA_SEL3_RESERVED = 0x3,
2315	TMDS_CTL3_DATA_SEL4_HSYNC = 0x4,
2316	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5,
2317	TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6,
2318	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7,
2319	} TMDS_CTL3_DATA_SEL;
2320	typedef enum DIG_FE_CNTL_SOURCE_SELECT {
2321	DIG_FE_SOURCE_FROM_FMT0 = 0x0,
2322	DIG_FE_SOURCE_FROM_FMT1 = 0x1,
2323	DIG_FE_SOURCE_FROM_FMT2 = 0x2,
2324	DIG_FE_SOURCE_FROM_FMT3 = 0x3,
2325	} DIG_FE_CNTL_SOURCE_SELECT;
2326	typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
2327	DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0,
2328	DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1,
2329	DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2,
2330	DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3,
2331	} DIG_FE_CNTL_STEREOSYNC_SELECT;
2332	typedef enum DIG_FIFO_READ_CLOCK_SRC {
2333	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0,
2334	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1,
2335	} DIG_FIFO_READ_CLOCK_SRC;
2336	typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
2337	DIG_OUTPUT_CRC_ON_LINK0 = 0x0,
2338	DIG_OUTPUT_CRC_ON_LINK1 = 0x1,
2339	} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
2340	typedef enum DIG_OUTPUT_CRC_DATA_SEL {
2341	DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0,
2342	DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1,
2343	DIG_OUTPUT_CRC_FOR_VBI = 0x2,
2344	DIG_OUTPUT_CRC_FOR_AUDIO = 0x3,
2345	} DIG_OUTPUT_CRC_DATA_SEL;
2346	typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
2347	DIG_IN_NORMAL_OPERATION = 0x0,
2348	DIG_IN_DEBUG_MODE = 0x1,
2349	} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
2350	typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
2351	DIG_10BIT_TEST_PATTERN = 0x0,
2352	DIG_ALTERNATING_TEST_PATTERN = 0x1,
2353	} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
2354	typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
2355	DIG_TEST_PATTERN_NORMAL = 0x0,
2356	DIG_TEST_PATTERN_RANDOM = 0x1,
2357	} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
2358	typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
2359	DIG_RANDOM_PATTERN_ENABLED = 0x0,
2360	DIG_RANDOM_PATTERN_RESETED = 0x1,
2361	} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
2362	typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
2363	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0,
2364	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1,
2365	} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
2366	typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
2367	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0,
2368	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1,
2369	} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
2370	typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
2371	DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0,
2372	DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1,
2373	} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
2374	typedef enum DIG_FIFO_ERROR_ACK {
2375	DIG_FIFO_ERROR_ACK_INT = 0x0,
2376	DIG_FIFO_ERROR_NOT_ACK = 0x1,
2377	} DIG_FIFO_ERROR_ACK;
2378	typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
2379	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0,
2380	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1,
2381	} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
2382	typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
2383	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0,
2384	DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1,
2385	} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
2386	typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
2387	DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0,
2388	DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1,
2389	} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
2390	typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
2391	DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0,
2392	DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1,
2393	} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
2394	typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
2395	DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0,
2396	DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1,
2397	} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
2398	typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
2399	AFMT_INTERRUPT_DISABLE = 0x0,
2400	AFMT_INTERRUPT_ENABLE = 0x1,
2401	} AFMT_INTERRUPT_STATUS_CHG_MASK;
2402	typedef enum HDMI_GC_AVMUTE {
2403	HDMI_GC_AVMUTE_SET = 0x0,
2404	HDMI_GC_AVMUTE_UNSET = 0x1,
2405	} HDMI_GC_AVMUTE;
2406	typedef enum HDMI_DEFAULT_PAHSE {
2407	HDMI_DEFAULT_PHASE_IS_0 = 0x0,
2408	HDMI_DEFAULT_PHASE_IS_1 = 0x1,
2409	} HDMI_DEFAULT_PAHSE;
2410	typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
2411	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
2412	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1,
2413	} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
2414	typedef enum AUDIO_LAYOUT_SELECT {
2415	AUDIO_LAYOUT_0 = 0x0,
2416	AUDIO_LAYOUT_1 = 0x1,
2417	} AUDIO_LAYOUT_SELECT;
2418	typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
2419	AFMT_AUDIO_CRC_ONESHOT = 0x0,
2420	AFMT_AUDIO_CRC_AUTO_RESTART = 0x1,
2421	} AFMT_AUDIO_CRC_CONTROL_CONT;
2422	typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
2423	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0,
2424	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1,
2425	} AFMT_AUDIO_CRC_CONTROL_SOURCE;
2426	typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
2427	AFMT_AUDIO_CRC_CH0_SIG = 0x0,
2428	AFMT_AUDIO_CRC_CH1_SIG = 0x1,
2429	AFMT_AUDIO_CRC_CH2_SIG = 0x2,
2430	AFMT_AUDIO_CRC_CH3_SIG = 0x3,
2431	AFMT_AUDIO_CRC_CH4_SIG = 0x4,
2432	AFMT_AUDIO_CRC_CH5_SIG = 0x5,
2433	AFMT_AUDIO_CRC_CH6_SIG = 0x6,
2434	AFMT_AUDIO_CRC_CH7_SIG = 0x7,
2435	AFMT_AUDIO_CRC_RESERVED = 0x8,
2436	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9,
2437	} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
2438	typedef enum AFMT_RAMP_CONTROL0_SIGN {
2439	AFMT_RAMP_SIGNED = 0x0,
2440	AFMT_RAMP_UNSIGNED = 0x1,
2441	} AFMT_RAMP_CONTROL0_SIGN;
2442	typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
2443	AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0,
2444	AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1,
2445	} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
2446	typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
2447	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
2448	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1,
2449	} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
2450	typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
2451	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0,
2452	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1,
2453	} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
2454	typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
2455	AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0,
2456	AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1,
2457	AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2,
2458	AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3,
2459	AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4,
2460	AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5,
2461	AFMT_AUDIO_SRC_RESERVED = 0x6,
2462	} AFMT_AUDIO_SRC_CONTROL_SELECT;
2463	typedef enum DIG_BE_CNTL_MODE {
2464	DIG_BE_DP_SST_MODE = 0x0,
2465	DIG_BE_RESERVED1 = 0x1,
2466	DIG_BE_TMDS_DVI_MODE = 0x2,
2467	DIG_BE_TMDS_HDMI_MODE = 0x3,
2468	DIG_BE_SDVO_RESERVED = 0x4,
2469	DIG_BE_DP_MST_MODE = 0x5,
2470	DIG_BE_RESERVED2 = 0x6,
2471	DIG_BE_RESERVED3 = 0x7,
2472	} DIG_BE_CNTL_MODE;
2473	typedef enum DIG_BE_CNTL_HPD_SELECT {
2474	DIG_BE_CNTL_HPD1 = 0x0,
2475	DIG_BE_CNTL_HPD2 = 0x1,
2476	DIG_BE_CNTL_HPD3 = 0x2,
2477	DIG_BE_CNTL_HPD4 = 0x3,
2478	DIG_BE_CNTL_HPD5 = 0x4,
2479	DIG_BE_CNTL_HPD6 = 0x5,
2480	} DIG_BE_CNTL_HPD_SELECT;
2481	typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
2482	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0,
2483	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1,
2484	} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
2485	typedef enum TMDS_SYNC_PHASE {
2486	TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0,
2487	TMDS_SYNC_PHASE_ON_FRAME_START = 0x1,
2488	} TMDS_SYNC_PHASE;
2489	typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
2490	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0,
2491	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1,
2492	} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
2493	typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
2494	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0,
2495	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1,
2496	} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
2497	typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
2498	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0,
2499	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1,
2500	} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
2501	typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
2502	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0,
2503	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1,
2504	} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
2505	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
2506	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0,
2507	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
2508	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2,
2509	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3,
2510	} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
2511	typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
2512	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0,
2513	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1,
2514	} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
2515	typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
2516	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0,
2517	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1,
2518	} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
2519	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
2520	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0,
2521	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1,
2522	} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
2523	typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
2524	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0,
2525	TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1,
2526	} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
2527	typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
2528	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0,
2529	TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1,
2530	} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
2531	typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
2532	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0,
2533	TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1,
2534	} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
2535	typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
2536	TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0,
2537	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1,
2538	} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
2539	typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
2540	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0,
2541	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1,
2542	} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
2543	typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
2544	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0,
2545	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1,
2546	} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
2547	typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
2548	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0,
2549	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1,
2550	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2,
2551	TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3,
2552	} TMDS_REG_TEST_OUTPUTA_CNTLA;
2553	typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
2554	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0,
2555	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1,
2556	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2,
2557	TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3,
2558	} TMDS_REG_TEST_OUTPUTB_CNTLB;
2559	typedef enum DP_LINK_TRAINING_COMPLETE {
2560	DP_LINK_TRAINING_NOT_COMPLETE = 0x0,
2561	DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1,
2562	} DP_LINK_TRAINING_COMPLETE;
2563	typedef enum DP_EMBEDDED_PANEL_MODE {
2564	DP_EXTERNAL_PANEL = 0x0,
2565	DP_EMBEDDED_PANEL = 0x1,
2566	} DP_EMBEDDED_PANEL_MODE;
2567	typedef enum DP_PIXEL_ENCODING {
2568	DP_PIXEL_ENCODING_RGB444 = 0x0,
2569	DP_PIXEL_ENCODING_YCBCR422 = 0x1,
2570	DP_PIXEL_ENCODING_YCBCR444 = 0x2,
2571	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3,
2572	DP_PIXEL_ENCODING_Y_ONLY = 0x4,
2573	DP_PIXEL_ENCODING_RESERVED = 0x5,
2574	} DP_PIXEL_ENCODING;
2575	typedef enum DP_DYN_RANGE {
2576	DP_DYN_VESA_RANGE = 0x0,
2577	DP_DYN_CEA_RANGE = 0x1,
2578	} DP_DYN_RANGE;
2579	typedef enum DP_YCBCR_RANGE {
2580	DP_YCBCR_RANGE_BT601_5 = 0x0,
2581	DP_YCBCR_RANGE_BT709_5 = 0x1,
2582	} DP_YCBCR_RANGE;
2583	typedef enum DP_COMPONENT_DEPTH {
2584	DP_COMPONENT_DEPTH_6BPC = 0x0,
2585	DP_COMPONENT_DEPTH_8BPC = 0x1,
2586	DP_COMPONENT_DEPTH_10BPC = 0x2,
2587	DP_COMPONENT_DEPTH_12BPC = 0x3,
2588	DP_COMPONENT_DEPTH_16BPC = 0x4,
2589	DP_COMPONENT_DEPTH_RESERVED = 0x5,
2590	} DP_COMPONENT_DEPTH;
2591	typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
2592	MSA_MISC0_OVERRIDE_DISABLE = 0x0,
2593	MSA_MISC0_OVERRIDE_ENABLE = 0x1,
2594	} DP_MSA_MISC0_OVERRIDE_ENABLE;
2595	typedef enum DP_UDI_LANES {
2596	DP_UDI_1_LANE = 0x0,
2597	DP_UDI_2_LANES = 0x1,
2598	DP_UDI_LANES_RESERVED = 0x2,
2599	DP_UDI_4_LANES = 0x3,
2600	} DP_UDI_LANES;
2601	typedef enum DP_VID_STREAM_DIS_DEFER {
2602	DP_VID_STREAM_DIS_NO_DEFER = 0x0,
2603	DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1,
2604	DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2,
2605	} DP_VID_STREAM_DIS_DEFER;
2606	typedef enum DP_STEER_OVERFLOW_ACK {
2607	DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0,
2608	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
2609	} DP_STEER_OVERFLOW_ACK;
2610	typedef enum DP_STEER_OVERFLOW_MASK {
2611	DP_STEER_OVERFLOW_MASKED = 0x0,
2612	DP_STEER_OVERFLOW_UNMASK = 0x1,
2613	} DP_STEER_OVERFLOW_MASK;
2614	typedef enum DP_TU_OVERFLOW_ACK {
2615	DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0,
2616	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
2617	} DP_TU_OVERFLOW_ACK;
2618	typedef enum DP_VID_TIMING_MODE {
2619	DP_VID_TIMING_MODE_ASYNC = 0x0,
2620	DP_VID_TIMING_MODE_SYNC = 0x1,
2621	} DP_VID_TIMING_MODE;
2622	typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
2623	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0,
2624	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1,
2625	} DP_VID_M_N_DOUBLE_BUFFER_MODE;
2626	typedef enum DP_VID_M_N_GEN_EN {
2627	DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0,
2628	DP_VID_M_N_CALC_AUTO = 0x1,
2629	} DP_VID_M_N_GEN_EN;
2630	typedef enum DP_VID_ENHANCED_FRAME_MODE {
2631	VID_NORMAL_FRAME_MODE = 0x0,
2632	VID_ENHANCED_MODE = 0x1,
2633	} DP_VID_ENHANCED_FRAME_MODE;
2634	typedef enum DP_VID_MSA_TOP_FIELD_MODE {
2635	DP_TOP_FIELD_ONLY = 0x0,
2636	DP_TOP_PLUS_BOTTOM_FIELD = 0x1,
2637	} DP_VID_MSA_TOP_FIELD_MODE;
2638	typedef enum DP_VID_VBID_FIELD_POL {
2639	DP_VID_VBID_FIELD_POL_NORMAL = 0x0,
2640	DP_VID_VBID_FIELD_POL_INV = 0x1,
2641	} DP_VID_VBID_FIELD_POL;
2642	typedef enum DP_VID_STREAM_DISABLE_ACK {
2643	ID_STREAM_DISABLE_NO_ACK = 0x0,
2644	ID_STREAM_DISABLE_ACKED = 0x1,
2645	} DP_VID_STREAM_DISABLE_ACK;
2646	typedef enum DP_VID_STREAM_DISABLE_MASK {
2647	VID_STREAM_DISABLE_MASKED = 0x0,
2648	VID_STREAM_DISABLE_UNMASK = 0x1,
2649	} DP_VID_STREAM_DISABLE_MASK;
2650	typedef enum DPHY_ATEST_SEL_LANE0 {
2651	DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0,
2652	DPHY_ATEST_LANE0_REG_PATTERN = 0x1,
2653	} DPHY_ATEST_SEL_LANE0;
2654	typedef enum DPHY_ATEST_SEL_LANE1 {
2655	DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0,
2656	DPHY_ATEST_LANE1_REG_PATTERN = 0x1,
2657	} DPHY_ATEST_SEL_LANE1;
2658	typedef enum DPHY_ATEST_SEL_LANE2 {
2659	DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0,
2660	DPHY_ATEST_LANE2_REG_PATTERN = 0x1,
2661	} DPHY_ATEST_SEL_LANE2;
2662	typedef enum DPHY_ATEST_SEL_LANE3 {
2663	DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0,
2664	DPHY_ATEST_LANE3_REG_PATTERN = 0x1,
2665	} DPHY_ATEST_SEL_LANE3;
2666	typedef enum DPHY_BYPASS {
2667	DPHY_8B10B_OUTPUT = 0x0,
2668	DPHY_DBG_OUTPUT = 0x1,
2669	} DPHY_BYPASS;
2670	typedef enum DPHY_SKEW_BYPASS {
2671	DPHY_WITH_SKEW = 0x0,
2672	DPHY_NO_SKEW = 0x1,
2673	} DPHY_SKEW_BYPASS;
2674	typedef enum DPHY_TRAINING_PATTERN_SEL {
2675	DPHY_TRAINING_PATTERN_1 = 0x0,
2676	DPHY_TRAINING_PATTERN_2 = 0x1,
2677	DPHY_TRAINING_PATTERN_3 = 0x2,
2678	} DPHY_TRAINING_PATTERN_SEL;
2679	typedef enum DPHY_8B10B_RESET {
2680	DPHY_8B10B_NOT_RESET = 0x0,
2681	DPHY_8B10B_RESETET = 0x1,
2682	} DPHY_8B10B_RESET;
2683	typedef enum DP_DPHY_8B10B_EXT_DISP {
2684	DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0,
2685	DP_DPHY_8B10B_EXT_DISP_ONE = 0x1,
2686	} DP_DPHY_8B10B_EXT_DISP;
2687	typedef enum DPHY_8B10B_CUR_DISP {
2688	DPHY_8B10B_CUR_DISP_ZERO = 0x0,
2689	DPHY_8B10B_CUR_DISP_ONE = 0x1,
2690	} DPHY_8B10B_CUR_DISP;
2691	typedef enum DPHY_PRBS_EN {
2692	DPHY_PRBS_DISABLE = 0x0,
2693	DPHY_PRBS_ENABLE = 0x1,
2694	} DPHY_PRBS_EN;
2695	typedef enum DPHY_PRBS_SEL {
2696	DPHY_PRBS7_SELECTED = 0x0,
2697	DPHY_PRBS23_SELECTED = 0x1,
2698	DPHY_PRBS11_SELECTED = 0x2,
2699	} DPHY_PRBS_SEL;
2700	typedef enum DPHY_LOAD_BS_COUNT_START {
2701	DPHY_LOAD_BS_COUNT_STARTED = 0x0,
2702	DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1,
2703	} DPHY_LOAD_BS_COUNT_START;
2704	typedef enum DPHY_CRC_EN {
2705	DPHY_CRC_DISABLED = 0x0,
2706	DPHY_CRC_ENABLED = 0x1,
2707	} DPHY_CRC_EN;
2708	typedef enum DPHY_CRC_CONT_EN {
2709	DPHY_CRC_ONE_SHOT = 0x0,
2710	DPHY_CRC_CONTINUOUS = 0x1,
2711	} DPHY_CRC_CONT_EN;
2712	typedef enum DPHY_CRC_FIELD {
2713	DPHY_CRC_START_FROM_TOP_FIELD = 0x0,
2714	DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1,
2715	} DPHY_CRC_FIELD;
2716	typedef enum DPHY_CRC_SEL {
2717	DPHY_CRC_LANE0_SELECTED = 0x0,
2718	DPHY_CRC_LANE1_SELECTED = 0x1,
2719	DPHY_CRC_LANE2_SELECTED = 0x2,
2720	DPHY_CRC_LANE3_SELECTED = 0x3,
2721	} DPHY_CRC_SEL;
2722	typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
2723	DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0,
2724	DPHY_FAST_TRAINING_CAPABLE = 0x1,
2725	} DPHY_RX_FAST_TRAINING_CAPABLE;
2726	typedef enum DP_SEC_COLLISION_ACK {
2727	DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0,
2728	DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1,
2729	} DP_SEC_COLLISION_ACK;
2730	typedef enum DP_SEC_AUDIO_MUTE {
2731	DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0,
2732	DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1,
2733	} DP_SEC_AUDIO_MUTE;
2734	typedef enum DP_SEC_TIMESTAMP_MODE {
2735	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0,
2736	DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1,
2737	} DP_SEC_TIMESTAMP_MODE;
2738	typedef enum DP_SEC_ASP_PRIORITY {
2739	DP_SEC_ASP_LOW_PRIORITY = 0x0,
2740	DP_SEC_ASP_HIGH_PRIORITY = 0x1,
2741	} DP_SEC_ASP_PRIORITY;
2742	typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
2743	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0,
2744	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1,
2745	} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
2746	typedef enum DP_MSE_SAT_UPDATE_ACT {
2747	DP_MSE_SAT_UPDATE_NO_ACTION = 0x0,
2748	DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1,
2749	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2,
2750	} DP_MSE_SAT_UPDATE_ACT;
2751	typedef enum DP_MSE_LINK_LINE {
2752	DP_MSE_LINK_LINE_32_MTP_LONG = 0x0,
2753	DP_MSE_LINK_LINE_64_MTP_LONG = 0x1,
2754	DP_MSE_LINK_LINE_128_MTP_LONG = 0x2,
2755	DP_MSE_LINK_LINE_256_MTP_LONG = 0x3,
2756	} DP_MSE_LINK_LINE;
2757	typedef enum DP_MSE_BLANK_CODE {
2758	DP_MSE_BLANK_CODE_SF_FILLED = 0x0,
2759	DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1,
2760	} DP_MSE_BLANK_CODE;
2761	typedef enum DP_MSE_TIMESTAMP_MODE {
2762	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0,
2763	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1,
2764	} DP_MSE_TIMESTAMP_MODE;
2765	typedef enum DP_MSE_ZERO_ENCODER {
2766	DP_MSE_NOT_ZERO_FE_ENCODER = 0x0,
2767	DP_MSE_ZERO_FE_ENCODER = 0x1,
2768	} DP_MSE_ZERO_ENCODER;
2769	typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
2770	DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0,
2771	DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1,
2772	} DP_MSE_OUTPUT_DPDBG_DATA;
2773	typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
2774	DP_DPHY_HBR2_PASS_THROUGH = 0x0,
2775	DP_DPHY_HBR2_PATTERN_1 = 0x1,
2776	DP_DPHY_HBR2_PATTERN_2_NEG = 0x2,
2777	DP_DPHY_HBR2_PATTERN_3 = 0x3,
2778	DP_DPHY_HBR2_PATTERN_2_POS = 0x6,
2779	} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
2780	typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
2781	DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0,
2782	DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1,
2783	} DPHY_CRC_MST_PHASE_ERROR_ACK;
2784	typedef enum DPHY_SW_FAST_TRAINING_START {
2785	DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0,
2786	DPHY_SW_FAST_TRAINING_STARTED = 0x1,
2787	} DPHY_SW_FAST_TRAINING_START;
2788	typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
2789	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
2790	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
2791	} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
2792	typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
2793	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0,
2794	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1,
2795	} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
2796	typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
2797	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0,
2798	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1,
2799	} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
2800	typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
2801	MSA_V_TIMING_OVERRIDE_DISABLED = 0x0,
2802	MSA_V_TIMING_OVERRIDE_ENABLED = 0x1,
2803	} DP_MSA_V_TIMING_OVERRIDE_EN;
2804	typedef enum DP_SEC_GSP0_PRIORITY {
2805	SEC_GSP0_PRIORITY_LOW = 0x0,
2806	SEC_GSP0_PRIORITY_HIGH = 0x1,
2807	} DP_SEC_GSP0_PRIORITY;
2808	typedef enum DP_SEC_GSP0_SEND {
2809	NOT_SENT = 0x0,
2810	FORCE_SENT = 0x1,
2811	} DP_SEC_GSP0_SEND;
2812	typedef enum DP_AUX_CONTROL_HPD_SEL {
2813	DP_AUX_CONTROL_HPD1_SELECTED = 0x0,
2814	DP_AUX_CONTROL_HPD2_SELECTED = 0x1,
2815	DP_AUX_CONTROL_HPD3_SELECTED = 0x2,
2816	DP_AUX_CONTROL_HPD4_SELECTED = 0x3,
2817	DP_AUX_CONTROL_HPD5_SELECTED = 0x4,
2818	DP_AUX_CONTROL_HPD6_SELECTED = 0x5,
2819	} DP_AUX_CONTROL_HPD_SEL;
2820	typedef enum DP_AUX_CONTROL_TEST_MODE {
2821	DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0,
2822	DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1,
2823	} DP_AUX_CONTROL_TEST_MODE;
2824	typedef enum DP_AUX_SW_CONTROL_SW_GO {
2825	DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0,
2826	DP_AUX_SW_CONTROL_SW__GO = 0x1,
2827	} DP_AUX_SW_CONTROL_SW_GO;
2828	typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
2829	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0,
2830	DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1,
2831	} DP_AUX_SW_CONTROL_LS_READ_TRIG;
2832	typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
2833	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0,
2834	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1,
2835	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2,
2836	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3,
2837	} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
2838	typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
2839	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0,
2840	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1,
2841	} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
2842	typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
2843	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0,
2844	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1,
2845	} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
2846	typedef enum DP_AUX_INT_ACK {
2847	DP_AUX_INT__NOT_ACK = 0x0,
2848	DP_AUX_INT__ACK = 0x1,
2849	} DP_AUX_INT_ACK;
2850	typedef enum DP_AUX_LS_UPDATE_ACK {
2851	DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0,
2852	DP_AUX_INT_LS_UPDATE_ACK = 0x1,
2853	} DP_AUX_LS_UPDATE_ACK;
2854	typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
2855	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
2856	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
2857	} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
2858	typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
2859	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0,
2860	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1,
2861	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2,
2862	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3,
2863	} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
2864	typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
2865	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0,
2866	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1,
2867	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2,
2868	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3,
2869	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4,
2870	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5,
2871	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6,
2872	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7,
2873	} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
2874	typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
2875	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0,
2876	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
2877	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
2878	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
2879	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
2880	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
2881	} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
2882	typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
2883	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
2884	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
2885	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
2886	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
2887	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
2888	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
2889	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
2890	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
2891	} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
2892	typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
2893	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
2894	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
2895	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
2896	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
2897	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
2898	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
2899	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
2900	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
2901	} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
2902	typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
2903	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
2904	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
2905	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
2906	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
2907	} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
2908	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
2909	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
2910	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
2911	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
2912	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
2913	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
2914	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
2915	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
2916	typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
2917	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
2918	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
2919	} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
2920	typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
2921	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
2922	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
2923	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
2924	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
2925	} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
2926	typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
2927	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0,
2928	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1,
2929	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2,
2930	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3,
2931	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4,
2932	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5,
2933	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6,
2934	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7,
2935	} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
2936	typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
2937	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0,
2938	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1,
2939	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2,
2940	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3,
2941	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4,
2942	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5,
2943	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6,
2944	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7,
2945	} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
2946	typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
2947	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
2948	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
2949	} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
2950	typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
2951	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
2952	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
2953	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
2954	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
2955	} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
2956	typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
2957	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
2958	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
2959	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
2960	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
2961	} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
2962	typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
2963	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
2964	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
2965	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
2966	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
2967	} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
2968	typedef enum DP_AUX_ERR_OCCURRED_ACK {
2969	DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0,
2970	DP_AUX_ERR_OCCURRED__ACK = 0x1,
2971	} DP_AUX_ERR_OCCURRED_ACK;
2972	typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
2973	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0,
2974	DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1,
2975	} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
2976	typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
2977	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0,
2978	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1,
2979	} DP_AUX_DEFINITE_ERR_REACHED_ACK;
2980	typedef enum DP_AUX_RESET {
2981	DP_AUX_RESET_DEASSERTED = 0x0,
2982	DP_AUX_RESET_ASSERTED = 0x1,
2983	} DP_AUX_RESET;
2984	typedef enum DP_AUX_RESET_DONE {
2985	DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0,
2986	DP_AUX_RESET_SEQUENCE_DONE = 0x1,
2987	} DP_AUX_RESET_DONE;
2988	typedef enum FMT_CONTROL_PIXEL_ENCODING {
2989	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0,
2990	FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1,
2991	} FMT_CONTROL_PIXEL_ENCODING;
2992	typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
2993	FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0,
2994	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1,
2995	} FMT_CONTROL_SUBSAMPLING_MODE;
2996	typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
2997	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0,
2998	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1,
2999	} FMT_CONTROL_SUBSAMPLING_ORDER;
3000	typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3001	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0,
3002	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1,
3003	} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3004	typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3005	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0,
3006	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1,
3007	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2,
3008	} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3009	typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3010	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
3011	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
3012	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
3013	} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3014	typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3015	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
3016	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
3017	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
3018	} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3019	typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3020	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
3021	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
3022	} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3023	typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3024	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0,
3025	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1,
3026	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2,
3027	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3,
3028	} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3029	typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3030	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0,
3031	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1,
3032	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2,
3033	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3,
3034	} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3035	typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3036	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0,
3037	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1,
3038	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2,
3039	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3,
3040	} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3041	typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3042	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
3043	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
3044	} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3045	typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3046	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
3047	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
3048	} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3049	typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3050	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0,
3051	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1,
3052	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2,
3053	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0 = 0x3,
3054	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4,
3055	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5,
3056	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6,
3057	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7,
3058	} FMT_CLAMP_CNTL_COLOR_FORMAT;
3059	typedef enum FMT_CRC_CNTL_CONT_EN {
3060	FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0,
3061	FMT_CRC_CNTL_CONT_EN_CONT = 0x1,
3062	} FMT_CRC_CNTL_CONT_EN;
3063	typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3064	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0,
3065	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1,
3066	} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3067	typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3068	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0,
3069	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1,
3070	} FMT_CRC_CNTL_ONLY_BLANKB;
3071	typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3072	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0,
3073	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1,
3074	} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3075	typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3076	FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0,
3077	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1,
3078	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2,
3079	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3,
3080	} FMT_CRC_CNTL_INTERLACE_MODE;
3081	typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3082	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0,
3083	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1,
3084	} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3085	typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3086	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0,
3087	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1,
3088	} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3089	typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3090	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0,
3091	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1,
3092	FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2,
3093	FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3,
3094	} FMT_DEBUG_CNTL_COLOR_SELECT;
3095	typedef enum FMT_SPATIAL_DITHER_MODE {
3096	FMT_SPATIAL_DITHER_MODE_0 = 0x0,
3097	FMT_SPATIAL_DITHER_MODE_1 = 0x1,
3098	FMT_SPATIAL_DITHER_MODE_2 = 0x2,
3099	FMT_SPATIAL_DITHER_MODE_3 = 0x3,
3100	} FMT_SPATIAL_DITHER_MODE;
3101	typedef enum FMT_STEREOSYNC_OVR_POL {
3102	FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0,
3103	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1,
3104	} FMT_STEREOSYNC_OVR_POL;
3105	typedef enum FMT_DYNAMIC_EXP_MODE {
3106	FMT_DYNAMIC_EXP_MODE_10to12 = 0x0,
3107	FMT_DYNAMIC_EXP_MODE_8to12 = 0x1,
3108	} FMT_DYNAMIC_EXP_MODE;
3109	typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3110	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0,
3111	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1,
3112	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2,
3113	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3,
3114	} LB_DATA_FORMAT_PIXEL_DEPTH;
3115	typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3116	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
3117	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
3118	} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3119	typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3120	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
3121	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1,
3122	} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3123	typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3124	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
3125	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
3126	} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3127	typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3128	LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0,
3129	LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1,
3130	} LB_DATA_FORMAT_INTERLEAVE_EN;
3131	typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3132	LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0,
3133	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1,
3134	} LB_DATA_FORMAT_REQUEST_MODE;
3135	typedef enum LB_DATA_FORMAT_ALPHA_EN {
3136	LB_DATA_FORMAT_ALPHA_DISABLE = 0x0,
3137	LB_DATA_FORMAT_ALPHA_ENABLE = 0x1,
3138	} LB_DATA_FORMAT_ALPHA_EN;
3139	typedef enum LB_VLINE_START_END_VLINE_INV {
3140	LB_VLINE_START_END_VLINE_NORMAL = 0x0,
3141	LB_VLINE_START_END_VLINE_INVERSE = 0x1,
3142	} LB_VLINE_START_END_VLINE_INV;
3143	typedef enum LB_VLINE2_START_END_VLINE2_INV {
3144	LB_VLINE2_START_END_VLINE2_NORMAL = 0x0,
3145	LB_VLINE2_START_END_VLINE2_INVERSE = 0x1,
3146	} LB_VLINE2_START_END_VLINE2_INV;
3147	typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3148	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0,
3149	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1,
3150	} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3151	typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3152	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0,
3153	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1,
3154	} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3155	typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3156	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0,
3157	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1,
3158	} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3159	typedef enum LB_VLINE_STATUS_VLINE_ACK {
3160	LB_VLINE_STATUS_VLINE_NORMAL = 0x0,
3161	LB_VLINE_STATUS_VLINE_CLEAR = 0x1,
3162	} LB_VLINE_STATUS_VLINE_ACK;
3163	typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3164	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
3165	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
3166	} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3167	typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3168	LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0,
3169	LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1,
3170	} LB_VLINE2_STATUS_VLINE2_ACK;
3171	typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3172	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3173	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3174	} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3175	typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3176	LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0,
3177	LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1,
3178	} LB_VBLANK_STATUS_VBLANK_ACK;
3179	typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3180	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3181	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3182	} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3183	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3184	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0,
3185	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
3186	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
3187	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
3188	} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3189	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3190	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0,
3191	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1,
3192	} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3193	typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3194	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0,
3195	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1,
3196	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2,
3197	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3,
3198	} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3199	typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3200	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0,
3201	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1,
3202	} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3203	typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3204	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
3205	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
3206	} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3207	typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3208	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0,
3209	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1,
3210	} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3211	typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3212	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0,
3213	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1,
3214	} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3215	typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3216	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
3217	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
3218	} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3219	typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3220	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
3221	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
3222	} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3223	typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3224	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
3225	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
3226	} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3227	typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3228	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
3229	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
3230	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
3231	} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3232	typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3233	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
3234	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1,
3235	} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3236	typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3237	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
3238	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
3239	} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3240	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3241	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
3242	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
3243	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3244	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3245	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
3246	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
3247	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3248	typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3249	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
3250	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
3251	} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3252	typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3253	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
3254	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
3255	} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3256	typedef enum LBV_PIXEL_DEPTH {
3257	PIXEL_DEPTH_30BPP = 0x0,
3258	PIXEL_DEPTH_24BPP = 0x1,
3259	PIXEL_DEPTH_18BPP = 0x2,
3260	PIXEL_DEPTH_38BPP = 0x3,
3261	} LBV_PIXEL_DEPTH;
3262	typedef enum LBV_PIXEL_EXPAN_MODE {
3263	PIXEL_EXPAN_MODE_ZERO_EXP = 0x0,
3264	PIXEL_EXPAN_MODE_DYN_EXP = 0x1,
3265	} LBV_PIXEL_EXPAN_MODE;
3266	typedef enum LBV_INTERLEAVE_EN {
3267	INTERLEAVE_DIS = 0x0,
3268	INTERLEAVE_EN = 0x1,
3269	} LBV_INTERLEAVE_EN;
3270	typedef enum LBV_PIXEL_REDUCE_MODE {
3271	PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
3272	PIXEL_REDUCE_MODE_ROUNDING = 0x1,
3273	} LBV_PIXEL_REDUCE_MODE;
3274	typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
3275	DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
3276	DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
3277	} LBV_DYNAMIC_PIXEL_DEPTH;
3278	typedef enum LBV_DITHER_EN {
3279	DITHER_DIS = 0x0,
3280	DITHER_EN = 0x1,
3281	} LBV_DITHER_EN;
3282	typedef enum LBV_DOWNSCALE_PREFETCH_EN {
3283	DOWNSCALE_PREFETCH_DIS = 0x0,
3284	DOWNSCALE_PREFETCH_EN = 0x1,
3285	} LBV_DOWNSCALE_PREFETCH_EN;
3286	typedef enum LBV_MEMORY_CONFIG {
3287	MEMORY_CONFIG_0 = 0x0,
3288	MEMORY_CONFIG_1 = 0x1,
3289	MEMORY_CONFIG_2 = 0x2,
3290	MEMORY_CONFIG_3 = 0x3,
3291	} LBV_MEMORY_CONFIG;
3292	typedef enum LBV_SYNC_RESET_SEL2 {
3293	SYNC_RESET_SEL2_VBLANK = 0x0,
3294	SYNC_RESET_SEL2_VSYNC = 0x1,
3295	} LBV_SYNC_RESET_SEL2;
3296	typedef enum LBV_SYNC_DURATION {
3297	SYNC_DURATION_16 = 0x0,
3298	SYNC_DURATION_32 = 0x1,
3299	SYNC_DURATION_64 = 0x2,
3300	SYNC_DURATION_128 = 0x3,
3301	} LBV_SYNC_DURATION;
3302	typedef enum SCL_C_RAM_TAP_PAIR_IDX {
3303	SCL_C_RAM_TAP_PAIR_ID0 = 0x0,
3304	SCL_C_RAM_TAP_PAIR_ID1 = 0x1,
3305	SCL_C_RAM_TAP_PAIR_ID2 = 0x2,
3306	SCL_C_RAM_TAP_PAIR_ID3 = 0x3,
3307	SCL_C_RAM_TAP_PAIR_ID4 = 0x4,
3308	} SCL_C_RAM_TAP_PAIR_IDX;
3309	typedef enum SCL_C_RAM_PHASE {
3310	SCL_C_RAM_PHASE_0 = 0x0,
3311	SCL_C_RAM_PHASE_1 = 0x1,
3312	SCL_C_RAM_PHASE_2 = 0x2,
3313	SCL_C_RAM_PHASE_3 = 0x3,
3314	SCL_C_RAM_PHASE_4 = 0x4,
3315	SCL_C_RAM_PHASE_5 = 0x5,
3316	SCL_C_RAM_PHASE_6 = 0x6,
3317	SCL_C_RAM_PHASE_7 = 0x7,
3318	SCL_C_RAM_PHASE_8 = 0x8,
3319	} SCL_C_RAM_PHASE;
3320	typedef enum SCL_C_RAM_FILTER_TYPE {
3321	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0,
3322	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1,
3323	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2,
3324	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3,
3325	SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT = 0x4,
3326	SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT = 0x5,
3327	} SCL_C_RAM_FILTER_TYPE;
3328	typedef enum SCL_MODE_SEL {
3329	SCL_MODE_SCL_BYPASS = 0x0,
3330	SCL_MODE_RGB_SCALING = 0x1,
3331	SCL_MODE_YCBCR_SCALING = 0x2,
3332	} SCL_MODE_SEL;
3333	typedef enum SCL_PSCL_EN {
3334	SCL_PSCL_DISABLE = 0x0,
3335	SCL_PSCL_ENANBLE = 0x1,
3336	} SCL_PSCL_EN;
3337	typedef enum SCL_V_NUM_OF_TAPS {
3338	SCL_V_NUM_OF_TAPS_1 = 0x0,
3339	SCL_V_NUM_OF_TAPS_2 = 0x1,
3340	SCL_V_NUM_OF_TAPS_3 = 0x2,
3341	SCL_V_NUM_OF_TAPS_4 = 0x3,
3342	SCL_V_NUM_OF_TAPS_5 = 0x4,
3343	SCL_V_NUM_OF_TAPS_6 = 0x5,
3344	} SCL_V_NUM_OF_TAPS;
3345	typedef enum SCL_H_NUM_OF_TAPS {
3346	SCL_H_NUM_OF_TAPS_1 = 0x0,
3347	SCL_H_NUM_OF_TAPS_2 = 0x1,
3348	SCL_H_NUM_OF_TAPS_4 = 0x3,
3349	SCL_H_NUM_OF_TAPS_6 = 0x5,
3350	SCL_H_NUM_OF_TAPS_8 = 0x7,
3351	SCL_H_NUM_OF_TAPS_10 = 0x9,
3352	} SCL_H_NUM_OF_TAPS;
3353	typedef enum SCL_BOUNDARY_MODE {
3354	SCL_BOUNDARY_MODE_BLACK = 0x0,
3355	SCL_BOUNDARY_MODE_EDGE = 0x1,
3356	} SCL_BOUNDARY_MODE;
3357	typedef enum SCL_EARLY_EOL_MOD {
3358	SCL_EARLY_EOL_MODE_CRTC = 0x0,
3359	SCL_EARLY_EOL_MODE_INTERNAL = 0x1,
3360	} SCL_EARLY_EOL_MOD;
3361	typedef enum SCL_BYPASS_MODE {
3362	SCL_BYPASS_MODE_MC_MR = 0x0,
3363	SCL_BYPASS_MODE_AC_NR = 0x1,
3364	SCL_BYPASS_MODE_AC_AR = 0x2,
3365	SCL_BYPASS_MODE_RESERVED = 0x3,
3366	} SCL_BYPASS_MODE;
3367	typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
3368	SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0,
3369	SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1,
3370	SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2,
3371	SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3,
3372	SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4,
3373	SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5,
3374	SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6,
3375	SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7,
3376	SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8,
3377	SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9,
3378	SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa,
3379	SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb,
3380	SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc,
3381	SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd,
3382	SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe,
3383	SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf,
3384	} SCL_V_MANUAL_REPLICATE_FACTOR;
3385	typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
3386	SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0,
3387	SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1,
3388	SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2,
3389	SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3,
3390	SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4,
3391	SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5,
3392	SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6,
3393	SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7,
3394	SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8,
3395	SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9,
3396	SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa,
3397	SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb,
3398	SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc,
3399	SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd,
3400	SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe,
3401	SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf,
3402	} SCL_H_MANUAL_REPLICATE_FACTOR;
3403	typedef enum SCL_V_CALC_AUTO_RATIO_EN {
3404	SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0,
3405	SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1,
3406	} SCL_V_CALC_AUTO_RATIO_EN;
3407	typedef enum SCL_H_CALC_AUTO_RATIO_EN {
3408	SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0,
3409	SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1,
3410	} SCL_H_CALC_AUTO_RATIO_EN;
3411	typedef enum SCL_H_FILTER_PICK_NEAREST {
3412	SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0,
3413	SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1,
3414	} SCL_H_FILTER_PICK_NEAREST;
3415	typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
3416	SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0,
3417	SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1,
3418	} SCL_H_2TAP_HARDCODE_COEF_EN;
3419	typedef enum SCL_V_FILTER_PICK_NEAREST {
3420	SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0,
3421	SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1,
3422	} SCL_V_FILTER_PICK_NEAREST;
3423	typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
3424	SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0,
3425	SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1,
3426	} SCL_V_2TAP_HARDCODE_COEF_EN;
3427	typedef enum SCL_UPDATE_TAKEN {
3428	SCL_UPDATE_TAKEN_NO = 0x0,
3429	SCL_UPDATE_TAKEN_YES = 0x1,
3430	} SCL_UPDATE_TAKEN;
3431	typedef enum SCL_UPDATE_LOCK {
3432	SCL_UPDATE_UNLOCKED = 0x0,
3433	SCL_UPDATE_LOCKED = 0x1,
3434	} SCL_UPDATE_LOCK;
3435	typedef enum SCL_COEF_UPDATE_COMPLETE {
3436	SCL_COEF_UPDATE_NOT_COMPLETED = 0x0,
3437	SCL_COEF_UPDATE_COMPLETED = 0x1,
3438	} SCL_COEF_UPDATE_COMPLETE;
3439	typedef enum SCL_HF_SHARP_SCALE_FACTOR {
3440	SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0,
3441	SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1,
3442	SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2,
3443	SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3,
3444	SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4,
3445	SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5,
3446	SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6,
3447	SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7,
3448	} SCL_HF_SHARP_SCALE_FACTOR;
3449	typedef enum SCL_HF_SHARP_EN {
3450	SCL_HF_SHARP_DISABLE = 0x0,
3451	SCL_HF_SHARP_ENABLE = 0x1,
3452	} SCL_HF_SHARP_EN;
3453	typedef enum SCL_VF_SHARP_SCALE_FACTOR {
3454	SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0,
3455	SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1,
3456	SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2,
3457	SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3,
3458	SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4,
3459	SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5,
3460	SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6,
3461	SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7,
3462	} SCL_VF_SHARP_SCALE_FACTOR;
3463	typedef enum SCL_VF_SHARP_EN {
3464	SCL_VF_SHARP_DISABLE = 0x0,
3465	SCL_VF_SHARP_ENABLE = 0x1,
3466	} SCL_VF_SHARP_EN;
3467	typedef enum SCL_ALU_DISABLE {
3468	SCL_ALU_ENABLED = 0x0,
3469	SCL_ALU_DISABLED = 0x1,
3470	} SCL_ALU_DISABLE;
3471	typedef enum SCL_HOST_CONFLICT_MASK {
3472	SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0,
3473	SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1,
3474	} SCL_HOST_CONFLICT_MASK;
3475	typedef enum SCL_SCL_MODE_CHANGE_MASK {
3476	SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0,
3477	SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1,
3478	} SCL_SCL_MODE_CHANGE_MASK;
3479	typedef enum SCLV_INTERLACE_SOURCE {
3480	INTERLACE_SOURCE_PROGRESSIVE = 0x0,
3481	INTERLACE_SOURCE_INTERLEAVE = 0x1,
3482	INTERLACE_SOURCE_STACK = 0x2,
3483	} SCLV_INTERLACE_SOURCE;
3484	typedef enum SCLV_UPDATE_LOCK {
3485	UPDATE_UNLOCKED = 0x0,
3486	UPDATE_LOCKED = 0x1,
3487	} SCLV_UPDATE_LOCK;
3488	typedef enum SCLV_COEF_UPDATE_COMPLETE {
3489	COEF_UPDATE_NOT_COMPLETE = 0x0,
3490	COEF_UPDATE_COMPLETE = 0x1,
3491	} SCLV_COEF_UPDATE_COMPLETE;
3492	typedef enum COL_MAN_UPDATE_LOCK {
3493	COL_MAN_UPDATE_UNLOCKED = 0x0,
3494	COL_MAN_UPDATE_LOCKED = 0x1,
3495	} COL_MAN_UPDATE_LOCK;
3496	typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
3497	COL_MAN_MULTIPLE_UPDATE = 0x0,
3498	COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1,
3499	} COL_MAN_DISABLE_MULTIPLE_UPDATE;
3500	typedef enum COL_MAN_INPUTCSC_MODE {
3501	INPUTCSC_MODE_BYPASS = 0x0,
3502	INPUTCSC_MODE_A = 0x1,
3503	INPUTCSC_MODE_B = 0x2,
3504	INPUTCSC_MODE_UNITY = 0x3,
3505	} COL_MAN_INPUTCSC_MODE;
3506	typedef enum COL_MAN_INPUTCSC_TYPE {
3507	INPUTCSC_TYPE_12_0 = 0x0,
3508	INPUTCSC_TYPE_10_2 = 0x1,
3509	INPUTCSC_TYPE_8_4 = 0x2,
3510	} COL_MAN_INPUTCSC_TYPE;
3511	typedef enum COL_MAN_INPUTCSC_CONVERT {
3512	INPUTCSC_ROUND = 0x0,
3513	INPUTCSC_TRUNCATE = 0x1,
3514	} COL_MAN_INPUTCSC_CONVERT;
3515	typedef enum COL_MAN_PRESCALE_MODE {
3516	PRESCALE_MODE_BYPASS = 0x0,
3517	PRESCALE_MODE_PROGRAM = 0x1,
3518	PRESCALE_MODE_UNITY = 0x2,
3519	} COL_MAN_PRESCALE_MODE;
3520	typedef enum COL_MAN_INPUT_GAMMA_MODE {
3521	INGAMMA_MODE_BYPASS = 0x0,
3522	INGAMMA_MODE_FIX = 0x1,
3523	INGAMMA_MODE_FLOAT = 0x2,
3524	} COL_MAN_INPUT_GAMMA_MODE;
3525	typedef enum COL_MAN_OUTPUT_CSC_MODE {
3526	COL_MAN_OUTPUT_CSC_BYPASS = 0x0,
3527	COL_MAN_OUTPUT_CSC_RGB = 0x1,
3528	COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
3529	COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3,
3530	COL_MAN_OUTPUT_CSC_A = 0x4,
3531	COL_MAN_OUTPUT_CSC_B = 0x5,
3532	COL_MAN_OUTPUT_CSC_UNITY = 0x6,
3533	} COL_MAN_OUTPUT_CSC_MODE;
3534	typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
3535	DENORM_CLAMP_MODE_UNITY = 0x0,
3536	DENORM_CLAMP_MODE_8 = 0x1,
3537	DENORM_CLAMP_MODE_10 = 0x2,
3538	DENORM_CLAMP_MODE_12 = 0x3,
3539	} COL_MAN_DENORM_CLAMP_CONTROL;
3540	typedef enum COL_MAN_GAMMA_CORR_CONTROL {
3541	GAMMA_CORR_MODE_BYPASS = 0x0,
3542	GAMMA_CORR_MODE_A = 0x1,
3543	GAMMA_CORR_MODE_B = 0x2,
3544	} COL_MAN_GAMMA_CORR_CONTROL;
3545	typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
3546	CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0,
3547	CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1,
3548	} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
3549	typedef enum UNP_GRPH_EN {
3550	UNP_GRPH_DISABLED = 0x0,
3551	UNP_GRPH_ENABLED = 0x1,
3552	} UNP_GRPH_EN;
3553	typedef enum UNP_GRPH_DEPTH {
3554	UNP_GRPH_8BPP = 0x0,
3555	UNP_GRPH_16BPP = 0x1,
3556	UNP_GRPH_32BPP = 0x2,
3557	} UNP_GRPH_DEPTH;
3558	typedef enum UNP_GRPH_NUM_BANKS {
3559	UNP_GRPH_ADDR_SURF_2_BANK = 0x0,
3560	UNP_GRPH_ADDR_SURF_4_BANK = 0x1,
3561	UNP_GRPH_ADDR_SURF_8_BANK = 0x2,
3562	UNP_GRPH_ADDR_SURF_16_BANK = 0x3,
3563	} UNP_GRPH_NUM_BANKS;
3564	typedef enum UNP_GRPH_BANK_WIDTH {
3565	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0,
3566	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1,
3567	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2,
3568	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3,
3569	} UNP_GRPH_BANK_WIDTH;
3570	typedef enum UNP_GRPH_BANK_HEIGHT {
3571	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0,
3572	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1,
3573	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2,
3574	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3,
3575	} UNP_GRPH_BANK_HEIGHT;
3576	typedef enum UNP_GRPH_TILE_SPLIT {
3577	UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0,
3578	UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1,
3579	UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2,
3580	UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3,
3581	UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4,
3582	UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5,
3583	UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6,
3584	} UNP_GRPH_TILE_SPLIT;
3585	typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
3586	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0,
3587	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1,
3588	} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
3589	typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
3590	UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0,
3591	UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1,
3592	} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
3593	typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
3594	UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0,
3595	UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1,
3596	UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2,
3597	UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3,
3598	} UNP_GRPH_MACRO_TILE_ASPECT;
3599	typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
3600	UNP_GRPH_DYNAMIC_EXPANSION = 0x0,
3601	UNP_GRPH_ZERO_EXPANSION = 0x1,
3602	} UNP_GRPH_COLOR_EXPANSION_MODE;
3603	typedef enum UNP_VIDEO_FORMAT {
3604	UNP_VIDEO_FORMAT0 = 0x0,
3605	UNP_VIDEO_FORMAT1 = 0x1,
3606	UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2,
3607	UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3,
3608	UNP_VIDEO_FORMAT_YUV422_YCb = 0x4,
3609	UNP_VIDEO_FORMAT_YUV422_YCr = 0x5,
3610	UNP_VIDEO_FORMAT_YUV422_CbY = 0x6,
3611	UNP_VIDEO_FORMAT_YUV422_CrY = 0x7,
3612	} UNP_VIDEO_FORMAT;
3613	typedef enum UNP_GRPH_ENDIAN_SWAP {
3614	UNP_GRPH_ENDIAN_SWAP_NONE = 0x0,
3615	UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
3616	UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
3617	UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3,
3618	} UNP_GRPH_ENDIAN_SWAP;
3619	typedef enum UNP_GRPH_RED_CROSSBAR {
3620	UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0,
3621	UNP_GRPH_RED_CROSSBAR_G_Y = 0x1,
3622	UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2,
3623	UNP_GRPH_RED_CROSSBAR_A = 0x3,
3624	} UNP_GRPH_RED_CROSSBAR;
3625	typedef enum UNP_GRPH_GREEN_CROSSBAR {
3626	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0,
3627	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1,
3628	UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2,
3629	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3,
3630	} UNP_GRPH_GREEN_CROSSBAR;
3631	typedef enum UNP_GRPH_BLUE_CROSSBAR {
3632	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0,
3633	UNP_GRPH_BLUE_CROSSBAR_A = 0x1,
3634	UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2,
3635	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3,
3636	} UNP_GRPH_BLUE_CROSSBAR;
3637	typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
3638	UNP_GRPH_UPDATE_LOCK_0 = 0x0,
3639	UNP_GRPH_UPDATE_LOCK_1 = 0x1,
3640	} UNP_GRPH_MODE_UPDATE_LOCKG;
3641	typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
3642	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0,
3643	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1,
3644	} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
3645	typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
3646	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
3647	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
3648	} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
3649	typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
3650	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
3651	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
3652	} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
3653	typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
3654	UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0,
3655	UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1,
3656	} UNP_GRPH_STEREOSYNC_FLIP_EN;
3657	typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
3658	UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0,
3659	UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1,
3660	UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2,
3661	UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3,
3662	} UNP_GRPH_STEREOSYNC_FLIP_MODE;
3663	typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
3664	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0,
3665	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1,
3666	} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
3667	typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
3668	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0,
3669	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1,
3670	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2,
3671	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3,
3672	} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
3673	typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
3674	UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0,
3675	UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1,
3676	} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
3677	typedef enum UNP_CRC_SOURCE_SEL {
3678	UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0,
3679	UNP_CRC_SOURCE_SEL_LOWER32 = 0x1,
3680	UNP_CRC_SOURCE_SEL_RESERVED = 0x2,
3681	UNP_CRC_SOURCE_SEL_LOWER16 = 0x3,
3682	UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4,
3683	} UNP_CRC_SOURCE_SEL;
3684	typedef enum UNP_CRC_LINE_SEL {
3685	UNP_CRC_LINE_SEL_RESERVED = 0x0,
3686	UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1,
3687	UNP_CRC_LINE_SEL_ODD_ONLY = 0x2,
3688	UNP_CRC_LINE_SEL_ODD_EVEN = 0x3,
3689	} UNP_CRC_LINE_SEL;
3690	typedef enum UNP_ROTATION_ANGLE {
3691	UNP_ROTATION_ANGLE_0 = 0x0,
3692	UNP_ROTATION_ANGLE_90 = 0x1,
3693	UNP_ROTATION_ANGLE_180 = 0x2,
3694	UNP_ROTATION_ANGLE_270 = 0x3,
3695	UNP_ROTATION_ANGLE_0m = 0x4,
3696	UNP_ROTATION_ANGLE_90m = 0x5,
3697	UNP_ROTATION_ANGLE_180m = 0x6,
3698	UNP_ROTATION_ANGLE_270m = 0x7,
3699	} UNP_ROTATION_ANGLE;
3700	typedef enum UNP_PIXEL_DROP {
3701	UNP_PIXEL_NO_DROP = 0x0,
3702	UNP_PIXEL_DROPPING = 0x1,
3703	} UNP_PIXEL_DROP;
3704	typedef enum UNP_BUFFER_MODE {
3705	UNP_BUFFER_MODE_LUMA = 0x0,
3706	UNP_BUFFER_MODE_LUMA_CHROMA = 0x1,
3707	} UNP_BUFFER_MODE;
3708	typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
3709	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
3710	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
3711	} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
3712	typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
3713	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
3714	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
3715	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
3716	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
3717	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
3718	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
3719	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
3720	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
3721	} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
3722	typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
3723	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
3724	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
3725	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
3726	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
3727	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
3728	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
3729	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
3730	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
3731	} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
3732	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
3733	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0,
3734	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1,
3735	} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
3736	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
3737	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0,
3738	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1,
3739	} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
3740	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
3741	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0,
3742	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1,
3743	} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
3744	typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
3745	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
3746	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
3747	} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
3748	typedef enum AZ_GLOBAL_CAPABILITIES {
3749	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
3750	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
3751	} AZ_GLOBAL_CAPABILITIES;
3752	typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
3753	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0,
3754	ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1,
3755	} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
3756	typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
3757	FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0,
3758	FLUSH_CONTROL_FLUSH_STARTED = 0x1,
3759	} GLOBAL_CONTROL_FLUSH_CONTROL;
3760	typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
3761	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0,
3762	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1,
3763	} GLOBAL_CONTROL_CONTROLLER_RESET;
3764	typedef enum AZ_STATE_CHANGE_STATUS {
3765	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0,
3766	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1,
3767	} AZ_STATE_CHANGE_STATUS;
3768	typedef enum GLOBAL_STATUS_FLUSH_STATUS {
3769	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0,
3770	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1,
3771	} GLOBAL_STATUS_FLUSH_STATUS;
3772	typedef enum STREAM_0_SYNCHRONIZATION {
3773	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
3774	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
3775	} STREAM_0_SYNCHRONIZATION;
3776	typedef enum STREAM_1_SYNCHRONIZATION {
3777	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
3778	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
3779	} STREAM_1_SYNCHRONIZATION;
3780	typedef enum STREAM_2_SYNCHRONIZATION {
3781	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
3782	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
3783	} STREAM_2_SYNCHRONIZATION;
3784	typedef enum STREAM_3_SYNCHRONIZATION {
3785	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3786	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3787	} STREAM_3_SYNCHRONIZATION;
3788	typedef enum STREAM_4_SYNCHRONIZATION {
3789	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3790	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3791	} STREAM_4_SYNCHRONIZATION;
3792	typedef enum STREAM_5_SYNCHRONIZATION {
3793	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3794	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3795	} STREAM_5_SYNCHRONIZATION;
3796	typedef enum STREAM_6_SYNCHRONIZATION {
3797	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3798	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3799	} STREAM_6_SYNCHRONIZATION;
3800	typedef enum STREAM_7_SYNCHRONIZATION {
3801	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3802	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3803	} STREAM_7_SYNCHRONIZATION;
3804	typedef enum STREAM_8_SYNCHRONIZATION {
3805	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3806	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3807	} STREAM_8_SYNCHRONIZATION;
3808	typedef enum STREAM_9_SYNCHRONIZATION {
3809	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3810	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3811	} STREAM_9_SYNCHRONIZATION;
3812	typedef enum STREAM_10_SYNCHRONIZATION {
3813	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3814	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3815	} STREAM_10_SYNCHRONIZATION;
3816	typedef enum STREAM_11_SYNCHRONIZATION {
3817	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3818	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3819	} STREAM_11_SYNCHRONIZATION;
3820	typedef enum STREAM_12_SYNCHRONIZATION {
3821	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3822	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3823	} STREAM_12_SYNCHRONIZATION;
3824	typedef enum STREAM_13_SYNCHRONIZATION {
3825	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3826	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3827	} STREAM_13_SYNCHRONIZATION;
3828	typedef enum STREAM_14_SYNCHRONIZATION {
3829	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3830	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3831	} STREAM_14_SYNCHRONIZATION;
3832	typedef enum STREAM_15_SYNCHRONIZATION {
3833	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3834	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3835	} STREAM_15_SYNCHRONIZATION;
3836	typedef enum CORB_READ_POINTER_RESET {
3837	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0,
3838	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1,
3839	} CORB_READ_POINTER_RESET;
3840	typedef enum AZ_CORB_SIZE {
3841	AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0,
3842	AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1,
3843	AZ_CORB_SIZE_256ENTRIES = 0x2,
3844	AZ_CORB_SIZE_RESERVED = 0x3,
3845	} AZ_CORB_SIZE;
3846	typedef enum AZ_RIRB_WRITE_POINTER_RESET {
3847	AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0,
3848	AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1,
3849	} AZ_RIRB_WRITE_POINTER_RESET;
3850	typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
3851	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
3852	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
3853	} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
3854	typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
3855	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
3856	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
3857	} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
3858	typedef enum AZ_RIRB_SIZE {
3859	AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0,
3860	AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1,
3861	AZ_RIRB_SIZE_256ENTRIES = 0x2,
3862	AZ_RIRB_SIZE_UNDEFINED = 0x3,
3863	} AZ_RIRB_SIZE;
3864	typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
3865	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
3866	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
3867	} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
3868	typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
3869	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
3870	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
3871	} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
3872	typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
3873	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
3874	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
3875	} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
3876	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
3877	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
3878	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
3879	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
3880	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
3881	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
3882	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
3883	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
3884	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
3885	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
3886	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
3887	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
3888	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
3889	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
3890	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
3891	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
3892	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
3893	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
3894	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
3895	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
3896	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
3897	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
3898	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
3899	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
3900	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
3901	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
3902	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
3903	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
3904	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
3905	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
3906	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
3907	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
3908	typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
3909	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
3910	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
3911	} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
3912	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
3913	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
3914	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
3915	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
3916	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
3917	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
3918	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
3919	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3920	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
3921	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
3922	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
3923	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
3924	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
3925	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
3926	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3927	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
3928	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
3929	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
3930	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
3931	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
3932	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
3933	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
3934	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
3935	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
3936	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3937	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
3938	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
3939	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
3940	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
3941	typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
3942	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
3943	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
3944	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
3945	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
3946	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
3947	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
3948	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
3949	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
3950	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
3951	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
3952	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
3953	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
3954	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
3955	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
3956	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
3957	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
3958	} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
3959	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
3960	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
3961	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
3962	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
3963	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
3964	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
3965	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
3966	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
3967	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
3968	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
3969	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
3970	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3971	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
3972	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
3973	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
3974	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
3975	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
3976	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
3977	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3978	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
3979	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
3980	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
3981	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
3982	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
3983	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
3984	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
3985	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
3986	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
3987	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3988	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
3989	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
3990	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
3991	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
3992	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
3993	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
3994	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
3995	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
3996	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
3997	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
3998	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
3999	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4000	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4001	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4002	} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4003	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
4004	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
4005	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
4006	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
4007	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
4008	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
4009	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
4010	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
4011	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
4012	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
4013	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
4014	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
4015	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
4016	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
4017	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
4018	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
4019	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
4020	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
4021	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
4022	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
4023	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
4024	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
4025	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
4026	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
4027	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
4028	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
4029	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
4030	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
4031	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4032	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4033	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4034	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4035	typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
4036	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
4037	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
4038	} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
4039	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
4040	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
4041	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
4042	} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
4043	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4044	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4045	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4046	} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4047	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
4048	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
4049	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1,
4050	} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
4051	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
4052	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
4053	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
4054	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
4055	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
4056	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
4057	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
4058	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
4059	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
4060	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
4061	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
4062	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
4063	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
4064	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
4065	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
4066	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
4067	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4068	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4069	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4070	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4071	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4072	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4073	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4074	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4075	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4076	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4077	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4078	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4079	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4080	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4081	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4082	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4083	typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4084	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4085	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4086	} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4087	typedef enum AZ_LATENCY_COUNTER_CONTROL {
4088	AZ_LATENCY_COUNTER_NO_RESET = 0x0,
4089	AZ_LATENCY_COUNTER_RESET_DONE = 0x1,
4090	} AZ_LATENCY_COUNTER_CONTROL;
4091	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4092	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4093	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4094	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4095	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4096	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4097	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4098	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4099	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4100	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4101	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4102	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4103	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4104	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4105	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4106	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4107	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4108	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4109	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4110	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4111	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4112	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4113	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4114	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4115	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4116	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4117	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4118	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4119	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4120	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4121	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4122	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4123	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4124	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4125	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4126	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4127	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4128	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4129	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4130	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4131	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4132	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4133	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
4134	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4135	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4136	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4137	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4138	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4139	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4140	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4141	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4142	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4143	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4144	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4145	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4146	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4147	typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4148	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4149	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4150	} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4151	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4152	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4153	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4154	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4155	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4156	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4157	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4158	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4159	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4160	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4161	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4162	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4163	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4164	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4165	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4166	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4167	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4168	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4169	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4170	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4171	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4172	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4173	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4174	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4175	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4176	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4177	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4178	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4179	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4180	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4181	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4182	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4183	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4184	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4185	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4186	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4187	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4188	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4189	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4190	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4191	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4192	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4193	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4194	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4195	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4196	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4197	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4198	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4199	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4200	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
4201	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4202	} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4203	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4204	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
4205	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
4206	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4207	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4208	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
4209	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4210	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4211	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4212	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4213	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4214	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4215	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4216	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4217	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4218	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4219	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4220	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4221	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4222	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4223	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4224	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
4225	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
4226	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4227	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4228	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4229	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4230	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4231	typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4232	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4233	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4234	} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4235	typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4236	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4237	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4238	} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4239	typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4240	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
4241	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
4242	} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4243	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4244	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4245	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4246	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4247	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4248	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4249	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4250	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4251	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4252	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4253	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4254	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4255	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4256	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4257	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4258	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4259	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4260	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4261	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4262	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4263	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4264	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
4265	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
4266	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4267	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4268	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4269	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4270	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4271	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4272	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4273	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4274	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4275	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4276	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
4277	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
4278	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4279	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4280	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
4281	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4282	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4283	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4284	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4285	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
4286	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4287	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4288	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4289	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
4290	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4291	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4292	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4293	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4294	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4295	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4296	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4297	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4298	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4299	typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4300	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4301	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4302	} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4303	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4304	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4305	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4306	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4307	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4308	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4309	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4310	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4311	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4312	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4313	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4314	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4315	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4316	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
4317	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
4318	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4319	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4320	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4321	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4322	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4323	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4324	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4325	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4326	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4327	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4328	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4329	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4330	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4331	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4332	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4333	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4334	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4335	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4336	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
4337	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
4338	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4339	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4340	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4341	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4342	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4343	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4344	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4345	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4346	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4347	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4348	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4349	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4350	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4351	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4352	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4353	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4354	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4355	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
4356	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
4357	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
4358	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
4359	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4360	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
4361	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
4362	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4363	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
4364	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
4365	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
4366	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
4367	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4368	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
4369	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4370	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4371	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4372	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4373	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4374	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4375	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4376	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4377	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4378	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4379	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4380	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4381	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4382	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4383	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4384	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
4385	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
4386	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4387	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4388	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4389	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4390	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4391	typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4392	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4393	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4394	} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4395	typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4396	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
4397	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
4398	} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4399	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
4400	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
4401	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
4402	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
4403	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
4404	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
4405	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
4406	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
4407	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
4408	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
4409	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
4410	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4411	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
4412	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
4413	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
4414	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
4415	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
4416	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
4417	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4418	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
4419	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
4420	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
4421	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
4422	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
4423	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
4424	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
4425	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
4426	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
4427	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4428	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
4429	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
4430	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
4431	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
4432	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
4433	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
4434	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
4435	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4436	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
4437	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4438	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4439	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4440	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4441	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4442	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4443	typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4444	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4445	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4446	} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4447	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
4448	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
4449	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
4450	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
4451	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4452	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4453	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4454	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4455	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
4456	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
4457	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
4458	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
4459	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4460	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4461	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4462	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4463	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
4464	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
4465	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
4466	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
4467	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4468	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4469	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4470	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4471	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
4472	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
4473	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
4474	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
4475	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4476	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4477	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4478	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4479	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
4480	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
4481	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
4482	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
4483	typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4484	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4485	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4486	} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4487	typedef enum BLND_CONTROL_BLND_MODE {
4488	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
4489	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
4490	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
4491	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
4492	} BLND_CONTROL_BLND_MODE;
4493	typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
4494	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
4495	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
4496	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
4497	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
4498	} BLND_CONTROL_BLND_STEREO_TYPE;
4499	typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
4500	BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
4501	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
4502	} BLND_CONTROL_BLND_STEREO_POLARITY;
4503	typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
4504	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
4505	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
4506	} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
4507	typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
4508	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
4509	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
4510	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
4511	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
4512	} BLND_CONTROL_BLND_ALPHA_MODE;
4513	typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
4514	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
4515	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
4516	} BLND_CONTROL_BLND_MULTIPLIED_MODE;
4517	typedef enum BLND_SM_CONTROL2_SM_MODE {
4518	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
4519	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
4520	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
4521	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
4522	} BLND_SM_CONTROL2_SM_MODE;
4523	typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
4524	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
4525	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
4526	} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
4527	typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
4528	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
4529	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
4530	} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
4531	typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
4532	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
4533	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
4534	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
4535	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
4536	} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
4537	typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
4538	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
4539	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
4540	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
4541	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
4542	} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
4543	typedef enum BLND_CONTROL2_PTI_ENABLE {
4544	BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0,
4545	BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1,
4546	} BLND_CONTROL2_PTI_ENABLE;
4547	typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
4548	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
4549	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
4550	} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
4551	typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
4552	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
4553	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
4554	} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
4555	typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
4556	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
4557	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
4558	} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
4559	typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
4560	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
4561	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
4562	} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
4563	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
4564	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
4565	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
4566	} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
4567	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
4568	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
4569	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
4570	} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
4571	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
4572	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
4573	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
4574	} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
4575	typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
4576	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
4577	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
4578	} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
4579	typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
4580	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
4581	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
4582	} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
4583	typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
4584	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
4585	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
4586	} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
4587	typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
4588	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
4589	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
4590	} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
4591	typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
4592	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
4593	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
4594	} BLND_DEBUG_BLND_CNV_MUX_SELECT;
4595	typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
4596	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
4597	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
4598	} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
4599	typedef enum DebugBlockId {
4600	DBG_BLOCK_ID_RESERVED = 0x0,
4601	DBG_BLOCK_ID_DBG = 0x1,
4602	DBG_BLOCK_ID_VMC = 0x2,
4603	DBG_BLOCK_ID_PDMA = 0x3,
4604	DBG_BLOCK_ID_CG = 0x4,
4605	DBG_BLOCK_ID_SRBM = 0x5,
4606	DBG_BLOCK_ID_GRBM = 0x6,
4607	DBG_BLOCK_ID_RLC = 0x7,
4608	DBG_BLOCK_ID_CSC = 0x8,
4609	DBG_BLOCK_ID_SEM = 0x9,
4610	DBG_BLOCK_ID_IH = 0xa,
4611	DBG_BLOCK_ID_SC = 0xb,
4612	DBG_BLOCK_ID_SQ = 0xc,
4613	DBG_BLOCK_ID_UVDU = 0xd,
4614	DBG_BLOCK_ID_SQA = 0xe,
4615	DBG_BLOCK_ID_SDMA0 = 0xf,
4616	DBG_BLOCK_ID_SDMA1 = 0x10,
4617	DBG_BLOCK_ID_SPIM = 0x11,
4618	DBG_BLOCK_ID_GDS = 0x12,
4619	DBG_BLOCK_ID_VC0 = 0x13,
4620	DBG_BLOCK_ID_VC1 = 0x14,
4621	DBG_BLOCK_ID_PA0 = 0x15,
4622	DBG_BLOCK_ID_PA1 = 0x16,
4623	DBG_BLOCK_ID_CP0 = 0x17,
4624	DBG_BLOCK_ID_CP1 = 0x18,
4625	DBG_BLOCK_ID_CP2 = 0x19,
4626	DBG_BLOCK_ID_XBR = 0x1a,
4627	DBG_BLOCK_ID_UVDM = 0x1b,
4628	DBG_BLOCK_ID_VGT0 = 0x1c,
4629	DBG_BLOCK_ID_VGT1 = 0x1d,
4630	DBG_BLOCK_ID_IA = 0x1e,
4631	DBG_BLOCK_ID_SXM0 = 0x1f,
4632	DBG_BLOCK_ID_SXM1 = 0x20,
4633	DBG_BLOCK_ID_SCT0 = 0x21,
4634	DBG_BLOCK_ID_SCT1 = 0x22,
4635	DBG_BLOCK_ID_SPM0 = 0x23,
4636	DBG_BLOCK_ID_SPM1 = 0x24,
4637	DBG_BLOCK_ID_UNUSED0 = 0x25,
4638	DBG_BLOCK_ID_UNUSED1 = 0x26,
4639	DBG_BLOCK_ID_TCAA = 0x27,
4640	DBG_BLOCK_ID_TCAB = 0x28,
4641	DBG_BLOCK_ID_TCCA = 0x29,
4642	DBG_BLOCK_ID_TCCB = 0x2a,
4643	DBG_BLOCK_ID_MCC0 = 0x2b,
4644	DBG_BLOCK_ID_MCC1 = 0x2c,
4645	DBG_BLOCK_ID_MCC2 = 0x2d,
4646	DBG_BLOCK_ID_MCC3 = 0x2e,
4647	DBG_BLOCK_ID_SXS0 = 0x2f,
4648	DBG_BLOCK_ID_SXS1 = 0x30,
4649	DBG_BLOCK_ID_SXS2 = 0x31,
4650	DBG_BLOCK_ID_SXS3 = 0x32,
4651	DBG_BLOCK_ID_SXS4 = 0x33,
4652	DBG_BLOCK_ID_SXS5 = 0x34,
4653	DBG_BLOCK_ID_SXS6 = 0x35,
4654	DBG_BLOCK_ID_SXS7 = 0x36,
4655	DBG_BLOCK_ID_SXS8 = 0x37,
4656	DBG_BLOCK_ID_SXS9 = 0x38,
4657	DBG_BLOCK_ID_BCI0 = 0x39,
4658	DBG_BLOCK_ID_BCI1 = 0x3a,
4659	DBG_BLOCK_ID_BCI2 = 0x3b,
4660	DBG_BLOCK_ID_BCI3 = 0x3c,
4661	DBG_BLOCK_ID_MCB = 0x3d,
4662	DBG_BLOCK_ID_UNUSED6 = 0x3e,
4663	DBG_BLOCK_ID_SQA00 = 0x3f,
4664	DBG_BLOCK_ID_SQA01 = 0x40,
4665	DBG_BLOCK_ID_SQA02 = 0x41,
4666	DBG_BLOCK_ID_SQA10 = 0x42,
4667	DBG_BLOCK_ID_SQA11 = 0x43,
4668	DBG_BLOCK_ID_SQA12 = 0x44,
4669	DBG_BLOCK_ID_UNUSED7 = 0x45,
4670	DBG_BLOCK_ID_UNUSED8 = 0x46,
4671	DBG_BLOCK_ID_SQB00 = 0x47,
4672	DBG_BLOCK_ID_SQB01 = 0x48,
4673	DBG_BLOCK_ID_SQB10 = 0x49,
4674	DBG_BLOCK_ID_SQB11 = 0x4a,
4675	DBG_BLOCK_ID_SQ00 = 0x4b,
4676	DBG_BLOCK_ID_SQ01 = 0x4c,
4677	DBG_BLOCK_ID_SQ10 = 0x4d,
4678	DBG_BLOCK_ID_SQ11 = 0x4e,
4679	DBG_BLOCK_ID_CB00 = 0x4f,
4680	DBG_BLOCK_ID_CB01 = 0x50,
4681	DBG_BLOCK_ID_CB02 = 0x51,
4682	DBG_BLOCK_ID_CB03 = 0x52,
4683	DBG_BLOCK_ID_CB04 = 0x53,
4684	DBG_BLOCK_ID_UNUSED9 = 0x54,
4685	DBG_BLOCK_ID_UNUSED10 = 0x55,
4686	DBG_BLOCK_ID_UNUSED11 = 0x56,
4687	DBG_BLOCK_ID_CB10 = 0x57,
4688	DBG_BLOCK_ID_CB11 = 0x58,
4689	DBG_BLOCK_ID_CB12 = 0x59,
4690	DBG_BLOCK_ID_CB13 = 0x5a,
4691	DBG_BLOCK_ID_CB14 = 0x5b,
4692	DBG_BLOCK_ID_UNUSED12 = 0x5c,
4693	DBG_BLOCK_ID_UNUSED13 = 0x5d,
4694	DBG_BLOCK_ID_UNUSED14 = 0x5e,
4695	DBG_BLOCK_ID_TCP0 = 0x5f,
4696	DBG_BLOCK_ID_TCP1 = 0x60,
4697	DBG_BLOCK_ID_TCP2 = 0x61,
4698	DBG_BLOCK_ID_TCP3 = 0x62,
4699	DBG_BLOCK_ID_TCP4 = 0x63,
4700	DBG_BLOCK_ID_TCP5 = 0x64,
4701	DBG_BLOCK_ID_TCP6 = 0x65,
4702	DBG_BLOCK_ID_TCP7 = 0x66,
4703	DBG_BLOCK_ID_TCP8 = 0x67,
4704	DBG_BLOCK_ID_TCP9 = 0x68,
4705	DBG_BLOCK_ID_TCP10 = 0x69,
4706	DBG_BLOCK_ID_TCP11 = 0x6a,
4707	DBG_BLOCK_ID_TCP12 = 0x6b,
4708	DBG_BLOCK_ID_TCP13 = 0x6c,
4709	DBG_BLOCK_ID_TCP14 = 0x6d,
4710	DBG_BLOCK_ID_TCP15 = 0x6e,
4711	DBG_BLOCK_ID_TCP16 = 0x6f,
4712	DBG_BLOCK_ID_TCP17 = 0x70,
4713	DBG_BLOCK_ID_TCP18 = 0x71,
4714	DBG_BLOCK_ID_TCP19 = 0x72,
4715	DBG_BLOCK_ID_TCP20 = 0x73,
4716	DBG_BLOCK_ID_TCP21 = 0x74,
4717	DBG_BLOCK_ID_TCP22 = 0x75,
4718	DBG_BLOCK_ID_TCP23 = 0x76,
4719	DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
4720	DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
4721	DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
4722	DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
4723	DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
4724	DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
4725	DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
4726	DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
4727	DBG_BLOCK_ID_DB00 = 0x7f,
4728	DBG_BLOCK_ID_DB01 = 0x80,
4729	DBG_BLOCK_ID_DB02 = 0x81,
4730	DBG_BLOCK_ID_DB03 = 0x82,
4731	DBG_BLOCK_ID_DB04 = 0x83,
4732	DBG_BLOCK_ID_UNUSED15 = 0x84,
4733	DBG_BLOCK_ID_UNUSED16 = 0x85,
4734	DBG_BLOCK_ID_UNUSED17 = 0x86,
4735	DBG_BLOCK_ID_DB10 = 0x87,
4736	DBG_BLOCK_ID_DB11 = 0x88,
4737	DBG_BLOCK_ID_DB12 = 0x89,
4738	DBG_BLOCK_ID_DB13 = 0x8a,
4739	DBG_BLOCK_ID_DB14 = 0x8b,
4740	DBG_BLOCK_ID_UNUSED18 = 0x8c,
4741	DBG_BLOCK_ID_UNUSED19 = 0x8d,
4742	DBG_BLOCK_ID_UNUSED20 = 0x8e,
4743	DBG_BLOCK_ID_TCC0 = 0x8f,
4744	DBG_BLOCK_ID_TCC1 = 0x90,
4745	DBG_BLOCK_ID_TCC2 = 0x91,
4746	DBG_BLOCK_ID_TCC3 = 0x92,
4747	DBG_BLOCK_ID_TCC4 = 0x93,
4748	DBG_BLOCK_ID_TCC5 = 0x94,
4749	DBG_BLOCK_ID_TCC6 = 0x95,
4750	DBG_BLOCK_ID_TCC7 = 0x96,
4751	DBG_BLOCK_ID_SPS00 = 0x97,
4752	DBG_BLOCK_ID_SPS01 = 0x98,
4753	DBG_BLOCK_ID_SPS02 = 0x99,
4754	DBG_BLOCK_ID_SPS10 = 0x9a,
4755	DBG_BLOCK_ID_SPS11 = 0x9b,
4756	DBG_BLOCK_ID_SPS12 = 0x9c,
4757	DBG_BLOCK_ID_UNUSED21 = 0x9d,
4758	DBG_BLOCK_ID_UNUSED22 = 0x9e,
4759	DBG_BLOCK_ID_TA00 = 0x9f,
4760	DBG_BLOCK_ID_TA01 = 0xa0,
4761	DBG_BLOCK_ID_TA02 = 0xa1,
4762	DBG_BLOCK_ID_TA03 = 0xa2,
4763	DBG_BLOCK_ID_TA04 = 0xa3,
4764	DBG_BLOCK_ID_TA05 = 0xa4,
4765	DBG_BLOCK_ID_TA06 = 0xa5,
4766	DBG_BLOCK_ID_TA07 = 0xa6,
4767	DBG_BLOCK_ID_TA08 = 0xa7,
4768	DBG_BLOCK_ID_TA09 = 0xa8,
4769	DBG_BLOCK_ID_TA0A = 0xa9,
4770	DBG_BLOCK_ID_TA0B = 0xaa,
4771	DBG_BLOCK_ID_UNUSED23 = 0xab,
4772	DBG_BLOCK_ID_UNUSED24 = 0xac,
4773	DBG_BLOCK_ID_UNUSED25 = 0xad,
4774	DBG_BLOCK_ID_UNUSED26 = 0xae,
4775	DBG_BLOCK_ID_TA10 = 0xaf,
4776	DBG_BLOCK_ID_TA11 = 0xb0,
4777	DBG_BLOCK_ID_TA12 = 0xb1,
4778	DBG_BLOCK_ID_TA13 = 0xb2,
4779	DBG_BLOCK_ID_TA14 = 0xb3,
4780	DBG_BLOCK_ID_TA15 = 0xb4,
4781	DBG_BLOCK_ID_TA16 = 0xb5,
4782	DBG_BLOCK_ID_TA17 = 0xb6,
4783	DBG_BLOCK_ID_TA18 = 0xb7,
4784	DBG_BLOCK_ID_TA19 = 0xb8,
4785	DBG_BLOCK_ID_TA1A = 0xb9,
4786	DBG_BLOCK_ID_TA1B = 0xba,
4787	DBG_BLOCK_ID_UNUSED27 = 0xbb,
4788	DBG_BLOCK_ID_UNUSED28 = 0xbc,
4789	DBG_BLOCK_ID_UNUSED29 = 0xbd,
4790	DBG_BLOCK_ID_UNUSED30 = 0xbe,
4791	DBG_BLOCK_ID_TD00 = 0xbf,
4792	DBG_BLOCK_ID_TD01 = 0xc0,
4793	DBG_BLOCK_ID_TD02 = 0xc1,
4794	DBG_BLOCK_ID_TD03 = 0xc2,
4795	DBG_BLOCK_ID_TD04 = 0xc3,
4796	DBG_BLOCK_ID_TD05 = 0xc4,
4797	DBG_BLOCK_ID_TD06 = 0xc5,
4798	DBG_BLOCK_ID_TD07 = 0xc6,
4799	DBG_BLOCK_ID_TD08 = 0xc7,
4800	DBG_BLOCK_ID_TD09 = 0xc8,
4801	DBG_BLOCK_ID_TD0A = 0xc9,
4802	DBG_BLOCK_ID_TD0B = 0xca,
4803	DBG_BLOCK_ID_UNUSED31 = 0xcb,
4804	DBG_BLOCK_ID_UNUSED32 = 0xcc,
4805	DBG_BLOCK_ID_UNUSED33 = 0xcd,
4806	DBG_BLOCK_ID_UNUSED34 = 0xce,
4807	DBG_BLOCK_ID_TD10 = 0xcf,
4808	DBG_BLOCK_ID_TD11 = 0xd0,
4809	DBG_BLOCK_ID_TD12 = 0xd1,
4810	DBG_BLOCK_ID_TD13 = 0xd2,
4811	DBG_BLOCK_ID_TD14 = 0xd3,
4812	DBG_BLOCK_ID_TD15 = 0xd4,
4813	DBG_BLOCK_ID_TD16 = 0xd5,
4814	DBG_BLOCK_ID_TD17 = 0xd6,
4815	DBG_BLOCK_ID_TD18 = 0xd7,
4816	DBG_BLOCK_ID_TD19 = 0xd8,
4817	DBG_BLOCK_ID_TD1A = 0xd9,
4818	DBG_BLOCK_ID_TD1B = 0xda,
4819	DBG_BLOCK_ID_UNUSED35 = 0xdb,
4820	DBG_BLOCK_ID_UNUSED36 = 0xdc,
4821	DBG_BLOCK_ID_UNUSED37 = 0xdd,
4822	DBG_BLOCK_ID_UNUSED38 = 0xde,
4823	DBG_BLOCK_ID_LDS00 = 0xdf,
4824	DBG_BLOCK_ID_LDS01 = 0xe0,
4825	DBG_BLOCK_ID_LDS02 = 0xe1,
4826	DBG_BLOCK_ID_LDS03 = 0xe2,
4827	DBG_BLOCK_ID_LDS04 = 0xe3,
4828	DBG_BLOCK_ID_LDS05 = 0xe4,
4829	DBG_BLOCK_ID_LDS06 = 0xe5,
4830	DBG_BLOCK_ID_LDS07 = 0xe6,
4831	DBG_BLOCK_ID_LDS08 = 0xe7,
4832	DBG_BLOCK_ID_LDS09 = 0xe8,
4833	DBG_BLOCK_ID_LDS0A = 0xe9,
4834	DBG_BLOCK_ID_LDS0B = 0xea,
4835	DBG_BLOCK_ID_UNUSED39 = 0xeb,
4836	DBG_BLOCK_ID_UNUSED40 = 0xec,
4837	DBG_BLOCK_ID_UNUSED41 = 0xed,
4838	DBG_BLOCK_ID_UNUSED42 = 0xee,
4839	DBG_BLOCK_ID_LDS10 = 0xef,
4840	DBG_BLOCK_ID_LDS11 = 0xf0,
4841	DBG_BLOCK_ID_LDS12 = 0xf1,
4842	DBG_BLOCK_ID_LDS13 = 0xf2,
4843	DBG_BLOCK_ID_LDS14 = 0xf3,
4844	DBG_BLOCK_ID_LDS15 = 0xf4,
4845	DBG_BLOCK_ID_LDS16 = 0xf5,
4846	DBG_BLOCK_ID_LDS17 = 0xf6,
4847	DBG_BLOCK_ID_LDS18 = 0xf7,
4848	DBG_BLOCK_ID_LDS19 = 0xf8,
4849	DBG_BLOCK_ID_LDS1A = 0xf9,
4850	DBG_BLOCK_ID_LDS1B = 0xfa,
4851	DBG_BLOCK_ID_UNUSED43 = 0xfb,
4852	DBG_BLOCK_ID_UNUSED44 = 0xfc,
4853	DBG_BLOCK_ID_UNUSED45 = 0xfd,
4854	DBG_BLOCK_ID_UNUSED46 = 0xfe,
4855	} DebugBlockId;
4856	typedef enum DebugBlockId_BY2 {
4857	DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
4858	DBG_BLOCK_ID_VMC_BY2 = 0x1,
4859	DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
4860	DBG_BLOCK_ID_GRBM_BY2 = 0x3,
4861	DBG_BLOCK_ID_CSC_BY2 = 0x4,
4862	DBG_BLOCK_ID_IH_BY2 = 0x5,
4863	DBG_BLOCK_ID_SQ_BY2 = 0x6,
4864	DBG_BLOCK_ID_UVD_BY2 = 0x7,
4865	DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
4866	DBG_BLOCK_ID_SPIM_BY2 = 0x9,
4867	DBG_BLOCK_ID_VC0_BY2 = 0xa,
4868	DBG_BLOCK_ID_PA_BY2 = 0xb,
4869	DBG_BLOCK_ID_CP0_BY2 = 0xc,
4870	DBG_BLOCK_ID_CP2_BY2 = 0xd,
4871	DBG_BLOCK_ID_PC0_BY2 = 0xe,
4872	DBG_BLOCK_ID_BCI0_BY2 = 0xf,
4873	DBG_BLOCK_ID_SXM0_BY2 = 0x10,
4874	DBG_BLOCK_ID_SCT0_BY2 = 0x11,
4875	DBG_BLOCK_ID_SPM0_BY2 = 0x12,
4876	DBG_BLOCK_ID_BCI2_BY2 = 0x13,
4877	DBG_BLOCK_ID_TCA_BY2 = 0x14,
4878	DBG_BLOCK_ID_TCCA_BY2 = 0x15,
4879	DBG_BLOCK_ID_MCC_BY2 = 0x16,
4880	DBG_BLOCK_ID_MCC2_BY2 = 0x17,
4881	DBG_BLOCK_ID_MCD_BY2 = 0x18,
4882	DBG_BLOCK_ID_MCD2_BY2 = 0x19,
4883	DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
4884	DBG_BLOCK_ID_MCB_BY2 = 0x1b,
4885	DBG_BLOCK_ID_SQA_BY2 = 0x1c,
4886	DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
4887	DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
4888	DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
4889	DBG_BLOCK_ID_SQB_BY2 = 0x20,
4890	DBG_BLOCK_ID_SQB10_BY2 = 0x21,
4891	DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
4892	DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
4893	DBG_BLOCK_ID_CB_BY2 = 0x24,
4894	DBG_BLOCK_ID_CB02_BY2 = 0x25,
4895	DBG_BLOCK_ID_CB10_BY2 = 0x26,
4896	DBG_BLOCK_ID_CB12_BY2 = 0x27,
4897	DBG_BLOCK_ID_SXS_BY2 = 0x28,
4898	DBG_BLOCK_ID_SXS2_BY2 = 0x29,
4899	DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
4900	DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
4901	DBG_BLOCK_ID_DB_BY2 = 0x2c,
4902	DBG_BLOCK_ID_DB02_BY2 = 0x2d,
4903	DBG_BLOCK_ID_DB10_BY2 = 0x2e,
4904	DBG_BLOCK_ID_DB12_BY2 = 0x2f,
4905	DBG_BLOCK_ID_TCP_BY2 = 0x30,
4906	DBG_BLOCK_ID_TCP2_BY2 = 0x31,
4907	DBG_BLOCK_ID_TCP4_BY2 = 0x32,
4908	DBG_BLOCK_ID_TCP6_BY2 = 0x33,
4909	DBG_BLOCK_ID_TCP8_BY2 = 0x34,
4910	DBG_BLOCK_ID_TCP10_BY2 = 0x35,
4911	DBG_BLOCK_ID_TCP12_BY2 = 0x36,
4912	DBG_BLOCK_ID_TCP14_BY2 = 0x37,
4913	DBG_BLOCK_ID_TCP16_BY2 = 0x38,
4914	DBG_BLOCK_ID_TCP18_BY2 = 0x39,
4915	DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
4916	DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
4917	DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
4918	DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
4919	DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
4920	DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
4921	DBG_BLOCK_ID_TCC_BY2 = 0x40,
4922	DBG_BLOCK_ID_TCC2_BY2 = 0x41,
4923	DBG_BLOCK_ID_TCC4_BY2 = 0x42,
4924	DBG_BLOCK_ID_TCC6_BY2 = 0x43,
4925	DBG_BLOCK_ID_SPS_BY2 = 0x44,
4926	DBG_BLOCK_ID_SPS02_BY2 = 0x45,
4927	DBG_BLOCK_ID_SPS11_BY2 = 0x46,
4928	DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
4929	DBG_BLOCK_ID_TA_BY2 = 0x48,
4930	DBG_BLOCK_ID_TA02_BY2 = 0x49,
4931	DBG_BLOCK_ID_TA04_BY2 = 0x4a,
4932	DBG_BLOCK_ID_TA06_BY2 = 0x4b,
4933	DBG_BLOCK_ID_TA08_BY2 = 0x4c,
4934	DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
4935	DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
4936	DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
4937	DBG_BLOCK_ID_TA10_BY2 = 0x50,
4938	DBG_BLOCK_ID_TA12_BY2 = 0x51,
4939	DBG_BLOCK_ID_TA14_BY2 = 0x52,
4940	DBG_BLOCK_ID_TA16_BY2 = 0x53,
4941	DBG_BLOCK_ID_TA18_BY2 = 0x54,
4942	DBG_BLOCK_ID_TA1A_BY2 = 0x55,
4943	DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
4944	DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
4945	DBG_BLOCK_ID_TD_BY2 = 0x58,
4946	DBG_BLOCK_ID_TD02_BY2 = 0x59,
4947	DBG_BLOCK_ID_TD04_BY2 = 0x5a,
4948	DBG_BLOCK_ID_TD06_BY2 = 0x5b,
4949	DBG_BLOCK_ID_TD08_BY2 = 0x5c,
4950	DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
4951	DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
4952	DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
4953	DBG_BLOCK_ID_TD10_BY2 = 0x60,
4954	DBG_BLOCK_ID_TD12_BY2 = 0x61,
4955	DBG_BLOCK_ID_TD14_BY2 = 0x62,
4956	DBG_BLOCK_ID_TD16_BY2 = 0x63,
4957	DBG_BLOCK_ID_TD18_BY2 = 0x64,
4958	DBG_BLOCK_ID_TD1A_BY2 = 0x65,
4959	DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
4960	DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
4961	DBG_BLOCK_ID_LDS_BY2 = 0x68,
4962	DBG_BLOCK_ID_LDS02_BY2 = 0x69,
4963	DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
4964	DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
4965	DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
4966	DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
4967	DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
4968	DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
4969	DBG_BLOCK_ID_LDS10_BY2 = 0x70,
4970	DBG_BLOCK_ID_LDS12_BY2 = 0x71,
4971	DBG_BLOCK_ID_LDS14_BY2 = 0x72,
4972	DBG_BLOCK_ID_LDS16_BY2 = 0x73,
4973	DBG_BLOCK_ID_LDS18_BY2 = 0x74,
4974	DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
4975	DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
4976	DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
4977	} DebugBlockId_BY2;
4978	typedef enum DebugBlockId_BY4 {
4979	DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
4980	DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
4981	DBG_BLOCK_ID_CSC_BY4 = 0x2,
4982	DBG_BLOCK_ID_SQ_BY4 = 0x3,
4983	DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
4984	DBG_BLOCK_ID_VC0_BY4 = 0x5,
4985	DBG_BLOCK_ID_CP0_BY4 = 0x6,
4986	DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
4987	DBG_BLOCK_ID_SXM0_BY4 = 0x8,
4988	DBG_BLOCK_ID_SPM0_BY4 = 0x9,
4989	DBG_BLOCK_ID_TCAA_BY4 = 0xa,
4990	DBG_BLOCK_ID_MCC_BY4 = 0xb,
4991	DBG_BLOCK_ID_MCD_BY4 = 0xc,
4992	DBG_BLOCK_ID_MCD4_BY4 = 0xd,
4993	DBG_BLOCK_ID_SQA_BY4 = 0xe,
4994	DBG_BLOCK_ID_SQA11_BY4 = 0xf,
4995	DBG_BLOCK_ID_SQB_BY4 = 0x10,
4996	DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
4997	DBG_BLOCK_ID_CB_BY4 = 0x12,
4998	DBG_BLOCK_ID_CB10_BY4 = 0x13,
4999	DBG_BLOCK_ID_SXS_BY4 = 0x14,
5000	DBG_BLOCK_ID_SXS4_BY4 = 0x15,
5001	DBG_BLOCK_ID_DB_BY4 = 0x16,
5002	DBG_BLOCK_ID_DB10_BY4 = 0x17,
5003	DBG_BLOCK_ID_TCP_BY4 = 0x18,
5004	DBG_BLOCK_ID_TCP4_BY4 = 0x19,
5005	DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
5006	DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
5007	DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
5008	DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
5009	DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
5010	DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
5011	DBG_BLOCK_ID_TCC_BY4 = 0x20,
5012	DBG_BLOCK_ID_TCC4_BY4 = 0x21,
5013	DBG_BLOCK_ID_SPS_BY4 = 0x22,
5014	DBG_BLOCK_ID_SPS11_BY4 = 0x23,
5015	DBG_BLOCK_ID_TA_BY4 = 0x24,
5016	DBG_BLOCK_ID_TA04_BY4 = 0x25,
5017	DBG_BLOCK_ID_TA08_BY4 = 0x26,
5018	DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
5019	DBG_BLOCK_ID_TA10_BY4 = 0x28,
5020	DBG_BLOCK_ID_TA14_BY4 = 0x29,
5021	DBG_BLOCK_ID_TA18_BY4 = 0x2a,
5022	DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
5023	DBG_BLOCK_ID_TD_BY4 = 0x2c,
5024	DBG_BLOCK_ID_TD04_BY4 = 0x2d,
5025	DBG_BLOCK_ID_TD08_BY4 = 0x2e,
5026	DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
5027	DBG_BLOCK_ID_TD10_BY4 = 0x30,
5028	DBG_BLOCK_ID_TD14_BY4 = 0x31,
5029	DBG_BLOCK_ID_TD18_BY4 = 0x32,
5030	DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
5031	DBG_BLOCK_ID_LDS_BY4 = 0x34,
5032	DBG_BLOCK_ID_LDS04_BY4 = 0x35,
5033	DBG_BLOCK_ID_LDS08_BY4 = 0x36,
5034	DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
5035	DBG_BLOCK_ID_LDS10_BY4 = 0x38,
5036	DBG_BLOCK_ID_LDS14_BY4 = 0x39,
5037	DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
5038	DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
5039	} DebugBlockId_BY4;
5040	typedef enum DebugBlockId_BY8 {
5041	DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
5042	DBG_BLOCK_ID_CSC_BY8 = 0x1,
5043	DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
5044	DBG_BLOCK_ID_CP0_BY8 = 0x3,
5045	DBG_BLOCK_ID_SXM0_BY8 = 0x4,
5046	DBG_BLOCK_ID_TCA_BY8 = 0x5,
5047	DBG_BLOCK_ID_MCD_BY8 = 0x6,
5048	DBG_BLOCK_ID_SQA_BY8 = 0x7,
5049	DBG_BLOCK_ID_SQB_BY8 = 0x8,
5050	DBG_BLOCK_ID_CB_BY8 = 0x9,
5051	DBG_BLOCK_ID_SXS_BY8 = 0xa,
5052	DBG_BLOCK_ID_DB_BY8 = 0xb,
5053	DBG_BLOCK_ID_TCP_BY8 = 0xc,
5054	DBG_BLOCK_ID_TCP8_BY8 = 0xd,
5055	DBG_BLOCK_ID_TCP16_BY8 = 0xe,
5056	DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
5057	DBG_BLOCK_ID_TCC_BY8 = 0x10,
5058	DBG_BLOCK_ID_SPS_BY8 = 0x11,
5059	DBG_BLOCK_ID_TA_BY8 = 0x12,
5060	DBG_BLOCK_ID_TA08_BY8 = 0x13,
5061	DBG_BLOCK_ID_TA10_BY8 = 0x14,
5062	DBG_BLOCK_ID_TA18_BY8 = 0x15,
5063	DBG_BLOCK_ID_TD_BY8 = 0x16,
5064	DBG_BLOCK_ID_TD08_BY8 = 0x17,
5065	DBG_BLOCK_ID_TD10_BY8 = 0x18,
5066	DBG_BLOCK_ID_TD18_BY8 = 0x19,
5067	DBG_BLOCK_ID_LDS_BY8 = 0x1a,
5068	DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
5069	DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
5070	DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
5071	} DebugBlockId_BY8;
5072	typedef enum DebugBlockId_BY16 {
5073	DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
5074	DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
5075	DBG_BLOCK_ID_SXM_BY16 = 0x2,
5076	DBG_BLOCK_ID_MCD_BY16 = 0x3,
5077	DBG_BLOCK_ID_SQB_BY16 = 0x4,
5078	DBG_BLOCK_ID_SXS_BY16 = 0x5,
5079	DBG_BLOCK_ID_TCP_BY16 = 0x6,
5080	DBG_BLOCK_ID_TCP16_BY16 = 0x7,
5081	DBG_BLOCK_ID_TCC_BY16 = 0x8,
5082	DBG_BLOCK_ID_TA_BY16 = 0x9,
5083	DBG_BLOCK_ID_TA10_BY16 = 0xa,
5084	DBG_BLOCK_ID_TD_BY16 = 0xb,
5085	DBG_BLOCK_ID_TD10_BY16 = 0xc,
5086	DBG_BLOCK_ID_LDS_BY16 = 0xd,
5087	DBG_BLOCK_ID_LDS10_BY16 = 0xe,
5088	} DebugBlockId_BY16;
5089	typedef enum SurfaceEndian {
5090	ENDIAN_NONE = 0x0,
5091	ENDIAN_8IN16 = 0x1,
5092	ENDIAN_8IN32 = 0x2,
5093	ENDIAN_8IN64 = 0x3,
5094	} SurfaceEndian;
5095	typedef enum ArrayMode {
5096	ARRAY_LINEAR_GENERAL = 0x0,
5097	ARRAY_LINEAR_ALIGNED = 0x1,
5098	ARRAY_1D_TILED_THIN1 = 0x2,
5099	ARRAY_1D_TILED_THICK = 0x3,
5100	ARRAY_2D_TILED_THIN1 = 0x4,
5101	ARRAY_PRT_TILED_THIN1 = 0x5,
5102	ARRAY_PRT_2D_TILED_THIN1 = 0x6,
5103	ARRAY_2D_TILED_THICK = 0x7,
5104	ARRAY_2D_TILED_XTHICK = 0x8,
5105	ARRAY_PRT_TILED_THICK = 0x9,
5106	ARRAY_PRT_2D_TILED_THICK = 0xa,
5107	ARRAY_PRT_3D_TILED_THIN1 = 0xb,
5108	ARRAY_3D_TILED_THIN1 = 0xc,
5109	ARRAY_3D_TILED_THICK = 0xd,
5110	ARRAY_3D_TILED_XTHICK = 0xe,
5111	ARRAY_PRT_3D_TILED_THICK = 0xf,
5112	} ArrayMode;
5113	typedef enum PipeTiling {
5114	CONFIG_1_PIPE = 0x0,
5115	CONFIG_2_PIPE = 0x1,
5116	CONFIG_4_PIPE = 0x2,
5117	CONFIG_8_PIPE = 0x3,
5118	} PipeTiling;
5119	typedef enum BankTiling {
5120	CONFIG_4_BANK = 0x0,
5121	CONFIG_8_BANK = 0x1,
5122	} BankTiling;
5123	typedef enum GroupInterleave {
5124	CONFIG_256B_GROUP = 0x0,
5125	CONFIG_512B_GROUP = 0x1,
5126	} GroupInterleave;
5127	typedef enum RowTiling {
5128	CONFIG_1KB_ROW = 0x0,
5129	CONFIG_2KB_ROW = 0x1,
5130	CONFIG_4KB_ROW = 0x2,
5131	CONFIG_8KB_ROW = 0x3,
5132	CONFIG_1KB_ROW_OPT = 0x4,
5133	CONFIG_2KB_ROW_OPT = 0x5,
5134	CONFIG_4KB_ROW_OPT = 0x6,
5135	CONFIG_8KB_ROW_OPT = 0x7,
5136	} RowTiling;
5137	typedef enum BankSwapBytes {
5138	CONFIG_128B_SWAPS = 0x0,
5139	CONFIG_256B_SWAPS = 0x1,
5140	CONFIG_512B_SWAPS = 0x2,
5141	CONFIG_1KB_SWAPS = 0x3,
5142	} BankSwapBytes;
5143	typedef enum SampleSplitBytes {
5144	CONFIG_1KB_SPLIT = 0x0,
5145	CONFIG_2KB_SPLIT = 0x1,
5146	CONFIG_4KB_SPLIT = 0x2,
5147	CONFIG_8KB_SPLIT = 0x3,
5148	} SampleSplitBytes;
5149	typedef enum NumPipes {
5150	ADDR_CONFIG_1_PIPE = 0x0,
5151	ADDR_CONFIG_2_PIPE = 0x1,
5152	ADDR_CONFIG_4_PIPE = 0x2,
5153	ADDR_CONFIG_8_PIPE = 0x3,
5154	} NumPipes;
5155	typedef enum PipeInterleaveSize {
5156	ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
5157	ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
5158	} PipeInterleaveSize;
5159	typedef enum BankInterleaveSize {
5160	ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
5161	ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
5162	ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
5163	ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
5164	} BankInterleaveSize;
5165	typedef enum NumShaderEngines {
5166	ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
5167	ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
5168	} NumShaderEngines;
5169	typedef enum ShaderEngineTileSize {
5170	ADDR_CONFIG_SE_TILE_16 = 0x0,
5171	ADDR_CONFIG_SE_TILE_32 = 0x1,
5172	} ShaderEngineTileSize;
5173	typedef enum NumGPUs {
5174	ADDR_CONFIG_1_GPU = 0x0,
5175	ADDR_CONFIG_2_GPU = 0x1,
5176	ADDR_CONFIG_4_GPU = 0x2,
5177	} NumGPUs;
5178	typedef enum MultiGPUTileSize {
5179	ADDR_CONFIG_GPU_TILE_16 = 0x0,
5180	ADDR_CONFIG_GPU_TILE_32 = 0x1,
5181	ADDR_CONFIG_GPU_TILE_64 = 0x2,
5182	ADDR_CONFIG_GPU_TILE_128 = 0x3,
5183	} MultiGPUTileSize;
5184	typedef enum RowSize {
5185	ADDR_CONFIG_1KB_ROW = 0x0,
5186	ADDR_CONFIG_2KB_ROW = 0x1,
5187	ADDR_CONFIG_4KB_ROW = 0x2,
5188	} RowSize;
5189	typedef enum NumLowerPipes {
5190	ADDR_CONFIG_1_LOWER_PIPES = 0x0,
5191	ADDR_CONFIG_2_LOWER_PIPES = 0x1,
5192	} NumLowerPipes;
5193	typedef enum ColorTransform {
5194	DCC_CT_AUTO = 0x0,
5195	DCC_CT_NONE = 0x1,
5196	ABGR_TO_A_BG_G_RB = 0x2,
5197	BGRA_TO_BG_G_RB_A = 0x3,
5198	} ColorTransform;
5199	typedef enum CompareRef {
5200	REF_NEVER = 0x0,
5201	REF_LESS = 0x1,
5202	REF_EQUAL = 0x2,
5203	REF_LEQUAL = 0x3,
5204	REF_GREATER = 0x4,
5205	REF_NOTEQUAL = 0x5,
5206	REF_GEQUAL = 0x6,
5207	REF_ALWAYS = 0x7,
5208	} CompareRef;
5209	typedef enum ReadSize {
5210	READ_256_BITS = 0x0,
5211	READ_512_BITS = 0x1,
5212	} ReadSize;
5213	typedef enum DepthFormat {
5214	DEPTH_INVALID = 0x0,
5215	DEPTH_16 = 0x1,
5216	DEPTH_X8_24 = 0x2,
5217	DEPTH_8_24 = 0x3,
5218	DEPTH_X8_24_FLOAT = 0x4,
5219	DEPTH_8_24_FLOAT = 0x5,
5220	DEPTH_32_FLOAT = 0x6,
5221	DEPTH_X24_8_32_FLOAT = 0x7,
5222	} DepthFormat;
5223	typedef enum ZFormat {
5224	Z_INVALID = 0x0,
5225	Z_16 = 0x1,
5226	Z_24 = 0x2,
5227	Z_32_FLOAT = 0x3,
5228	} ZFormat;
5229	typedef enum StencilFormat {
5230	STENCIL_INVALID = 0x0,
5231	STENCIL_8 = 0x1,
5232	} StencilFormat;
5233	typedef enum CmaskMode {
5234	CMASK_CLEAR_NONE = 0x0,
5235	CMASK_CLEAR_ONE = 0x1,
5236	CMASK_CLEAR_ALL = 0x2,
5237	CMASK_ANY_EXPANDED = 0x3,
5238	CMASK_ALPHA0_FRAG1 = 0x4,
5239	CMASK_ALPHA0_FRAG2 = 0x5,
5240	CMASK_ALPHA0_FRAG4 = 0x6,
5241	CMASK_ALPHA0_FRAGS = 0x7,
5242	CMASK_ALPHA1_FRAG1 = 0x8,
5243	CMASK_ALPHA1_FRAG2 = 0x9,
5244	CMASK_ALPHA1_FRAG4 = 0xa,
5245	CMASK_ALPHA1_FRAGS = 0xb,
5246	CMASK_ALPHAX_FRAG1 = 0xc,
5247	CMASK_ALPHAX_FRAG2 = 0xd,
5248	CMASK_ALPHAX_FRAG4 = 0xe,
5249	CMASK_ALPHAX_FRAGS = 0xf,
5250	} CmaskMode;
5251	typedef enum QuadExportFormat {
5252	EXPORT_UNUSED = 0x0,
5253	EXPORT_32_R = 0x1,
5254	EXPORT_32_GR = 0x2,
5255	EXPORT_32_AR = 0x3,
5256	EXPORT_FP16_ABGR = 0x4,
5257	EXPORT_UNSIGNED16_ABGR = 0x5,
5258	EXPORT_SIGNED16_ABGR = 0x6,
5259	EXPORT_32_ABGR = 0x7,
5260	} QuadExportFormat;
5261	typedef enum QuadExportFormatOld {
5262	EXPORT_4P_32BPC_ABGR = 0x0,
5263	EXPORT_4P_16BPC_ABGR = 0x1,
5264	EXPORT_4P_32BPC_GR = 0x2,
5265	EXPORT_4P_32BPC_AR = 0x3,
5266	EXPORT_2P_32BPC_ABGR = 0x4,
5267	EXPORT_8P_32BPC_R = 0x5,
5268	} QuadExportFormatOld;
5269	typedef enum ColorFormat {
5270	COLOR_INVALID = 0x0,
5271	COLOR_8 = 0x1,
5272	COLOR_16 = 0x2,
5273	COLOR_8_8 = 0x3,
5274	COLOR_32 = 0x4,
5275	COLOR_16_16 = 0x5,
5276	COLOR_10_11_11 = 0x6,
5277	COLOR_11_11_10 = 0x7,
5278	COLOR_10_10_10_2 = 0x8,
5279	COLOR_2_10_10_10 = 0x9,
5280	COLOR_8_8_8_8 = 0xa,
5281	COLOR_32_32 = 0xb,
5282	COLOR_16_16_16_16 = 0xc,
5283	COLOR_RESERVED_13 = 0xd,
5284	COLOR_32_32_32_32 = 0xe,
5285	COLOR_RESERVED_15 = 0xf,
5286	COLOR_5_6_5 = 0x10,
5287	COLOR_1_5_5_5 = 0x11,
5288	COLOR_5_5_5_1 = 0x12,
5289	COLOR_4_4_4_4 = 0x13,
5290	COLOR_8_24 = 0x14,
5291	COLOR_24_8 = 0x15,
5292	COLOR_X24_8_32_FLOAT = 0x16,
5293	COLOR_RESERVED_23 = 0x17,
5294	} ColorFormat;
5295	typedef enum SurfaceFormat {
5296	FMT_INVALID = 0x0,
5297	FMT_8 = 0x1,
5298	FMT_16 = 0x2,
5299	FMT_8_8 = 0x3,
5300	FMT_32 = 0x4,
5301	FMT_16_16 = 0x5,
5302	FMT_10_11_11 = 0x6,
5303	FMT_11_11_10 = 0x7,
5304	FMT_10_10_10_2 = 0x8,
5305	FMT_2_10_10_10 = 0x9,
5306	FMT_8_8_8_8 = 0xa,
5307	FMT_32_32 = 0xb,
5308	FMT_16_16_16_16 = 0xc,
5309	FMT_32_32_32 = 0xd,
5310	FMT_32_32_32_32 = 0xe,
5311	FMT_RESERVED_4 = 0xf,
5312	FMT_5_6_5 = 0x10,
5313	FMT_1_5_5_5 = 0x11,
5314	FMT_5_5_5_1 = 0x12,
5315	FMT_4_4_4_4 = 0x13,
5316	FMT_8_24 = 0x14,
5317	FMT_24_8 = 0x15,
5318	FMT_X24_8_32_FLOAT = 0x16,
5319	FMT_RESERVED_33 = 0x17,
5320	FMT_11_11_10_FLOAT = 0x18,
5321	FMT_16_FLOAT = 0x19,
5322	FMT_32_FLOAT = 0x1a,
5323	FMT_16_16_FLOAT = 0x1b,
5324	FMT_8_24_FLOAT = 0x1c,
5325	FMT_24_8_FLOAT = 0x1d,
5326	FMT_32_32_FLOAT = 0x1e,
5327	FMT_10_11_11_FLOAT = 0x1f,
5328	FMT_16_16_16_16_FLOAT = 0x20,
5329	FMT_3_3_2 = 0x21,
5330	FMT_6_5_5 = 0x22,
5331	FMT_32_32_32_32_FLOAT = 0x23,
5332	FMT_RESERVED_36 = 0x24,
5333	FMT_1 = 0x25,
5334	FMT_1_REVERSED = 0x26,
5335	FMT_GB_GR = 0x27,
5336	FMT_BG_RG = 0x28,
5337	FMT_32_AS_8 = 0x29,
5338	FMT_32_AS_8_8 = 0x2a,
5339	FMT_5_9_9_9_SHAREDEXP = 0x2b,
5340	FMT_8_8_8 = 0x2c,
5341	FMT_16_16_16 = 0x2d,
5342	FMT_16_16_16_FLOAT = 0x2e,
5343	FMT_4_4 = 0x2f,
5344	FMT_32_32_32_FLOAT = 0x30,
5345	FMT_BC1 = 0x31,
5346	FMT_BC2 = 0x32,
5347	FMT_BC3 = 0x33,
5348	FMT_BC4 = 0x34,
5349	FMT_BC5 = 0x35,
5350	FMT_BC6 = 0x36,
5351	FMT_BC7 = 0x37,
5352	FMT_32_AS_32_32_32_32 = 0x38,
5353	FMT_APC3 = 0x39,
5354	FMT_APC4 = 0x3a,
5355	FMT_APC5 = 0x3b,
5356	FMT_APC6 = 0x3c,
5357	FMT_APC7 = 0x3d,
5358	FMT_CTX1 = 0x3e,
5359	FMT_RESERVED_63 = 0x3f,
5360	} SurfaceFormat;
5361	typedef enum BUF_DATA_FORMAT {
5362	BUF_DATA_FORMAT_INVALID = 0x0,
5363	BUF_DATA_FORMAT_8 = 0x1,
5364	BUF_DATA_FORMAT_16 = 0x2,
5365	BUF_DATA_FORMAT_8_8 = 0x3,
5366	BUF_DATA_FORMAT_32 = 0x4,
5367	BUF_DATA_FORMAT_16_16 = 0x5,
5368	BUF_DATA_FORMAT_10_11_11 = 0x6,
5369	BUF_DATA_FORMAT_11_11_10 = 0x7,
5370	BUF_DATA_FORMAT_10_10_10_2 = 0x8,
5371	BUF_DATA_FORMAT_2_10_10_10 = 0x9,
5372	BUF_DATA_FORMAT_8_8_8_8 = 0xa,
5373	BUF_DATA_FORMAT_32_32 = 0xb,
5374	BUF_DATA_FORMAT_16_16_16_16 = 0xc,
5375	BUF_DATA_FORMAT_32_32_32 = 0xd,
5376	BUF_DATA_FORMAT_32_32_32_32 = 0xe,
5377	BUF_DATA_FORMAT_RESERVED_15 = 0xf,
5378	} BUF_DATA_FORMAT;
5379	typedef enum IMG_DATA_FORMAT {
5380	IMG_DATA_FORMAT_INVALID = 0x0,
5381	IMG_DATA_FORMAT_8 = 0x1,
5382	IMG_DATA_FORMAT_16 = 0x2,
5383	IMG_DATA_FORMAT_8_8 = 0x3,
5384	IMG_DATA_FORMAT_32 = 0x4,
5385	IMG_DATA_FORMAT_16_16 = 0x5,
5386	IMG_DATA_FORMAT_10_11_11 = 0x6,
5387	IMG_DATA_FORMAT_11_11_10 = 0x7,
5388	IMG_DATA_FORMAT_10_10_10_2 = 0x8,
5389	IMG_DATA_FORMAT_2_10_10_10 = 0x9,
5390	IMG_DATA_FORMAT_8_8_8_8 = 0xa,
5391	IMG_DATA_FORMAT_32_32 = 0xb,
5392	IMG_DATA_FORMAT_16_16_16_16 = 0xc,
5393	IMG_DATA_FORMAT_32_32_32 = 0xd,
5394	IMG_DATA_FORMAT_32_32_32_32 = 0xe,
5395	IMG_DATA_FORMAT_RESERVED_15 = 0xf,
5396	IMG_DATA_FORMAT_5_6_5 = 0x10,
5397	IMG_DATA_FORMAT_1_5_5_5 = 0x11,
5398	IMG_DATA_FORMAT_5_5_5_1 = 0x12,
5399	IMG_DATA_FORMAT_4_4_4_4 = 0x13,
5400	IMG_DATA_FORMAT_8_24 = 0x14,
5401	IMG_DATA_FORMAT_24_8 = 0x15,
5402	IMG_DATA_FORMAT_X24_8_32 = 0x16,
5403	IMG_DATA_FORMAT_RESERVED_23 = 0x17,
5404	IMG_DATA_FORMAT_RESERVED_24 = 0x18,
5405	IMG_DATA_FORMAT_RESERVED_25 = 0x19,
5406	IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
5407	IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
5408	IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
5409	IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
5410	IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
5411	IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
5412	IMG_DATA_FORMAT_GB_GR = 0x20,
5413	IMG_DATA_FORMAT_BG_RG = 0x21,
5414	IMG_DATA_FORMAT_5_9_9_9 = 0x22,
5415	IMG_DATA_FORMAT_BC1 = 0x23,
5416	IMG_DATA_FORMAT_BC2 = 0x24,
5417	IMG_DATA_FORMAT_BC3 = 0x25,
5418	IMG_DATA_FORMAT_BC4 = 0x26,
5419	IMG_DATA_FORMAT_BC5 = 0x27,
5420	IMG_DATA_FORMAT_BC6 = 0x28,
5421	IMG_DATA_FORMAT_BC7 = 0x29,
5422	IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
5423	IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
5424	IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
5425	IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
5426	IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
5427	IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
5428	IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
5429	IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
5430	IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
5431	IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
5432	IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
5433	IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
5434	IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
5435	IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
5436	IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
5437	IMG_DATA_FORMAT_4_4 = 0x39,
5438	IMG_DATA_FORMAT_6_5_5 = 0x3a,
5439	IMG_DATA_FORMAT_1 = 0x3b,
5440	IMG_DATA_FORMAT_1_REVERSED = 0x3c,
5441	IMG_DATA_FORMAT_32_AS_8 = 0x3d,
5442	IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
5443	IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
5444	} IMG_DATA_FORMAT;
5445	typedef enum BUF_NUM_FORMAT {
5446	BUF_NUM_FORMAT_UNORM = 0x0,
5447	BUF_NUM_FORMAT_SNORM = 0x1,
5448	BUF_NUM_FORMAT_USCALED = 0x2,
5449	BUF_NUM_FORMAT_SSCALED = 0x3,
5450	BUF_NUM_FORMAT_UINT = 0x4,
5451	BUF_NUM_FORMAT_SINT = 0x5,
5452	BUF_NUM_FORMAT_RESERVED_6 = 0x6,
5453	BUF_NUM_FORMAT_FLOAT = 0x7,
5454	} BUF_NUM_FORMAT;
5455	typedef enum IMG_NUM_FORMAT {
5456	IMG_NUM_FORMAT_UNORM = 0x0,
5457	IMG_NUM_FORMAT_SNORM = 0x1,
5458	IMG_NUM_FORMAT_USCALED = 0x2,
5459	IMG_NUM_FORMAT_SSCALED = 0x3,
5460	IMG_NUM_FORMAT_UINT = 0x4,
5461	IMG_NUM_FORMAT_SINT = 0x5,
5462	IMG_NUM_FORMAT_RESERVED_6 = 0x6,
5463	IMG_NUM_FORMAT_FLOAT = 0x7,
5464	IMG_NUM_FORMAT_RESERVED_8 = 0x8,
5465	IMG_NUM_FORMAT_SRGB = 0x9,
5466	IMG_NUM_FORMAT_RESERVED_10 = 0xa,
5467	IMG_NUM_FORMAT_RESERVED_11 = 0xb,
5468	IMG_NUM_FORMAT_RESERVED_12 = 0xc,
5469	IMG_NUM_FORMAT_RESERVED_13 = 0xd,
5470	IMG_NUM_FORMAT_RESERVED_14 = 0xe,
5471	IMG_NUM_FORMAT_RESERVED_15 = 0xf,
5472	} IMG_NUM_FORMAT;
5473	typedef enum TileType {
5474	ARRAY_COLOR_TILE = 0x0,
5475	ARRAY_DEPTH_TILE = 0x1,
5476	} TileType;
5477	typedef enum NonDispTilingOrder {
5478	ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
5479	ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
5480	} NonDispTilingOrder;
5481	typedef enum MicroTileMode {
5482	ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
5483	ADDR_SURF_THIN_MICRO_TILING = 0x1,
5484	ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
5485	ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
5486	ADDR_SURF_THICK_MICRO_TILING = 0x4,
5487	} MicroTileMode;
5488	typedef enum TileSplit {
5489	ADDR_SURF_TILE_SPLIT_64B = 0x0,
5490	ADDR_SURF_TILE_SPLIT_128B = 0x1,
5491	ADDR_SURF_TILE_SPLIT_256B = 0x2,
5492	ADDR_SURF_TILE_SPLIT_512B = 0x3,
5493	ADDR_SURF_TILE_SPLIT_1KB = 0x4,
5494	ADDR_SURF_TILE_SPLIT_2KB = 0x5,
5495	ADDR_SURF_TILE_SPLIT_4KB = 0x6,
5496	} TileSplit;
5497	typedef enum SampleSplit {
5498	ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
5499	ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
5500	ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
5501	ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
5502	} SampleSplit;
5503	typedef enum PipeConfig {
5504	ADDR_SURF_P2 = 0x0,
5505	ADDR_SURF_P2_RESERVED0 = 0x1,
5506	ADDR_SURF_P2_RESERVED1 = 0x2,
5507	ADDR_SURF_P2_RESERVED2 = 0x3,
5508	ADDR_SURF_P4_8x16 = 0x4,
5509	ADDR_SURF_P4_16x16 = 0x5,
5510	ADDR_SURF_P4_16x32 = 0x6,
5511	ADDR_SURF_P4_32x32 = 0x7,
5512	ADDR_SURF_P8_16x16_8x16 = 0x8,
5513	ADDR_SURF_P8_16x32_8x16 = 0x9,
5514	ADDR_SURF_P8_32x32_8x16 = 0xa,
5515	ADDR_SURF_P8_16x32_16x16 = 0xb,
5516	ADDR_SURF_P8_32x32_16x16 = 0xc,
5517	ADDR_SURF_P8_32x32_16x32 = 0xd,
5518	ADDR_SURF_P8_32x64_32x32 = 0xe,
5519	ADDR_SURF_P8_RESERVED0 = 0xf,
5520	ADDR_SURF_P16_32x32_8x16 = 0x10,
5521	ADDR_SURF_P16_32x32_16x16 = 0x11,
5522	} PipeConfig;
5523	typedef enum NumBanks {
5524	ADDR_SURF_2_BANK = 0x0,
5525	ADDR_SURF_4_BANK = 0x1,
5526	ADDR_SURF_8_BANK = 0x2,
5527	ADDR_SURF_16_BANK = 0x3,
5528	} NumBanks;
5529	typedef enum BankWidth {
5530	ADDR_SURF_BANK_WIDTH_1 = 0x0,
5531	ADDR_SURF_BANK_WIDTH_2 = 0x1,
5532	ADDR_SURF_BANK_WIDTH_4 = 0x2,
5533	ADDR_SURF_BANK_WIDTH_8 = 0x3,
5534	} BankWidth;
5535	typedef enum BankHeight {
5536	ADDR_SURF_BANK_HEIGHT_1 = 0x0,
5537	ADDR_SURF_BANK_HEIGHT_2 = 0x1,
5538	ADDR_SURF_BANK_HEIGHT_4 = 0x2,
5539	ADDR_SURF_BANK_HEIGHT_8 = 0x3,
5540	} BankHeight;
5541	typedef enum BankWidthHeight {
5542	ADDR_SURF_BANK_WH_1 = 0x0,
5543	ADDR_SURF_BANK_WH_2 = 0x1,
5544	ADDR_SURF_BANK_WH_4 = 0x2,
5545	ADDR_SURF_BANK_WH_8 = 0x3,
5546	} BankWidthHeight;
5547	typedef enum MacroTileAspect {
5548	ADDR_SURF_MACRO_ASPECT_1 = 0x0,
5549	ADDR_SURF_MACRO_ASPECT_2 = 0x1,
5550	ADDR_SURF_MACRO_ASPECT_4 = 0x2,
5551	ADDR_SURF_MACRO_ASPECT_8 = 0x3,
5552	} MacroTileAspect;
5553	typedef enum GATCL1RequestType {
5554	GATCL1_TYPE_NORMAL = 0x0,
5555	GATCL1_TYPE_SHOOTDOWN = 0x1,
5556	GATCL1_TYPE_BYPASS = 0x2,
5557	} GATCL1RequestType;
5558	typedef enum TCC_CACHE_POLICIES {
5559	TCC_CACHE_POLICY_LRU = 0x0,
5560	TCC_CACHE_POLICY_STREAM = 0x1,
5561	} TCC_CACHE_POLICIES;
5562	typedef enum MTYPE {
5563	MTYPE_NC_NV = 0x0,
5564	MTYPE_NC = 0x1,
5565	MTYPE_CC = 0x2,
5566	MTYPE_UC = 0x3,
5567	} MTYPE;
5568	typedef enum PERFMON_COUNTER_MODE {
5569	PERFMON_COUNTER_MODE_ACCUM = 0x0,
5570	PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
5571	PERFMON_COUNTER_MODE_MAX = 0x2,
5572	PERFMON_COUNTER_MODE_DIRTY = 0x3,
5573	PERFMON_COUNTER_MODE_SAMPLE = 0x4,
5574	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
5575	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
5576	PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
5577	PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
5578	PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
5579	PERFMON_COUNTER_MODE_RESERVED = 0xf,
5580	} PERFMON_COUNTER_MODE;
5581	typedef enum PERFMON_SPM_MODE {
5582	PERFMON_SPM_MODE_OFF = 0x0,
5583	PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
5584	PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
5585	PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
5586	PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
5587	PERFMON_SPM_MODE_RESERVED_5 = 0x5,
5588	PERFMON_SPM_MODE_RESERVED_6 = 0x6,
5589	PERFMON_SPM_MODE_RESERVED_7 = 0x7,
5590	PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
5591	PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
5592	PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
5593	} PERFMON_SPM_MODE;
5594	typedef enum SurfaceTiling {
5595	ARRAY_LINEAR = 0x0,
5596	ARRAY_TILED = 0x1,
5597	} SurfaceTiling;
5598	typedef enum SurfaceArray {
5599	ARRAY_1D = 0x0,
5600	ARRAY_2D = 0x1,
5601	ARRAY_3D = 0x2,
5602	ARRAY_3D_SLICE = 0x3,
5603	} SurfaceArray;
5604	typedef enum ColorArray {
5605	ARRAY_2D_ALT_COLOR = 0x0,
5606	ARRAY_2D_COLOR = 0x1,
5607	ARRAY_3D_SLICE_COLOR = 0x3,
5608	} ColorArray;
5609	typedef enum DepthArray {
5610	ARRAY_2D_ALT_DEPTH = 0x0,
5611	ARRAY_2D_DEPTH = 0x1,
5612	} DepthArray;
5613	typedef enum ENUM_NUM_SIMD_PER_CU {
5614	NUM_SIMD_PER_CU = 0x4,
5615	} ENUM_NUM_SIMD_PER_CU;
5616	typedef enum MEM_PWR_FORCE_CTRL {
5617	NO_FORCE_REQUEST = 0x0,
5618	FORCE_LIGHT_SLEEP_REQUEST = 0x1,
5619	FORCE_DEEP_SLEEP_REQUEST = 0x2,
5620	FORCE_SHUT_DOWN_REQUEST = 0x3,
5621	} MEM_PWR_FORCE_CTRL;
5622	typedef enum MEM_PWR_FORCE_CTRL2 {
5623	NO_FORCE_REQ = 0x0,
5624	FORCE_LIGHT_SLEEP_REQ = 0x1,
5625	} MEM_PWR_FORCE_CTRL2;
5626	typedef enum MEM_PWR_DIS_CTRL {
5627	ENABLE_MEM_PWR_CTRL = 0x0,
5628	DISABLE_MEM_PWR_CTRL = 0x1,
5629	} MEM_PWR_DIS_CTRL;
5630	typedef enum MEM_PWR_SEL_CTRL {
5631	DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
5632	DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
5633	DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
5634	} MEM_PWR_SEL_CTRL;
5635	typedef enum MEM_PWR_SEL_CTRL2 {
5636	DYNAMIC_DEEP_SLEEP_EN = 0x0,
5637	DYNAMIC_LIGHT_SLEEP_EN = 0x1,
5638	} MEM_PWR_SEL_CTRL2;
5639	typedef enum HPD_INT_CONTROL_ACK {
5640	HPD_INT_CONTROL_ACK_0 = 0x0,
5641	HPD_INT_CONTROL_ACK_1 = 0x1,
5642	} HPD_INT_CONTROL_ACK;
5643	typedef enum HPD_INT_CONTROL_POLARITY {
5644	HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0,
5645	HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1,
5646	} HPD_INT_CONTROL_POLARITY;
5647	typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5648	HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0,
5649	HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1,
5650	} HPD_INT_CONTROL_RX_INT_ACK;
5651	typedef enum DPDBG_EN {
5652	DPDBG_DISABLE = 0x0,
5653	DPDBG_ENABLE = 0x1,
5654	} DPDBG_EN;
5655	typedef enum DPDBG_INPUT_EN {
5656	DPDBG_INPUT_DISABLE = 0x0,
5657	DPDBG_INPUT_ENABLE = 0x1,
5658	} DPDBG_INPUT_EN;
5659	typedef enum DPDBG_ERROR_DETECTION_MODE {
5660	DPDBG_ERROR_DETECTION_MODE_CSC = 0x0,
5661	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1,
5662	} DPDBG_ERROR_DETECTION_MODE;
5663	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
5664	DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0,
5665	DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1,
5666	} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
5667	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
5668	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0,
5669	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1,
5670	} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
5671	typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
5672	DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0,
5673	DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1,
5674	} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
5675	typedef enum PM_ASSERT_RESET {
5676	PM_ASSERT_RESET_0 = 0x0,
5677	PM_ASSERT_RESET_1 = 0x1,
5678	} PM_ASSERT_RESET;
5679	typedef enum DAC_MUX_SELECT {
5680	DAC_MUX_SELECT_DACA = 0x0,
5681	DAC_MUX_SELECT_DACB = 0x1,
5682	} DAC_MUX_SELECT;
5683	typedef enum TMDS_DVO_MUX_SELECT {
5684	TMDS_DVO_MUX_SELECT_B = 0x0,
5685	TMDS_DVO_MUX_SELECT_G = 0x1,
5686	TMDS_DVO_MUX_SELECT_R = 0x2,
5687	TMDS_DVO_MUX_SELECT_RESERVED = 0x3,
5688	} TMDS_DVO_MUX_SELECT;
5689	typedef enum DACA_SOFT_RESET {
5690	DACA_SOFT_RESET_0 = 0x0,
5691	DACA_SOFT_RESET_1 = 0x1,
5692	} DACA_SOFT_RESET;
5693	typedef enum I2S0_SPDIF0_SOFT_RESET {
5694	I2S0_SPDIF0_SOFT_RESET_0 = 0x0,
5695	I2S0_SPDIF0_SOFT_RESET_1 = 0x1,
5696	} I2S0_SPDIF0_SOFT_RESET;
5697	typedef enum I2S1_SOFT_RESET {
5698	I2S1_SOFT_RESET_0 = 0x0,
5699	I2S1_SOFT_RESET_1 = 0x1,
5700	} I2S1_SOFT_RESET;
5701	typedef enum SPDIF1_SOFT_RESET {
5702	SPDIF1_SOFT_RESET_0 = 0x0,
5703	SPDIF1_SOFT_RESET_1 = 0x1,
5704	} SPDIF1_SOFT_RESET;
5705	typedef enum DB_CLK_SOFT_RESET {
5706	DB_CLK_SOFT_RESET_0 = 0x0,
5707	DB_CLK_SOFT_RESET_1 = 0x1,
5708	} DB_CLK_SOFT_RESET;
5709	typedef enum FMT0_SOFT_RESET {
5710	FMT0_SOFT_RESET_0 = 0x0,
5711	FMT0_SOFT_RESET_1 = 0x1,
5712	} FMT0_SOFT_RESET;
5713	typedef enum FMT1_SOFT_RESET {
5714	FMT1_SOFT_RESET_0 = 0x0,
5715	FMT1_SOFT_RESET_1 = 0x1,
5716	} FMT1_SOFT_RESET;
5717	typedef enum FMT2_SOFT_RESET {
5718	FMT2_SOFT_RESET_0 = 0x0,
5719	FMT2_SOFT_RESET_1 = 0x1,
5720	} FMT2_SOFT_RESET;
5721	typedef enum FMT3_SOFT_RESET {
5722	FMT3_SOFT_RESET_0 = 0x0,
5723	FMT3_SOFT_RESET_1 = 0x1,
5724	} FMT3_SOFT_RESET;
5725	typedef enum FMT4_SOFT_RESET {
5726	FMT4_SOFT_RESET_0 = 0x0,
5727	FMT4_SOFT_RESET_1 = 0x1,
5728	} FMT4_SOFT_RESET;
5729	typedef enum FMT5_SOFT_RESET {
5730	FMT5_SOFT_RESET_0 = 0x0,
5731	FMT5_SOFT_RESET_1 = 0x1,
5732	} FMT5_SOFT_RESET;
5733	typedef enum MVP_SOFT_RESET {
5734	MVP_SOFT_RESET_0 = 0x0,
5735	MVP_SOFT_RESET_1 = 0x1,
5736	} MVP_SOFT_RESET;
5737	typedef enum ABM_SOFT_RESET {
5738	ABM_SOFT_RESET_0 = 0x0,
5739	ABM_SOFT_RESET_1 = 0x1,
5740	} ABM_SOFT_RESET;
5741	typedef enum DVO_SOFT_RESET {
5742	DVO_SOFT_RESET_0 = 0x0,
5743	DVO_SOFT_RESET_1 = 0x1,
5744	} DVO_SOFT_RESET;
5745	typedef enum DIGA_FE_SOFT_RESET {
5746	DIGA_FE_SOFT_RESET_0 = 0x0,
5747	DIGA_FE_SOFT_RESET_1 = 0x1,
5748	} DIGA_FE_SOFT_RESET;
5749	typedef enum DIGA_BE_SOFT_RESET {
5750	DIGA_BE_SOFT_RESET_0 = 0x0,
5751	DIGA_BE_SOFT_RESET_1 = 0x1,
5752	} DIGA_BE_SOFT_RESET;
5753	typedef enum DIGB_FE_SOFT_RESET {
5754	DIGB_FE_SOFT_RESET_0 = 0x0,
5755	DIGB_FE_SOFT_RESET_1 = 0x1,
5756	} DIGB_FE_SOFT_RESET;
5757	typedef enum DIGB_BE_SOFT_RESET {
5758	DIGB_BE_SOFT_RESET_0 = 0x0,
5759	DIGB_BE_SOFT_RESET_1 = 0x1,
5760	} DIGB_BE_SOFT_RESET;
5761	typedef enum DIGC_FE_SOFT_RESET {
5762	DIGC_FE_SOFT_RESET_0 = 0x0,
5763	DIGC_FE_SOFT_RESET_1 = 0x1,
5764	} DIGC_FE_SOFT_RESET;
5765	typedef enum DIGC_BE_SOFT_RESET {
5766	DIGC_BE_SOFT_RESET_0 = 0x0,
5767	DIGC_BE_SOFT_RESET_1 = 0x1,
5768	} DIGC_BE_SOFT_RESET;
5769	typedef enum DIGD_FE_SOFT_RESET {
5770	DIGD_FE_SOFT_RESET_0 = 0x0,
5771	DIGD_FE_SOFT_RESET_1 = 0x1,
5772	} DIGD_FE_SOFT_RESET;
5773	typedef enum DIGD_BE_SOFT_RESET {
5774	DIGD_BE_SOFT_RESET_0 = 0x0,
5775	DIGD_BE_SOFT_RESET_1 = 0x1,
5776	} DIGD_BE_SOFT_RESET;
5777	typedef enum DIGE_FE_SOFT_RESET {
5778	DIGE_FE_SOFT_RESET_0 = 0x0,
5779	DIGE_FE_SOFT_RESET_1 = 0x1,
5780	} DIGE_FE_SOFT_RESET;
5781	typedef enum DIGE_BE_SOFT_RESET {
5782	DIGE_BE_SOFT_RESET_0 = 0x0,
5783	DIGE_BE_SOFT_RESET_1 = 0x1,
5784	} DIGE_BE_SOFT_RESET;
5785	typedef enum DIGF_FE_SOFT_RESET {
5786	DIGF_FE_SOFT_RESET_0 = 0x0,
5787	DIGF_FE_SOFT_RESET_1 = 0x1,
5788	} DIGF_FE_SOFT_RESET;
5789	typedef enum DIGF_BE_SOFT_RESET {
5790	DIGF_BE_SOFT_RESET_0 = 0x0,
5791	DIGF_BE_SOFT_RESET_1 = 0x1,
5792	} DIGF_BE_SOFT_RESET;
5793	typedef enum DIGG_FE_SOFT_RESET {
5794	DIGG_FE_SOFT_RESET_0 = 0x0,
5795	DIGG_FE_SOFT_RESET_1 = 0x1,
5796	} DIGG_FE_SOFT_RESET;
5797	typedef enum DIGG_BE_SOFT_RESET {
5798	DIGG_BE_SOFT_RESET_0 = 0x0,
5799	DIGG_BE_SOFT_RESET_1 = 0x1,
5800	} DIGG_BE_SOFT_RESET;
5801	typedef enum DPDBG_SOFT_RESET {
5802	DPDBG_SOFT_RESET_0 = 0x0,
5803	DPDBG_SOFT_RESET_1 = 0x1,
5804	} DPDBG_SOFT_RESET;
5805	typedef enum DIGLPA_FE_SOFT_RESET {
5806	DIGLPA_FE_SOFT_RESET_0 = 0x0,
5807	DIGLPA_FE_SOFT_RESET_1 = 0x1,
5808	} DIGLPA_FE_SOFT_RESET;
5809	typedef enum DIGLPA_BE_SOFT_RESET {
5810	DIGLPA_BE_SOFT_RESET_0 = 0x0,
5811	DIGLPA_BE_SOFT_RESET_1 = 0x1,
5812	} DIGLPA_BE_SOFT_RESET;
5813	typedef enum DIGLPB_FE_SOFT_RESET {
5814	DIGLPB_FE_SOFT_RESET_0 = 0x0,
5815	DIGLPB_FE_SOFT_RESET_1 = 0x1,
5816	} DIGLPB_FE_SOFT_RESET;
5817	typedef enum DIGLPB_BE_SOFT_RESET {
5818	DIGLPB_BE_SOFT_RESET_0 = 0x0,
5819	DIGLPB_BE_SOFT_RESET_1 = 0x1,
5820	} DIGLPB_BE_SOFT_RESET;
5821	typedef enum GENERICA_STEREOSYNC_SEL {
5822	GENERICA_STEREOSYNC_SEL_D1 = 0x0,
5823	GENERICA_STEREOSYNC_SEL_D2 = 0x1,
5824	GENERICA_STEREOSYNC_SEL_D3 = 0x2,
5825	GENERICA_STEREOSYNC_SEL_D4 = 0x3,
5826	GENERICA_STEREOSYNC_SEL_D5 = 0x4,
5827	GENERICA_STEREOSYNC_SEL_D6 = 0x5,
5828	GENERICA_STEREOSYNC_SEL_RESERVED = 0x6,
5829	} GENERICA_STEREOSYNC_SEL;
5830	typedef enum GENERICB_STEREOSYNC_SEL {
5831	GENERICB_STEREOSYNC_SEL_D1 = 0x0,
5832	GENERICB_STEREOSYNC_SEL_D2 = 0x1,
5833	GENERICB_STEREOSYNC_SEL_D3 = 0x2,
5834	GENERICB_STEREOSYNC_SEL_D4 = 0x3,
5835	GENERICB_STEREOSYNC_SEL_D5 = 0x4,
5836	GENERICB_STEREOSYNC_SEL_D6 = 0x5,
5837	GENERICB_STEREOSYNC_SEL_RESERVED = 0x6,
5838	} GENERICB_STEREOSYNC_SEL;
5839	typedef enum DCO_DBG_BLOCK_SEL {
5840	DCO_DBG_BLOCK_SEL_DCO = 0x0,
5841	DCO_DBG_BLOCK_SEL_ABM = 0x1,
5842	DCO_DBG_BLOCK_SEL_DVO = 0x2,
5843	DCO_DBG_BLOCK_SEL_DAC = 0x3,
5844	DCO_DBG_BLOCK_SEL_MVP = 0x4,
5845	DCO_DBG_BLOCK_SEL_FMT0 = 0x5,
5846	DCO_DBG_BLOCK_SEL_FMT1 = 0x6,
5847	DCO_DBG_BLOCK_SEL_FMT2 = 0x7,
5848	DCO_DBG_BLOCK_SEL_FMT3 = 0x8,
5849	DCO_DBG_BLOCK_SEL_FMT4 = 0x9,
5850	DCO_DBG_BLOCK_SEL_FMT5 = 0xa,
5851	DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb,
5852	DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc,
5853	DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd,
5854	DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe,
5855	DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf,
5856	DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10,
5857	DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11,
5858	DCO_DBG_BLOCK_SEL_DIGA = 0x12,
5859	DCO_DBG_BLOCK_SEL_DIGB = 0x13,
5860	DCO_DBG_BLOCK_SEL_DIGC = 0x14,
5861	DCO_DBG_BLOCK_SEL_DIGD = 0x15,
5862	DCO_DBG_BLOCK_SEL_DIGE = 0x16,
5863	DCO_DBG_BLOCK_SEL_DIGF = 0x17,
5864	DCO_DBG_BLOCK_SEL_DIGG = 0x18,
5865	DCO_DBG_BLOCK_SEL_DPFE_A = 0x19,
5866	DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a,
5867	DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b,
5868	DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c,
5869	DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d,
5870	DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e,
5871	DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f,
5872	DCO_DBG_BLOCK_SEL_DPA = 0x20,
5873	DCO_DBG_BLOCK_SEL_DPB = 0x21,
5874	DCO_DBG_BLOCK_SEL_DPC = 0x22,
5875	DCO_DBG_BLOCK_SEL_DPD = 0x23,
5876	DCO_DBG_BLOCK_SEL_DPE = 0x24,
5877	DCO_DBG_BLOCK_SEL_DPF = 0x25,
5878	DCO_DBG_BLOCK_SEL_DPG = 0x26,
5879	DCO_DBG_BLOCK_SEL_AUX0 = 0x27,
5880	DCO_DBG_BLOCK_SEL_AUX1 = 0x28,
5881	DCO_DBG_BLOCK_SEL_AUX2 = 0x29,
5882	DCO_DBG_BLOCK_SEL_AUX3 = 0x2a,
5883	DCO_DBG_BLOCK_SEL_AUX4 = 0x2b,
5884	DCO_DBG_BLOCK_SEL_AUX5 = 0x2c,
5885	DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d,
5886	DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e,
5887	DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f,
5888	DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30,
5889	DCO_DBG_BLOCK_SEL_DIGLPA = 0x31,
5890	DCO_DBG_BLOCK_SEL_DIGLPB = 0x32,
5891	DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33,
5892	DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34,
5893	DCO_DBG_BLOCK_SEL_DPLPA = 0x35,
5894	DCO_DBG_BLOCK_SEL_DPLPB = 0x36,
5895	} DCO_DBG_BLOCK_SEL;
5896	typedef enum DCO_DBG_CLOCK_SEL {
5897	DCO_DBG_CLOCK_SEL_DISPCLK = 0x0,
5898	DCO_DBG_CLOCK_SEL_SCLK = 0x1,
5899	DCO_DBG_CLOCK_SEL_MVPCLK = 0x2,
5900	DCO_DBG_CLOCK_SEL_DVOCLK = 0x3,
5901	DCO_DBG_CLOCK_SEL_DACCLK = 0x4,
5902	DCO_DBG_CLOCK_SEL_REFCLK = 0x5,
5903	DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6,
5904	DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7,
5905	DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8,
5906	DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9,
5907	DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa,
5908	DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb,
5909	DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc,
5910	DCO_DBG_CLOCK_SEL_RESERVED = 0xd,
5911	DCO_DBG_CLOCK_SEL_AM0CLK = 0xe,
5912	DCO_DBG_CLOCK_SEL_AM1CLK = 0xf,
5913	DCO_DBG_CLOCK_SEL_AM2CLK = 0x10,
5914	DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11,
5915	DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12,
5916	} DCO_DBG_CLOCK_SEL;
5917	typedef enum DOUT_I2C_CONTROL_GO {
5918	DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0,
5919	DOUT_I2C_CONTROL_START_TRANSFER = 0x1,
5920	} DOUT_I2C_CONTROL_GO;
5921	typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
5922	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0,
5923	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1,
5924	} DOUT_I2C_CONTROL_SOFT_RESET;
5925	typedef enum DOUT_I2C_CONTROL_SEND_RESET {
5926	DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0,
5927	DOUT_I2C_CONTROL__SEND_RESET = 0x1,
5928	} DOUT_I2C_CONTROL_SEND_RESET;
5929	typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
5930	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0,
5931	DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1,
5932	} DOUT_I2C_CONTROL_SW_STATUS_RESET;
5933	typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
5934	DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0,
5935	DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1,
5936	DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2,
5937	DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3,
5938	DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4,
5939	DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5,
5940	DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6,
5941	} DOUT_I2C_CONTROL_DDC_SELECT;
5942	typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
5943	DOUT_I2C_CONTROL_TRANS0 = 0x0,
5944	DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1,
5945	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2,
5946	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3,
5947	} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
5948	typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
5949	DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0,
5950	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1,
5951	} DOUT_I2C_CONTROL_DBG_REF_SEL;
5952	typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
5953	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0,
5954	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1,
5955	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2,
5956	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3,
5957	} DOUT_I2C_ARBITRATION_SW_PRIORITY;
5958	typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
5959	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0,
5960	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1,
5961	} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
5962	typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
5963	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0,
5964	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1,
5965	} DOUT_I2C_ARBITRATION_ABORT_XFER;
5966	typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
5967	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0,
5968	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1,
5969	} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
5970	typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
5971	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0,
5972	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1,
5973	} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
5974	typedef enum DOUT_I2C_ACK {
5975	DOUT_I2C_NO_ACK = 0x0,
5976	DOUT_I2C_ACK_TO_CLEAN = 0x1,
5977	} DOUT_I2C_ACK;
5978	typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
5979	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0,
5980	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
5981	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
5982	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
5983	} DOUT_I2C_DDC_SPEED_THRESHOLD;
5984	typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
5985	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
5986	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1,
5987	} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
5988	typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
5989	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0,
5990	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1,
5991	} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
5992	typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
5993	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0,
5994	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1,
5995	} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
5996	typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
5997	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
5998	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1,
5999	} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
6000	typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
6001	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0,
6002	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1,
6003	} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
6004	typedef enum DOUT_I2C_DATA_INDEX_WRITE {
6005	DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0,
6006	DOUT_I2C_DATA__INDEX_WRITE = 0x1,
6007	} DOUT_I2C_DATA_INDEX_WRITE;
6008	typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
6009	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
6010	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
6011	} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
6012	typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
6013	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0,
6014	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1,
6015	} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
6016	typedef enum BLNDV_CONTROL_BLND_MODE {
6017	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
6018	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
6019	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
6020	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
6021	} BLNDV_CONTROL_BLND_MODE;
6022	typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
6023	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
6024	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
6025	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
6026	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
6027	} BLNDV_CONTROL_BLND_STEREO_TYPE;
6028	typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
6029	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
6030	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
6031	} BLNDV_CONTROL_BLND_STEREO_POLARITY;
6032	typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
6033	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
6034	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
6035	} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
6036	typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
6037	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
6038	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
6039	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
6040	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
6041	} BLNDV_CONTROL_BLND_ALPHA_MODE;
6042	typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
6043	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
6044	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
6045	} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
6046	typedef enum BLNDV_SM_CONTROL2_SM_MODE {
6047	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
6048	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
6049	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
6050	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
6051	} BLNDV_SM_CONTROL2_SM_MODE;
6052	typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
6053	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
6054	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
6055	} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
6056	typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
6057	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
6058	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
6059	} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
6060	typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6061	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
6062	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
6063	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
6064	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
6065	} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6066	typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6067	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
6068	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
6069	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
6070	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
6071	} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6072	typedef enum BLNDV_CONTROL2_PTI_ENABLE {
6073	BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0,
6074	BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1,
6075	} BLNDV_CONTROL2_PTI_ENABLE;
6076	typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6077	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
6078	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
6079	} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6080	typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6081	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
6082	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
6083	} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6084	typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6085	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
6086	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
6087	} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6088	typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6089	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
6090	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
6091	} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6092	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6093	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
6094	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
6095	} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6096	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
6097	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
6098	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
6099	} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
6100	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
6101	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
6102	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
6103	} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
6104	typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
6105	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
6106	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
6107	} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
6108	typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
6109	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
6110	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
6111	} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
6112	typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
6113	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
6114	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
6115	} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
6116	typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
6117	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
6118	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
6119	} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
6120	typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
6121	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
6122	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
6123	} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
6124	typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
6125	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
6126	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
6127	} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
6128
6129	#endif /* DCE_11_0_ENUM_H */
6130