1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "../dmub_srv.h"
27#include "dmub_reg.h"
28#include "dmub_dcn20.h"
29
30#include "dcn/dcn_2_0_0_offset.h"
31#include "dcn/dcn_2_0_0_sh_mask.h"
32#include "soc15_hw_ip.h"
33#include "vega10_ip_offset.h"
34
35#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
36#define CTX dmub
37#define REGS dmub->regs
38
39/* Registers. */
40
41const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
42#define DMUB_SR(reg) REG_OFFSET(reg),
43 {
44 DMUB_COMMON_REGS()
45 DMCUB_INTERNAL_REGS()
46 },
47#undef DMUB_SR
48
49#define DMUB_SF(reg, field) FD_MASK(reg, field),
50 { DMUB_COMMON_FIELDS() },
51#undef DMUB_SF
52
53#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
54 { DMUB_COMMON_FIELDS() },
55#undef DMUB_SF
56};
57
58/* Shared functions. */
59
60static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
61 uint64_t *fb_base,
62 uint64_t *fb_offset)
63{
64 uint32_t tmp;
65
66 if (dmub->fb_base || dmub->fb_offset) {
67 *fb_base = dmub->fb_base;
68 *fb_offset = dmub->fb_offset;
69 return;
70 }
71
72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
73 *fb_base = (uint64_t)tmp << 24;
74
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
76 *fb_offset = (uint64_t)tmp << 24;
77}
78
79static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
80 uint64_t fb_base,
81 uint64_t fb_offset,
82 union dmub_addr *addr_out)
83{
84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
85}
86
87bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
88{
89 /* Cached inbox is not supported in this fw version range */
90 return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
91 dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
92}
93
94void dmub_dcn20_reset(struct dmub_srv *dmub)
95{
96 union dmub_gpint_data_register cmd;
97 const uint32_t timeout = 30;
98 uint32_t in_reset, scratch, i;
99
100 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
101
102 if (in_reset == 0) {
103 cmd.bits.status = 1;
104 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
105 cmd.bits.param = 0;
106
107 dmub->hw_funcs.set_gpint(dmub, cmd);
108
109 /**
110 * Timeout covers both the ACK and the wait
111 * for remaining work to finish.
112 *
113 * This is mostly bound by the PHY disable sequence.
114 * Each register check will be greater than 1us, so
115 * don't bother using udelay.
116 */
117
118 for (i = 0; i < timeout; ++i) {
119 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
120 break;
121 }
122
123 for (i = 0; i < timeout; ++i) {
124 scratch = dmub->hw_funcs.get_gpint_response(dmub);
125 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
126 break;
127 }
128
129 /* Clear the GPINT command manually so we don't reset again. */
130 cmd.all = 0;
131 dmub->hw_funcs.set_gpint(dmub, cmd);
132
133 /* Force reset in case we timed out, DMCUB is likely hung. */
134 }
135
136 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
137 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
138 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
139 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
140 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
141 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
142 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
143 REG_WRITE(DMCUB_SCRATCH0, 0);
144}
145
146void dmub_dcn20_reset_release(struct dmub_srv *dmub)
147{
148 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
149 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
150 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
151 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
152}
153
154void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
155 const struct dmub_window *cw0,
156 const struct dmub_window *cw1)
157{
158 union dmub_addr offset;
159 uint64_t fb_base, fb_offset;
160
161 dmub_dcn20_get_fb_base_offset(dmub, fb_base: &fb_base, fb_offset: &fb_offset);
162
163 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
164 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
165 DMCUB_MEM_WRITE_SPACE, 0x3);
166
167 dmub_dcn20_translate_addr(addr_in: &cw0->offset, fb_base, fb_offset, addr_out: &offset);
168
169 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
171 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
172 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
173 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
174 DMCUB_REGION3_CW0_ENABLE, 1);
175
176 dmub_dcn20_translate_addr(addr_in: &cw1->offset, fb_base, fb_offset, addr_out: &offset);
177
178 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
179 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
180 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
181 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
182 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
183 DMCUB_REGION3_CW1_ENABLE, 1);
184
185 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
186 0x20);
187}
188
189void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
190 const struct dmub_window *cw2,
191 const struct dmub_window *cw3,
192 const struct dmub_window *cw4,
193 const struct dmub_window *cw5,
194 const struct dmub_window *cw6,
195 const struct dmub_window *region6)
196{
197 union dmub_addr offset;
198 uint64_t fb_base, fb_offset;
199
200 dmub_dcn20_get_fb_base_offset(dmub, fb_base: &fb_base, fb_offset: &fb_offset);
201
202 if (cw2->region.base != cw2->region.top) {
203 dmub_dcn20_translate_addr(addr_in: &cw2->offset, fb_base, fb_offset,
204 addr_out: &offset);
205
206 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
207 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
208 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
209 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
210 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
211 DMCUB_REGION3_CW2_ENABLE, 1);
212 } else {
213 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
214 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
215 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
216 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
217 }
218
219 dmub_dcn20_translate_addr(addr_in: &cw3->offset, fb_base, fb_offset, addr_out: &offset);
220
221 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
222 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
223 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
224 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
225 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
226 DMCUB_REGION3_CW3_ENABLE, 1);
227
228 /* TODO: Move this to CW4. */
229 dmub_dcn20_translate_addr(addr_in: &cw4->offset, fb_base, fb_offset, addr_out: &offset);
230
231 /* New firmware can support CW4. */
232 if (dmub_dcn20_use_cached_inbox(dmub)) {
233 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
234 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
235 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
236 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
237 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
238 DMCUB_REGION3_CW4_ENABLE, 1);
239 } else {
240 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
241 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
242 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
243 DMCUB_REGION4_TOP_ADDRESS,
244 cw4->region.top - cw4->region.base - 1,
245 DMCUB_REGION4_ENABLE, 1);
246 }
247
248 dmub_dcn20_translate_addr(addr_in: &cw5->offset, fb_base, fb_offset, addr_out: &offset);
249
250 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
251 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
252 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
253 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
254 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
255 DMCUB_REGION3_CW5_ENABLE, 1);
256
257 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
258 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
259 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
260 DMCUB_REGION5_TOP_ADDRESS,
261 cw5->region.top - cw5->region.base - 1,
262 DMCUB_REGION5_ENABLE, 1);
263
264 dmub_dcn20_translate_addr(addr_in: &cw6->offset, fb_base, fb_offset, addr_out: &offset);
265
266 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
267 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
268 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
269 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
270 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
271 DMCUB_REGION3_CW6_ENABLE, 1);
272}
273
274void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
275 const struct dmub_region *inbox1)
276{
277 /* New firmware can support CW4 for the inbox. */
278 if (dmub_dcn20_use_cached_inbox(dmub))
279 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
280 else
281 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
282
283 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
284}
285
286uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)
287{
288 return REG_READ(DMCUB_INBOX1_WPTR);
289}
290
291uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
292{
293 return REG_READ(DMCUB_INBOX1_RPTR);
294}
295
296void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
297{
298 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
299}
300
301void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
302 const struct dmub_region *outbox1)
303{
304 /* New firmware can support CW4 for the outbox. */
305 if (dmub_dcn20_use_cached_inbox(dmub))
306 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
307 else
308 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
309
310 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
311}
312
313uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
314{
315 /**
316 * outbox1 wptr register is accessed without locks (dal & dc)
317 * and to be called only by dmub_srv_stat_get_notification()
318 */
319 return REG_READ(DMCUB_OUTBOX1_WPTR);
320}
321
322void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
323{
324 /**
325 * outbox1 rptr register is accessed without locks (dal & dc)
326 * and to be called only by dmub_srv_stat_get_notification()
327 */
328 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
329}
330
331void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
332 const struct dmub_region *outbox0)
333{
334 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
335
336 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
337}
338
339uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
340{
341 return REG_READ(DMCUB_OUTBOX0_WPTR);
342}
343
344void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
345{
346 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
347}
348
349bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
350{
351 uint32_t is_hw_init;
352
353 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
354
355 return is_hw_init != 0;
356}
357
358bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
359{
360 uint32_t supported = 0;
361
362 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
363
364 return supported;
365}
366
367void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
368 union dmub_gpint_data_register reg)
369{
370 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
371}
372
373bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
374 union dmub_gpint_data_register reg)
375{
376 union dmub_gpint_data_register test;
377
378 reg.bits.status = 0;
379 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
380
381 return test.all == reg.all;
382}
383
384uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
385{
386 return REG_READ(DMCUB_SCRATCH7);
387}
388
389union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
390{
391 union dmub_fw_boot_status status;
392
393 status.all = REG_READ(DMCUB_SCRATCH0);
394 return status;
395}
396
397void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
398{
399 union dmub_fw_boot_options boot_options = {0};
400
401 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
402}
403
404void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
405{
406 union dmub_fw_boot_options boot_options;
407 boot_options.all = REG_READ(DMCUB_SCRATCH14);
408 boot_options.bits.skip_phy_init_panel_sequence = skip;
409 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
410}
411
412uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
413{
414 return REG_READ(DMCUB_TIMER_CURRENT);
415}
416
417void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)
418{
419 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
420 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
421 struct dmub_timeout_info timeout = {0};
422
423 if (!dmub)
424 return;
425
426 /* timeout data filled externally, cache before resetting memory */
427 timeout = dmub->debug.timeout_info;
428 memset(&dmub->debug, 0, sizeof(dmub->debug));
429 dmub->debug.timeout_info = timeout;
430
431 dmub->debug.dmcub_version = dmub->fw_version;
432
433 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
434 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
435 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
436 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
437 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
438 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
439 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
440 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
441 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
442 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
443 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
444 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
445 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
446 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
447 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
448 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
449
450 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
451 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
452 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
453
454 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
455 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
456 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
457
458 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
459 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
460 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
461
462 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
463 dmub->debug.is_dmcub_enabled = is_dmub_enabled;
464
465 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
466 dmub->debug.is_dmcub_soft_reset = is_soft_reset;
467
468 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
469 dmub->debug.is_dmcub_secure_reset = is_sec_reset;
470
471 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
472 dmub->debug.is_traceport_en = is_traceport_enabled;
473
474 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
475 dmub->debug.is_cw0_enabled = is_cw0_enabled;
476
477 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
478 dmub->debug.is_cw6_enabled = is_cw6_enabled;
479}
480

source code of linux/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c