1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
27#define __DAL_TIMING_GENERATOR_TYPES_H__
28
29#include "hw_shared.h"
30
31struct dc_bios;
32
33/* Contains CRTC vertical/horizontal pixel counters */
34struct crtc_position {
35 int32_t vertical_count;
36 int32_t horizontal_count;
37 int32_t nominal_vcount;
38};
39
40struct dcp_gsl_params {
41 int gsl_group;
42 int gsl_master;
43};
44
45struct gsl_params {
46 int gsl0_en;
47 int gsl1_en;
48 int gsl2_en;
49 int gsl_master_en;
50 int gsl_master_mode;
51 int master_update_lock_gsl_en;
52 int gsl_window_start_x;
53 int gsl_window_end_x;
54 int gsl_window_start_y;
55 int gsl_window_end_y;
56};
57
58/* define the structure of Dynamic Refresh Mode */
59struct drr_params {
60 uint32_t vertical_total_min;
61 uint32_t vertical_total_max;
62 uint32_t vertical_total_mid;
63 uint32_t vertical_total_mid_frame_num;
64 bool immediate_flip;
65};
66
67struct long_vtotal_params {
68 uint32_t vertical_total_min;
69 uint32_t vertical_total_max;
70 uint32_t vertical_blank_start;
71};
72
73#define LEFT_EYE_3D_PRIMARY_SURFACE 1
74#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
75
76enum crtc_state {
77 CRTC_STATE_VBLANK = 0,
78 CRTC_STATE_VACTIVE
79};
80
81struct vupdate_keepout_params {
82 int start_offset;
83 int end_offset;
84 int enable;
85};
86
87struct crtc_stereo_flags {
88 uint8_t PROGRAM_STEREO : 1;
89 uint8_t PROGRAM_POLARITY : 1;
90 uint8_t RIGHT_EYE_POLARITY : 1;
91 uint8_t FRAME_PACKED : 1;
92 uint8_t DISABLE_STEREO_DP_SYNC : 1;
93};
94
95enum crc_selection {
96 /* Order must match values expected by hardware */
97 UNION_WINDOW_A_B = 0,
98 UNION_WINDOW_A_NOT_B,
99 UNION_WINDOW_NOT_A_B,
100 UNION_WINDOW_NOT_A_NOT_B,
101 INTERSECT_WINDOW_A_B,
102 INTERSECT_WINDOW_A_NOT_B,
103 INTERSECT_WINDOW_NOT_A_B,
104 INTERSECT_WINDOW_NOT_A_NOT_B,
105};
106
107enum otg_out_mux_dest {
108 OUT_MUX_DIO = 0,
109 OUT_MUX_HPO_DP = 2,
110};
111
112enum h_timing_div_mode {
113 H_TIMING_NO_DIV,
114 H_TIMING_DIV_BY2,
115 H_TIMING_RESERVED,
116 H_TIMING_DIV_BY4,
117};
118
119enum timing_synchronization_type {
120 NOT_SYNCHRONIZABLE,
121 TIMING_SYNCHRONIZABLE,
122 VBLANK_SYNCHRONIZABLE
123};
124
125struct crc_params {
126 /* Regions used to calculate CRC*/
127 uint16_t windowa_x_start;
128 uint16_t windowa_x_end;
129 uint16_t windowa_y_start;
130 uint16_t windowa_y_end;
131
132 uint16_t windowb_x_start;
133 uint16_t windowb_x_end;
134 uint16_t windowb_y_start;
135 uint16_t windowb_y_end;
136
137 enum crc_selection selection;
138
139 uint8_t dsc_mode;
140 uint8_t odm_mode;
141
142 bool continuous_mode;
143 bool enable;
144
145 uint8_t crc_eng_inst;
146 bool reset;
147};
148
149struct dcn_otg_state {
150 uint32_t v_blank_start;
151 uint32_t v_blank_end;
152 uint32_t v_sync_a_pol;
153 uint32_t v_total;
154 uint32_t v_total_max;
155 uint32_t v_total_min;
156 uint32_t v_total_min_sel;
157 uint32_t v_total_max_sel;
158 uint32_t v_sync_a_start;
159 uint32_t v_sync_a_end;
160 uint32_t h_blank_start;
161 uint32_t h_blank_end;
162 uint32_t h_sync_a_start;
163 uint32_t h_sync_a_end;
164 uint32_t h_sync_a_pol;
165 uint32_t h_total;
166 uint32_t underflow_occurred_status;
167 uint32_t otg_enabled;
168 uint32_t blank_enabled;
169 uint32_t vertical_interrupt1_en;
170 uint32_t vertical_interrupt1_line;
171 uint32_t vertical_interrupt2_en;
172 uint32_t vertical_interrupt2_line;
173 uint32_t vertical_interrupt2_dest;
174 uint32_t otg_master_update_lock;
175 uint32_t otg_double_buffer_control;
176};
177
178struct dcn_optc_reg_state {
179 uint32_t optc_bytes_per_pixel;
180 uint32_t optc_data_format_control;
181 uint32_t optc_data_source_select;
182 uint32_t optc_input_clock_control;
183 uint32_t optc_input_global_control;
184 uint32_t optc_input_spare_register;
185 uint32_t optc_memory_config;
186 uint32_t optc_rsmu_underflow;
187 uint32_t optc_underflow_threshold;
188 uint32_t optc_width_control;
189
190 uint32_t otg_3d_structure_control;
191 uint32_t otg_clock_control;
192 uint32_t otg_control;
193 uint32_t otg_count_control;
194 uint32_t otg_count_reset;
195 uint32_t otg_crc_cntl;
196 uint32_t otg_crc_sig_blue_control_mask;
197 uint32_t otg_crc_sig_red_green_mask;
198 uint32_t otg_crc0_data_b;
199 uint32_t otg_crc0_data_rg;
200 uint32_t otg_crc0_windowa_x_control;
201 uint32_t otg_crc0_windowa_x_control_readback;
202 uint32_t otg_crc0_windowa_y_control;
203 uint32_t otg_crc0_windowa_y_control_readback;
204 uint32_t otg_crc0_windowb_x_control;
205 uint32_t otg_crc0_windowb_x_control_readback;
206 uint32_t otg_crc0_windowb_y_control;
207 uint32_t otg_crc0_windowb_y_control_readback;
208 uint32_t otg_crc1_data_b;
209 uint32_t otg_crc1_data_rg;
210 uint32_t otg_crc1_windowa_x_control;
211 uint32_t otg_crc1_windowa_x_control_readback;
212 uint32_t otg_crc1_windowa_y_control;
213 uint32_t otg_crc1_windowa_y_control_readback;
214 uint32_t otg_crc1_windowb_x_control;
215 uint32_t otg_crc1_windowb_x_control_readback;
216 uint32_t otg_crc1_windowb_y_control;
217 uint32_t otg_crc1_windowb_y_control_readback;
218 uint32_t otg_crc2_data_b;
219 uint32_t otg_crc2_data_rg;
220 uint32_t otg_crc3_data_b;
221 uint32_t otg_crc3_data_rg;
222 uint32_t otg_dlpc_control;
223 uint32_t otg_double_buffer_control;
224 uint32_t otg_drr_control2;
225 uint32_t otg_drr_control;
226 uint32_t otg_drr_timing_int_status;
227 uint32_t otg_drr_trigger_window;
228 uint32_t otg_drr_v_total_change;
229 uint32_t otg_drr_v_total_reach_range;
230 uint32_t otg_dsc_start_position;
231 uint32_t otg_force_count_now_cntl;
232 uint32_t otg_global_control0;
233 uint32_t otg_global_control1;
234 uint32_t otg_global_control2;
235 uint32_t otg_global_control3;
236 uint32_t otg_global_control4;
237 uint32_t otg_global_sync_status;
238 uint32_t otg_gsl_control;
239 uint32_t otg_gsl_vsync_gap;
240 uint32_t otg_gsl_window_x;
241 uint32_t otg_gsl_window_y;
242 uint32_t otg_h_blank_start_end;
243 uint32_t otg_h_sync_a;
244 uint32_t otg_h_sync_a_cntl;
245 uint32_t otg_h_timing_cntl;
246 uint32_t otg_h_total;
247 uint32_t otg_interlace_control;
248 uint32_t otg_interlace_status;
249 uint32_t otg_interrupt_control;
250 uint32_t otg_long_vblank_status;
251 uint32_t otg_m_const_dto0;
252 uint32_t otg_m_const_dto1;
253 uint32_t otg_manual_force_vsync_next_line;
254 uint32_t otg_master_en;
255 uint32_t otg_master_update_lock;
256 uint32_t otg_master_update_mode;
257 uint32_t otg_nom_vert_position;
258 uint32_t otg_pipe_update_status;
259 uint32_t otg_pixel_data_readback0;
260 uint32_t otg_pixel_data_readback1;
261 uint32_t otg_request_control;
262 uint32_t otg_snapshot_control;
263 uint32_t otg_snapshot_frame;
264 uint32_t otg_snapshot_position;
265 uint32_t otg_snapshot_status;
266 uint32_t otg_spare_register;
267 uint32_t otg_static_screen_control;
268 uint32_t otg_status;
269 uint32_t otg_status_frame_count;
270 uint32_t otg_status_hv_count;
271 uint32_t otg_status_position;
272 uint32_t otg_status_vf_count;
273 uint32_t otg_stereo_control;
274 uint32_t otg_stereo_force_next_eye;
275 uint32_t otg_stereo_status;
276 uint32_t otg_trig_manual_control;
277 uint32_t otg_triga_cntl;
278 uint32_t otg_triga_manual_trig;
279 uint32_t otg_trigb_cntl;
280 uint32_t otg_trigb_manual_trig;
281 uint32_t otg_update_lock;
282 uint32_t otg_v_blank_start_end;
283 uint32_t otg_v_count_stop_control;
284 uint32_t otg_v_count_stop_control2;
285 uint32_t otg_v_sync_a;
286 uint32_t otg_v_sync_a_cntl;
287 uint32_t otg_v_total;
288 uint32_t otg_v_total_control;
289 uint32_t otg_v_total_int_status;
290 uint32_t otg_v_total_max;
291 uint32_t otg_v_total_mid;
292 uint32_t otg_v_total_min;
293 uint32_t otg_vert_sync_control;
294 uint32_t otg_vertical_interrupt0_control;
295 uint32_t otg_vertical_interrupt0_position;
296 uint32_t otg_vertical_interrupt1_control;
297 uint32_t otg_vertical_interrupt1_position;
298 uint32_t otg_vertical_interrupt2_control;
299 uint32_t otg_vertical_interrupt2_position;
300 uint32_t otg_vready_param;
301 uint32_t otg_vstartup_param;
302 uint32_t otg_vsync_nom_int_status;
303 uint32_t otg_vupdate_keepout;
304 uint32_t otg_vupdate_param;
305};
306
307/**
308 * struct timing_generator - Entry point to Output Timing Generator feature.
309 */
310struct timing_generator {
311 /**
312 * @funcs: Timing generator control functions
313 */
314 const struct timing_generator_funcs *funcs;
315 struct dc_bios *bp;
316 struct dc_context *ctx;
317 int inst;
318};
319
320struct dc_crtc_timing;
321
322struct drr_params;
323
324/**
325 * struct timing_generator_funcs - Control timing generator on a given device.
326 */
327struct timing_generator_funcs {
328 bool (*validate_timing)(struct timing_generator *tg,
329 const struct dc_crtc_timing *timing);
330 void (*program_timing)(struct timing_generator *tg,
331 const struct dc_crtc_timing *timing,
332 int vready_offset,
333 int vstartup_start,
334 int vupdate_offset,
335 int vupdate_width,
336 int pstate_keepout,
337 const enum signal_type signal,
338 bool use_vbios
339 );
340 void (*setup_vertical_interrupt0)(
341 struct timing_generator *optc,
342 uint32_t start_line,
343 uint32_t end_line);
344 void (*setup_vertical_interrupt1)(
345 struct timing_generator *optc,
346 uint32_t start_line);
347 void (*setup_vertical_interrupt2)(
348 struct timing_generator *optc,
349 uint32_t start_line);
350
351 bool (*enable_crtc)(struct timing_generator *tg);
352 bool (*disable_crtc)(struct timing_generator *tg);
353 void (*phantom_crtc_post_enable)(struct timing_generator *tg);
354 void (*disable_phantom_crtc)(struct timing_generator *tg);
355 bool (*immediate_disable_crtc)(struct timing_generator *tg);
356 bool (*is_counter_moving)(struct timing_generator *tg);
357 void (*get_position)(struct timing_generator *tg,
358 struct crtc_position *position);
359
360 uint32_t (*get_frame_count)(struct timing_generator *tg);
361 void (*get_scanoutpos)(
362 struct timing_generator *tg,
363 uint32_t *v_blank_start,
364 uint32_t *v_blank_end,
365 uint32_t *h_position,
366 uint32_t *v_position);
367 bool (*get_otg_active_size)(struct timing_generator *optc,
368 uint32_t *otg_active_width,
369 uint32_t *otg_active_height);
370 bool (*is_matching_timing)(struct timing_generator *tg,
371 const struct dc_crtc_timing *otg_timing);
372 void (*set_early_control)(struct timing_generator *tg,
373 uint32_t early_cntl);
374 void (*wait_for_state)(struct timing_generator *tg,
375 enum crtc_state state);
376 void (*set_blank)(struct timing_generator *tg,
377 bool enable_blanking);
378 bool (*is_blanked)(struct timing_generator *tg);
379 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
380 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
381 void (*set_colors)(struct timing_generator *tg,
382 const struct tg_color *blank_color,
383 const struct tg_color *overscan_color);
384
385 void (*disable_vga)(struct timing_generator *tg);
386 bool (*did_triggered_reset_occur)(struct timing_generator *tg);
387 void (*setup_global_swap_lock)(struct timing_generator *tg,
388 const struct dcp_gsl_params *gsl_params);
389 void (*unlock)(struct timing_generator *tg);
390 void (*lock)(struct timing_generator *tg);
391 void (*lock_doublebuffer_disable)(struct timing_generator *tg);
392 void (*lock_doublebuffer_enable)(struct timing_generator *tg);
393 void(*triplebuffer_unlock)(struct timing_generator *tg);
394 void(*triplebuffer_lock)(struct timing_generator *tg);
395 void (*enable_reset_trigger)(struct timing_generator *tg,
396 int source_tg_inst);
397 void (*enable_crtc_reset)(struct timing_generator *tg,
398 int source_tg_inst,
399 struct crtc_trigger_info *crtc_tp);
400 void (*disable_reset_trigger)(struct timing_generator *tg);
401 void (*tear_down_global_swap_lock)(struct timing_generator *tg);
402 void (*enable_advanced_request)(struct timing_generator *tg,
403 bool enable, const struct dc_crtc_timing *timing);
404 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
405 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
406 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
407 void (*set_static_screen_control)(struct timing_generator *tg,
408 uint32_t event_triggers,
409 uint32_t num_frames);
410 void (*set_test_pattern)(
411 struct timing_generator *tg,
412 enum controller_dp_test_pattern test_pattern,
413 enum dc_color_depth color_depth);
414
415 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
416
417 void (*program_global_sync)(struct timing_generator *tg,
418 int vready_offset,
419 int vstartup_start,
420 int vupdate_offset,
421 int vupdate_width,
422 int pstate_keepout);
423 void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
424 void (*program_stereo)(struct timing_generator *tg,
425 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
426 bool (*is_stereo_left_eye)(struct timing_generator *tg);
427
428 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
429
430 void (*tg_init)(struct timing_generator *tg);
431 bool (*is_tg_enabled)(struct timing_generator *tg);
432 bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
433 void (*clear_optc_underflow)(struct timing_generator *tg);
434
435 void (*set_dwb_source)(struct timing_generator *optc,
436 uint32_t dwb_pipe_inst);
437
438 void (*get_optc_source)(struct timing_generator *optc,
439 uint32_t *num_of_input_segments,
440 uint32_t *seg0_src_sel,
441 uint32_t *seg1_src_sel);
442 bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);
443
444 /**
445 * Configure CRCs for the given timing generator. Return false if TG is
446 * not on.
447 */
448 bool (*configure_crc)(struct timing_generator *tg,
449 const struct crc_params *params);
450
451 /**
452 * @get_crc: Get CRCs for the given timing generator. Return false if
453 * CRCs are not enabled (via configure_crc).
454 */
455 bool (*get_crc)(struct timing_generator *tg, uint8_t idx,
456 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
457
458 void (*program_manual_trigger)(struct timing_generator *optc);
459 void (*setup_manual_trigger)(struct timing_generator *optc);
460 bool (*get_hw_timing)(struct timing_generator *optc,
461 struct dc_crtc_timing *hw_crtc_timing);
462
463 void (*set_vtg_params)(struct timing_generator *optc,
464 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
465
466 void (*set_dsc_config)(struct timing_generator *optc,
467 enum optc_dsc_mode dsc_mode,
468 uint32_t dsc_bytes_per_pixel,
469 uint32_t dsc_slice_width);
470 void (*get_dsc_status)(struct timing_generator *optc,
471 uint32_t *dsc_mode);
472 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
473
474 /**
475 * @set_odm_combine: Set up the ODM block to read from the correct
476 * OPP(s) and turn on/off ODM memory.
477 */
478 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
479 int segment_width, int last_segment_width);
480 void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);
481 void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
482 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
483 void (*set_gsl_source_select)(struct timing_generator *optc,
484 int group_idx,
485 uint32_t gsl_ready_signal);
486 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
487 void (*set_drr_trigger_window)(struct timing_generator *optc,
488 uint32_t window_start, uint32_t window_end);
489 void (*set_vtotal_change_limit)(struct timing_generator *optc,
490 uint32_t limit);
491 void (*align_vblanks)(struct timing_generator *master_optc,
492 struct timing_generator *slave_optc,
493 uint32_t master_pixel_clock_100Hz,
494 uint32_t slave_pixel_clock_100Hz,
495 uint8_t master_clock_divider,
496 uint8_t slave_clock_divider);
497 bool (*validate_vmin_vmax)(struct timing_generator *optc,
498 int vmin, int vmax);
499 bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
500 uint32_t vtotal_change_limit);
501
502 void (*init_odm)(struct timing_generator *tg);
503 void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);
504 void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params);
505 void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg);
506 void (*wait_otg_disable)(struct timing_generator *optc);
507 bool (*get_optc_double_buffer_pending)(struct timing_generator *tg);
508 bool (*get_otg_double_buffer_pending)(struct timing_generator *tg);
509 bool (*get_pipe_update_pending)(struct timing_generator *tg);
510 void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);
511 bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
512 void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s);
513 void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state);
514};
515
516#endif
517

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h