1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_AUX_ENGINE_H__
27#define __DAL_AUX_ENGINE_H__
28
29#include "dc_ddc_types.h"
30
31enum aux_return_code_type;
32
33enum i2caux_transaction_operation {
34 I2CAUX_TRANSACTION_READ,
35 I2CAUX_TRANSACTION_WRITE
36};
37
38enum i2caux_transaction_address_space {
39 I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
40 I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
41};
42
43struct i2caux_transaction_payload {
44 enum i2caux_transaction_address_space address_space;
45 uint32_t address;
46 uint32_t length;
47 uint8_t *data;
48};
49
50enum i2caux_transaction_status {
51 I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
52 I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
53 I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
54 I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
55 I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
56 I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
57 I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
58 I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
59 I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
60 I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
61 I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
62};
63
64struct i2caux_transaction_request {
65 enum i2caux_transaction_operation operation;
66 struct i2caux_transaction_payload payload;
67 enum i2caux_transaction_status status;
68};
69
70enum i2caux_engine_type {
71 I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
72 I2CAUX_ENGINE_TYPE_AUX,
73 I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
74 I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
75 I2CAUX_ENGINE_TYPE_I2C_SW
76};
77
78enum i2c_default_speed {
79 I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
80 I2CAUX_DEFAULT_I2C_SW_SPEED = 50
81};
82
83union aux_config {
84 struct {
85 uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;
86 } bits;
87 uint32_t raw;
88};
89
90struct aux_engine {
91 uint32_t inst;
92 struct ddc *ddc;
93 struct dc_context *ctx;
94 const struct aux_engine_funcs *funcs;
95 /* following values are expressed in milliseconds */
96 uint32_t delay;
97 uint32_t max_defer_write_retry;
98 bool acquire_reset;
99};
100
101struct read_command_context {
102 uint8_t *buffer;
103 uint32_t current_read_length;
104 uint32_t offset;
105 enum i2caux_transaction_status status;
106
107 struct aux_request_transaction_data request;
108 struct aux_reply_transaction_data reply;
109
110 uint8_t returned_byte;
111
112 uint32_t timed_out_retry_aux;
113 uint32_t invalid_reply_retry_aux;
114 uint32_t defer_retry_aux;
115 uint32_t defer_retry_i2c;
116 uint32_t invalid_reply_retry_aux_on_ack;
117
118 bool transaction_complete;
119 bool operation_succeeded;
120};
121
122struct write_command_context {
123 bool mot;
124
125 uint8_t *buffer;
126 uint32_t current_write_length;
127 enum i2caux_transaction_status status;
128
129 struct aux_request_transaction_data request;
130 struct aux_reply_transaction_data reply;
131
132 uint8_t returned_byte;
133
134 uint32_t timed_out_retry_aux;
135 uint32_t invalid_reply_retry_aux;
136 uint32_t defer_retry_aux;
137 uint32_t defer_retry_i2c;
138 uint32_t max_defer_retry;
139 uint32_t ack_m_retry;
140
141 uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
142
143 bool transaction_complete;
144 bool operation_succeeded;
145};
146
147
148struct aux_engine_funcs {
149 bool (*configure_timeout)(
150 struct ddc_service *ddc,
151 uint32_t timeout);
152 void (*destroy)(
153 struct aux_engine **ptr);
154 bool (*acquire_engine)(
155 struct aux_engine *engine);
156 void (*configure)(
157 struct aux_engine *engine,
158 union aux_config cfg);
159 void (*submit_channel_request)(
160 struct aux_engine *engine,
161 struct aux_request_transaction_data *request);
162 void (*process_channel_reply)(
163 struct aux_engine *engine,
164 struct aux_reply_transaction_data *reply);
165 int (*read_channel_reply)(
166 struct aux_engine *engine,
167 uint32_t size,
168 uint8_t *buffer,
169 uint8_t *reply_result,
170 uint32_t *sw_status);
171 enum aux_return_code_type (*get_channel_status)(
172 struct aux_engine *engine,
173 uint8_t *returned_bytes);
174 bool (*is_engine_available)(struct aux_engine *engine);
175 bool (*acquire)(
176 struct aux_engine *engine,
177 struct ddc *ddc);
178 bool (*submit_request)(
179 struct aux_engine *engine,
180 struct i2caux_transaction_request *request,
181 bool middle_of_transaction);
182 void (*release_engine)(
183 struct aux_engine *engine);
184 void (*destroy_engine)(
185 struct aux_engine **engine);
186};
187#endif
188

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h