1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DISPLAY_MODE_CORE_H__
27#define __DISPLAY_MODE_CORE_H__
28
29#include "display_mode_core_structs.h"
30
31struct display_mode_lib_st;
32
33dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib);
34void dml_core_mode_support_partial(struct display_mode_lib_st *mode_lib);
35void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struct dml_clk_cfg_st *clk_cfg);
36
37void dml_core_get_row_heights(
38 dml_uint_t *dpte_row_height,
39 dml_uint_t *meta_row_height,
40 const struct display_mode_lib_st *mode_lib,
41 dml_bool_t is_plane1,
42 enum dml_source_format_class SourcePixelFormat,
43 enum dml_swizzle_mode SurfaceTiling,
44 enum dml_rotation_angle ScanDirection,
45 dml_uint_t pitch,
46 dml_uint_t GPUVMMinPageSizeKBytes);
47
48dml_float_t dml_get_return_bw_mbps_vm_only(
49 const struct soc_bounding_box_st *soc,
50 dml_bool_t use_ideal_dram_bw_strobe,
51 dml_bool_t HostVMEnable,
52 dml_float_t DCFCLK,
53 dml_float_t FabricClock,
54 dml_float_t DRAMSpeed);
55
56dml_float_t dml_get_return_bw_mbps(
57 const struct soc_bounding_box_st *soc,
58 dml_bool_t use_ideal_dram_bw_strobe,
59 dml_bool_t HostVMEnable,
60 dml_float_t DCFCLK,
61 dml_float_t FabricClock,
62 dml_float_t DRAMSpeed);
63
64dml_bool_t dml_mode_support(
65 struct display_mode_lib_st *mode_lib,
66 dml_uint_t state_idx,
67 const struct dml_display_cfg_st *display_cfg);
68
69dml_bool_t dml_mode_programming(
70 struct display_mode_lib_st *mode_lib,
71 dml_uint_t state_idx,
72 const struct dml_display_cfg_st *display_cfg,
73 bool call_standalone);
74
75dml_uint_t dml_mode_support_ex(
76 struct dml_mode_support_ex_params_st *in_out_params);
77
78dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx);
79
80#define dml_get_per_surface_var_decl(variable, type) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx)
81#define dml_get_var_decl(var, type) type dml_get_##var(struct display_mode_lib_st *mode_lib)
82
83dml_get_var_decl(wm_urgent, dml_float_t);
84dml_get_var_decl(wm_stutter_exit, dml_float_t);
85dml_get_var_decl(wm_stutter_enter_exit, dml_float_t);
86dml_get_var_decl(wm_memory_trip, dml_float_t);
87dml_get_var_decl(wm_dram_clock_change, dml_float_t);
88dml_get_var_decl(wm_z8_stutter_enter_exit, dml_float_t);
89dml_get_var_decl(wm_z8_stutter, dml_float_t);
90dml_get_var_decl(urgent_latency, dml_float_t);
91dml_get_var_decl(clk_dcf_deepsleep, dml_float_t);
92dml_get_var_decl(wm_fclk_change, dml_float_t);
93dml_get_var_decl(wm_usr_retraining, dml_float_t);
94dml_get_var_decl(urgent_latency, dml_float_t);
95
96dml_get_var_decl(wm_writeback_dram_clock_change, dml_float_t);
97dml_get_var_decl(wm_writeback_urgent, dml_float_t);
98dml_get_var_decl(stutter_efficiency_no_vblank, dml_float_t);
99dml_get_var_decl(stutter_efficiency, dml_float_t);
100dml_get_var_decl(stutter_efficiency_z8, dml_float_t);
101dml_get_var_decl(stutter_num_bursts_z8, dml_float_t);
102dml_get_var_decl(stutter_period, dml_float_t);
103dml_get_var_decl(stutter_efficiency_z8_bestcase, dml_float_t);
104dml_get_var_decl(stutter_num_bursts_z8_bestcase, dml_float_t);
105dml_get_var_decl(stutter_period_bestcase, dml_float_t);
106dml_get_var_decl(urgent_latency, dml_float_t);
107dml_get_var_decl(urgent_extra_latency, dml_float_t);
108dml_get_var_decl(fclk_change_latency, dml_float_t);
109dml_get_var_decl(nonurgent_latency, dml_float_t);
110dml_get_var_decl(dispclk_calculated, dml_float_t);
111dml_get_var_decl(total_data_read_bw, dml_float_t);
112dml_get_var_decl(return_bw, dml_float_t);
113dml_get_var_decl(return_dram_bw, dml_float_t);
114dml_get_var_decl(tcalc, dml_float_t);
115dml_get_var_decl(fraction_of_urgent_bandwidth, dml_float_t);
116dml_get_var_decl(fraction_of_urgent_bandwidth_imm_flip, dml_float_t);
117dml_get_var_decl(comp_buffer_size_kbytes, dml_uint_t);
118dml_get_var_decl(pixel_chunk_size_in_kbyte, dml_uint_t);
119dml_get_var_decl(alpha_pixel_chunk_size_in_kbyte, dml_uint_t);
120dml_get_var_decl(meta_chunk_size_in_kbyte, dml_uint_t);
121dml_get_var_decl(min_pixel_chunk_size_in_byte, dml_uint_t);
122dml_get_var_decl(min_meta_chunk_size_in_byte, dml_uint_t);
123dml_get_var_decl(total_immediate_flip_bytes, dml_uint_t);
124
125dml_get_per_surface_var_decl(dsc_delay, dml_uint_t);
126dml_get_per_surface_var_decl(dppclk_calculated, dml_float_t);
127dml_get_per_surface_var_decl(dscclk_calculated, dml_float_t);
128dml_get_per_surface_var_decl(min_ttu_vblank_in_us, dml_float_t);
129dml_get_per_surface_var_decl(vratio_prefetch_l, dml_float_t);
130dml_get_per_surface_var_decl(vratio_prefetch_c, dml_float_t);
131dml_get_per_surface_var_decl(dst_x_after_scaler, dml_uint_t);
132dml_get_per_surface_var_decl(dst_y_after_scaler, dml_uint_t);
133dml_get_per_surface_var_decl(dst_y_per_vm_vblank, dml_float_t);
134dml_get_per_surface_var_decl(dst_y_per_row_vblank, dml_float_t);
135dml_get_per_surface_var_decl(dst_y_prefetch, dml_float_t);
136dml_get_per_surface_var_decl(dst_y_per_vm_flip, dml_float_t);
137dml_get_per_surface_var_decl(dst_y_per_row_flip, dml_float_t);
138dml_get_per_surface_var_decl(dst_y_per_pte_row_nom_l, dml_float_t);
139dml_get_per_surface_var_decl(dst_y_per_pte_row_nom_c, dml_float_t);
140dml_get_per_surface_var_decl(dst_y_per_meta_row_nom_l, dml_float_t);
141dml_get_per_surface_var_decl(dst_y_per_meta_row_nom_c, dml_float_t);
142dml_get_per_surface_var_decl(refcyc_per_vm_group_vblank_in_us, dml_float_t);
143dml_get_per_surface_var_decl(refcyc_per_vm_group_flip_in_us, dml_float_t);
144dml_get_per_surface_var_decl(refcyc_per_vm_req_vblank_in_us, dml_float_t);
145dml_get_per_surface_var_decl(refcyc_per_vm_req_flip_in_us, dml_float_t);
146dml_get_per_surface_var_decl(refcyc_per_vm_dmdata_in_us, dml_float_t);
147dml_get_per_surface_var_decl(dmdata_dl_delta_in_us, dml_float_t);
148dml_get_per_surface_var_decl(refcyc_per_line_delivery_l_in_us, dml_float_t);
149dml_get_per_surface_var_decl(refcyc_per_line_delivery_c_in_us, dml_float_t);
150dml_get_per_surface_var_decl(refcyc_per_line_delivery_pre_l_in_us, dml_float_t);
151dml_get_per_surface_var_decl(refcyc_per_line_delivery_pre_c_in_us, dml_float_t);
152dml_get_per_surface_var_decl(refcyc_per_req_delivery_l_in_us, dml_float_t);
153dml_get_per_surface_var_decl(refcyc_per_req_delivery_c_in_us, dml_float_t);
154dml_get_per_surface_var_decl(refcyc_per_req_delivery_pre_l_in_us, dml_float_t);
155dml_get_per_surface_var_decl(refcyc_per_req_delivery_pre_c_in_us, dml_float_t);
156dml_get_per_surface_var_decl(refcyc_per_cursor_req_delivery_in_us, dml_float_t);
157dml_get_per_surface_var_decl(refcyc_per_cursor_req_delivery_pre_in_us, dml_float_t);
158dml_get_per_surface_var_decl(refcyc_per_meta_chunk_nom_l_in_us, dml_float_t);
159dml_get_per_surface_var_decl(refcyc_per_meta_chunk_nom_c_in_us, dml_float_t);
160dml_get_per_surface_var_decl(refcyc_per_meta_chunk_vblank_l_in_us, dml_float_t);
161dml_get_per_surface_var_decl(refcyc_per_meta_chunk_vblank_c_in_us, dml_float_t);
162dml_get_per_surface_var_decl(refcyc_per_meta_chunk_flip_l_in_us, dml_float_t);
163dml_get_per_surface_var_decl(refcyc_per_meta_chunk_flip_c_in_us, dml_float_t);
164dml_get_per_surface_var_decl(refcyc_per_pte_group_nom_l_in_us, dml_float_t);
165dml_get_per_surface_var_decl(refcyc_per_pte_group_nom_c_in_us, dml_float_t);
166dml_get_per_surface_var_decl(refcyc_per_pte_group_vblank_l_in_us, dml_float_t);
167dml_get_per_surface_var_decl(refcyc_per_pte_group_vblank_c_in_us, dml_float_t);
168dml_get_per_surface_var_decl(refcyc_per_pte_group_flip_l_in_us, dml_float_t);
169dml_get_per_surface_var_decl(refcyc_per_pte_group_flip_c_in_us, dml_float_t);
170
171dml_get_per_surface_var_decl(dpte_group_size_in_bytes, dml_uint_t);
172dml_get_per_surface_var_decl(vm_group_size_in_bytes, dml_uint_t);
173dml_get_per_surface_var_decl(swath_height_l, dml_uint_t);
174dml_get_per_surface_var_decl(swath_height_c, dml_uint_t);
175dml_get_per_surface_var_decl(dpte_row_height_l, dml_uint_t);
176dml_get_per_surface_var_decl(dpte_row_height_c, dml_uint_t);
177dml_get_per_surface_var_decl(dpte_row_height_linear_l, dml_uint_t);
178dml_get_per_surface_var_decl(dpte_row_height_linear_c, dml_uint_t);
179dml_get_per_surface_var_decl(meta_row_height_l, dml_uint_t);
180dml_get_per_surface_var_decl(meta_row_height_c, dml_uint_t);
181dml_get_per_surface_var_decl(vstartup_calculated, dml_uint_t);
182dml_get_per_surface_var_decl(vupdate_offset, dml_uint_t);
183dml_get_per_surface_var_decl(vupdate_width, dml_uint_t);
184dml_get_per_surface_var_decl(vready_offset, dml_uint_t);
185dml_get_per_surface_var_decl(vready_at_or_after_vsync, dml_uint_t);
186dml_get_per_surface_var_decl(min_dst_y_next_start, dml_uint_t);
187dml_get_per_surface_var_decl(det_stored_buffer_size_l_bytes, dml_uint_t);
188dml_get_per_surface_var_decl(det_stored_buffer_size_c_bytes, dml_uint_t);
189dml_get_per_surface_var_decl(use_mall_for_static_screen, dml_uint_t);
190dml_get_per_surface_var_decl(surface_size_for_mall, dml_uint_t);
191dml_get_per_surface_var_decl(dcc_max_uncompressed_block_l, dml_uint_t);
192dml_get_per_surface_var_decl(dcc_max_uncompressed_block_c, dml_uint_t);
193dml_get_per_surface_var_decl(dcc_max_compressed_block_l, dml_uint_t);
194dml_get_per_surface_var_decl(dcc_max_compressed_block_c, dml_uint_t);
195dml_get_per_surface_var_decl(dcc_independent_block_l, dml_uint_t);
196dml_get_per_surface_var_decl(dcc_independent_block_c, dml_uint_t);
197dml_get_per_surface_var_decl(max_active_dram_clock_change_latency_supported, dml_uint_t);
198dml_get_per_surface_var_decl(pte_buffer_mode, dml_uint_t);
199dml_get_per_surface_var_decl(bigk_fragment_size, dml_uint_t);
200dml_get_per_surface_var_decl(dpte_bytes_per_row, dml_uint_t);
201dml_get_per_surface_var_decl(meta_bytes_per_row, dml_uint_t);
202dml_get_per_surface_var_decl(det_buffer_size_kbytes, dml_uint_t);
203
204#endif
205

source code of linux/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h