1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_LINK_ENCODER__DCE110_H__
27#define __DC_LINK_ENCODER__DCE110_H__
28
29#include "link_encoder.h"
30
31#define TO_DCE110_LINK_ENC(link_encoder)\
32 container_of(link_encoder, struct dce110_link_encoder, base)
33
34/* Not found regs in dce120 spec
35 * BIOS_SCRATCH_2
36 * DP_DPHY_INTERNAL_CTRL
37 */
38
39#define AUX_REG_LIST(id)\
40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
43
44#define HPD_REG_LIST(id)\
45 SRI(DC_HPD_CONTROL, HPD, id)
46
47#define LE_COMMON_REG_LIST_BASE(id) \
48 SR(DMCU_RAM_ACCESS_CTRL), \
49 SR(DMCU_IRAM_RD_CTRL), \
50 SR(DMCU_IRAM_RD_DATA), \
51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
63 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
64 SRI(DP_MSE_SAT0, DP, id), \
65 SRI(DP_MSE_SAT1, DP, id), \
66 SRI(DP_MSE_SAT2, DP, id), \
67 SRI(DP_MSE_SAT_UPDATE, DP, id), \
68 SRI(DP_SEC_CNTL, DP, id), \
69 SRI(DP_VID_STREAM_CNTL, DP, id), \
70 SRI(DP_DPHY_FAST_TRAINING, DP, id), \
71 SRI(DP_SEC_CNTL1, DP, id)
72
73#define LE_COMMON_REG_LIST(id)\
74 LE_COMMON_REG_LIST_BASE(id), \
75 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
76 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
77 SR(DCI_MEM_PWR_STATUS)
78
79#if defined(CONFIG_DRM_AMD_DC_SI)
80#define LE_DCE60_REG_LIST(id)\
81 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
82 SR(DMCU_RAM_ACCESS_CTRL), \
83 SR(DMCU_IRAM_RD_CTRL), \
84 SR(DMCU_IRAM_RD_DATA), \
85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
86 SRI(DIG_BE_CNTL, DIG, id), \
87 SRI(DIG_BE_EN_CNTL, DIG, id), \
88 SRI(DP_CONFIG, DP, id), \
89 SRI(DP_DPHY_CNTL, DP, id), \
90 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
91 SRI(DP_DPHY_SYM0, DP, id), \
92 SRI(DP_DPHY_SYM1, DP, id), \
93 SRI(DP_DPHY_SYM2, DP, id), \
94 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
95 SRI(DP_LINK_CNTL, DP, id), \
96 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
97 SRI(DP_MSE_SAT0, DP, id), \
98 SRI(DP_MSE_SAT1, DP, id), \
99 SRI(DP_MSE_SAT2, DP, id), \
100 SRI(DP_MSE_SAT_UPDATE, DP, id), \
101 SRI(DP_SEC_CNTL, DP, id), \
102 SRI(DP_VID_STREAM_CNTL, DP, id), \
103 SRI(DP_DPHY_FAST_TRAINING, DP, id), \
104 SRI(DP_SEC_CNTL1, DP, id), \
105 SR(DAC_ENABLE)
106#endif
107
108#define LE_DCE80_REG_LIST(id)\
109 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
110 LE_COMMON_REG_LIST_BASE(id), \
111 SR(DAC_ENABLE)
112
113#define LE_DCE100_REG_LIST(id)\
114 LE_COMMON_REG_LIST_BASE(id), \
115 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
116 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
117 SR(DCI_MEM_PWR_STATUS), \
118 SR(DAC_ENABLE)
119
120#define LE_DCE110_REG_LIST(id)\
121 LE_COMMON_REG_LIST_BASE(id), \
122 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
123 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
124 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
125 SR(DCI_MEM_PWR_STATUS)
126
127#define LE_DCE120_REG_LIST(id)\
128 LE_COMMON_REG_LIST_BASE(id), \
129 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
130 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
131 SR(DCI_MEM_PWR_STATUS)
132
133#define LE_DCN10_REG_LIST(id)\
134 LE_COMMON_REG_LIST_BASE(id), \
135 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
136 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
137 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
138
139struct dce110_link_enc_aux_registers {
140 uint32_t AUX_CONTROL;
141 uint32_t AUX_DPHY_RX_CONTROL0;
142 uint32_t AUX_DPHY_RX_CONTROL1;
143};
144
145struct dce110_link_enc_hpd_registers {
146 uint32_t DC_HPD_CONTROL;
147};
148
149struct dce110_link_enc_registers {
150 /* DMCU registers */
151 uint32_t MASTER_COMM_DATA_REG1;
152 uint32_t MASTER_COMM_DATA_REG2;
153 uint32_t MASTER_COMM_DATA_REG3;
154 uint32_t MASTER_COMM_CMD_REG;
155 uint32_t MASTER_COMM_CNTL_REG;
156 uint32_t DMCU_RAM_ACCESS_CTRL;
157 uint32_t DCI_MEM_PWR_STATUS;
158 uint32_t DMU_MEM_PWR_CNTL;
159 uint32_t DMCU_IRAM_RD_CTRL;
160 uint32_t DMCU_IRAM_RD_DATA;
161 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
162
163 /* Common DP registers */
164 uint32_t DIG_BE_CNTL;
165 uint32_t DIG_BE_EN_CNTL;
166 uint32_t DP_CONFIG;
167 uint32_t DP_DPHY_CNTL;
168 uint32_t DP_DPHY_INTERNAL_CTRL;
169 uint32_t DP_DPHY_PRBS_CNTL;
170 uint32_t DP_DPHY_SCRAM_CNTL;
171 uint32_t DP_DPHY_SYM0;
172 uint32_t DP_DPHY_SYM1;
173 uint32_t DP_DPHY_SYM2;
174 uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
175 uint32_t DP_LINK_CNTL;
176 uint32_t DP_LINK_FRAMING_CNTL;
177 uint32_t DP_MSE_SAT0;
178 uint32_t DP_MSE_SAT1;
179 uint32_t DP_MSE_SAT2;
180 uint32_t DP_MSE_SAT_UPDATE;
181 uint32_t DP_SEC_CNTL;
182 uint32_t DP_VID_STREAM_CNTL;
183 uint32_t DP_DPHY_FAST_TRAINING;
184 uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
185 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
186 uint32_t DP_SEC_CNTL1;
187
188 /* DAC registers */
189 uint32_t DAC_ENABLE;
190};
191
192struct dce110_link_encoder {
193 struct link_encoder base;
194 const struct dce110_link_enc_registers *link_regs;
195 const struct dce110_link_enc_aux_registers *aux_regs;
196 const struct dce110_link_enc_hpd_registers *hpd_regs;
197};
198
199
200void dce110_link_encoder_construct(
201 struct dce110_link_encoder *enc110,
202 const struct encoder_init_data *init_data,
203 const struct encoder_feature_support *enc_features,
204 const struct dce110_link_enc_registers *link_regs,
205 const struct dce110_link_enc_aux_registers *aux_regs,
206 const struct dce110_link_enc_hpd_registers *hpd_regs);
207
208#if defined(CONFIG_DRM_AMD_DC_SI)
209void dce60_link_encoder_construct(
210 struct dce110_link_encoder *enc110,
211 const struct encoder_init_data *init_data,
212 const struct encoder_feature_support *enc_features,
213 const struct dce110_link_enc_registers *link_regs,
214 const struct dce110_link_enc_aux_registers *aux_regs,
215 const struct dce110_link_enc_hpd_registers *hpd_regs);
216#endif
217
218bool dce110_link_encoder_validate_dvi_output(
219 const struct dce110_link_encoder *enc110,
220 enum signal_type connector_signal,
221 enum signal_type signal,
222 const struct dc_crtc_timing *crtc_timing);
223
224bool dce110_link_encoder_validate_dp_output(
225 const struct dce110_link_encoder *enc110,
226 const struct dc_crtc_timing *crtc_timing);
227
228bool dce110_link_encoder_validate_wireless_output(
229 const struct dce110_link_encoder *enc110,
230 const struct dc_crtc_timing *crtc_timing);
231
232bool dce110_link_encoder_validate_output_with_stream(
233 struct link_encoder *enc,
234 const struct dc_stream_state *stream);
235
236/****************** HW programming ************************/
237
238/* initialize HW */ /* why do we initialze aux in here? */
239void dce110_link_encoder_hw_init(struct link_encoder *enc);
240
241void dce110_link_encoder_destroy(struct link_encoder **enc);
242
243/* program DIG_MODE in DIG_BE */
244/* TODO can this be combined with enable_output? */
245void dce110_link_encoder_setup(
246 struct link_encoder *enc,
247 enum signal_type signal);
248
249/* enables TMDS PHY output */
250/* TODO: still need depth or just pass in adjusted pixel clock? */
251void dce110_link_encoder_enable_tmds_output(
252 struct link_encoder *enc,
253 enum clock_source_id clock_source,
254 enum dc_color_depth color_depth,
255 enum signal_type signal,
256 uint32_t pixel_clock);
257
258/* enables DP PHY output */
259void dce110_link_encoder_enable_dp_output(
260 struct link_encoder *enc,
261 const struct dc_link_settings *link_settings,
262 enum clock_source_id clock_source);
263
264/* enables DP PHY output in MST mode */
265void dce110_link_encoder_enable_dp_mst_output(
266 struct link_encoder *enc,
267 const struct dc_link_settings *link_settings,
268 enum clock_source_id clock_source);
269
270/* enables LVDS PHY output */
271void dce110_link_encoder_enable_lvds_output(
272 struct link_encoder *enc,
273 enum clock_source_id clock_source,
274 uint32_t pixel_clock);
275
276/* disable PHY output */
277void dce110_link_encoder_disable_output(
278 struct link_encoder *enc,
279 enum signal_type signal);
280
281/* set DP lane settings */
282void dce110_link_encoder_dp_set_lane_settings(
283 struct link_encoder *enc,
284 const struct dc_link_settings *link_settings,
285 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
286
287void dce110_link_encoder_dp_set_phy_pattern(
288 struct link_encoder *enc,
289 const struct encoder_set_dp_phy_pattern_param *param);
290
291/* programs DP MST VC payload allocation */
292void dce110_link_encoder_update_mst_stream_allocation_table(
293 struct link_encoder *enc,
294 const struct link_mst_stream_allocation_table *table);
295
296void dce110_link_encoder_connect_dig_be_to_fe(
297 struct link_encoder *enc,
298 enum engine_id engine,
299 bool connect);
300
301unsigned int dce110_get_dig_frontend(struct link_encoder *enc);
302
303void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
304 struct link_encoder *enc,
305 uint32_t index);
306
307void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
308
309void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
310
311void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
312 bool exit_link_training_required);
313
314void dce110_psr_program_secondary_packet(struct link_encoder *enc,
315 unsigned int sdp_transmit_line_num_deadline);
316
317bool dce110_is_dig_enabled(struct link_encoder *enc);
318
319void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
320 struct dc_link_settings *link_settings);
321
322#endif /* __DC_LINK_ENCODER__DCE110_H__ */
323

source code of linux/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h