1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef _DCE_ABM_H_
28#define _DCE_ABM_H_
29
30#include "abm.h"
31
32#define ABM_COMMON_REG_LIST_DCE_BASE() \
33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
36
37#define ABM_DCE110_COMMON_REG_LIST() \
38 ABM_COMMON_REG_LIST_DCE_BASE(), \
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
46 SR(BL1_PWM_USER_LEVEL), \
47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
49 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
50 SR(DC_ABM1_ACE_THRES_12), \
51 SR(BIOS_SCRATCH_2)
52
53#define ABM_DCN10_REG_LIST(id)\
54 ABM_COMMON_REG_LIST_DCE_BASE(), \
55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
65 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
66 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
67 NBIO_SR(BIOS_SCRATCH_2)
68
69#define ABM_DCN20_REG_LIST() \
70 ABM_COMMON_REG_LIST_DCE_BASE(), \
71 SR(DC_ABM1_HG_SAMPLE_RATE), \
72 SR(DC_ABM1_LS_SAMPLE_RATE), \
73 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
74 SR(DC_ABM1_HG_MISC_CTRL), \
75 SR(DC_ABM1_IPCSC_COEFF_SEL), \
76 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
77 SR(BL1_PWM_TARGET_ABM_LEVEL), \
78 SR(BL1_PWM_USER_LEVEL), \
79 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
80 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
81 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
82 SR(DC_ABM1_ACE_THRES_12), \
83 NBIO_SR(BIOS_SCRATCH_2)
84
85#define ABM_DCN301_REG_LIST(id)\
86 ABM_COMMON_REG_LIST_DCE_BASE(), \
87 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
88 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
89 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
90 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
91 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
92 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
93 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
94 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
95 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
96 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
97 NBIO_SR(BIOS_SCRATCH_2)
98
99#define ABM_DCN302_REG_LIST(id)\
100 ABM_COMMON_REG_LIST_DCE_BASE(), \
101 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
102 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
103 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
104 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
105 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
106 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
107 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
108 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
109 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
110 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
111 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
112 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
113 NBIO_SR(BIOS_SCRATCH_2)
114
115#define ABM_DCN30_REG_LIST(id)\
116 ABM_COMMON_REG_LIST_DCE_BASE(), \
117 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
118 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
119 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
120 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
121 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
122 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
123 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
124 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
125 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
126 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
127 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
128 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
129 NBIO_SR(BIOS_SCRATCH_2)
130
131#define ABM_SF(reg_name, field_name, post_fix)\
132 .field_name = reg_name ## __ ## field_name ## post_fix
133
134#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
135 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
136 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
137 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
138 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
139
140#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
141 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
142 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
143 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
144 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
145 ABM1_HG_VMAX_SEL, mask_sh), \
146 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
147 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
148 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
149 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
150 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
151 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
152 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
153 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
154 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
155 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
156 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
157 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
158 ABM_SF(BL1_PWM_USER_LEVEL, \
159 BL1_PWM_USER_LEVEL, mask_sh), \
160 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
161 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
162 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
163 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
164 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
165 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
166 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
167 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
168 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
169 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
170
171#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
172 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
173 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
174 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
175 ABM1_HG_VMAX_SEL, mask_sh), \
176 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
177 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
178 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
179 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
180 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
181 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
182 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
183 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
184 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
185 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
186 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
187 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
188 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
189 BL1_PWM_USER_LEVEL, mask_sh), \
190 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
191 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
192 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
193 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
194 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
195 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
196 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
197 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
198 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
199 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
200
201#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
202 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
203 ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
204
205#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
206#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
207#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
208
209#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
210 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
211 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
212 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
213 ABM1_HG_VMAX_SEL, mask_sh), \
214 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
215 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
216 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
217 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
218 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
219 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
220 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
221 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
222 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
223 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
224 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
225 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
226 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
227 BL1_PWM_USER_LEVEL, mask_sh), \
228 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
229 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
230 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
231 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
232 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
233 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
234 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
235 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
236 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
237 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
238
239#define ABM_MASK_SH_LIST_DCN401(mask_sh) \
240 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
241 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
242 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
243 ABM1_HG_VMAX_SEL, mask_sh), \
244 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
245 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
246 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
247 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
248 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
249 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
250 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
251 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
252 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
253 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
254 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
255 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
256 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
257 BL1_PWM_USER_LEVEL, mask_sh), \
258 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
259 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
260 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
261 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
262 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
263 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
264 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
265 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
266 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
267 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
268 ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
269 ABM1_ACE_SLOPE_DATA, mask_sh), \
270 ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
271 ABM1_ACE_OFFSET_DATA, mask_sh), \
272 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
273 ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \
274 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
275 ABM1_ACE_THRES_INDEX, mask_sh), \
276 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
277 ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \
278 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
279 ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \
280 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
281 ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \
282 ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
283 ABM1_ACE_LOCK, mask_sh), \
284 ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \
285 ABM1_ACE_THRES_DATA_1, mask_sh), \
286 ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \
287 ABM1_ACE_THRES_DATA_2, mask_sh), \
288 ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
289 ABM1_HG_RESULT_DATA, mask_sh), \
290 ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
291 ABM1_HG_RESULT_INDEX, mask_sh), \
292 ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \
293 ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \
294 ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \
295 ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \
296 ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \
297 ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \
298 ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \
299 ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \
300 ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
301 ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
302
303#define ABM_REG_FIELD_LIST(type) \
304 type ABM1_HG_NUM_OF_BINS_SEL; \
305 type ABM1_HG_VMAX_SEL; \
306 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
307 type ABM1_IPCSC_COEFF_SEL_R; \
308 type ABM1_IPCSC_COEFF_SEL_G; \
309 type ABM1_IPCSC_COEFF_SEL_B; \
310 type BL1_PWM_CURRENT_ABM_LEVEL; \
311 type BL1_PWM_TARGET_ABM_LEVEL; \
312 type BL1_PWM_USER_LEVEL; \
313 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
314 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
315 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
316 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
317 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
318 type MASTER_COMM_INTERRUPT; \
319 type MASTER_COMM_CMD_REG_BYTE0; \
320 type MASTER_COMM_CMD_REG_BYTE1; \
321 type MASTER_COMM_CMD_REG_BYTE2; \
322 type ABM1_HG_BIN_33_40_SHIFT_INDEX; \
323 type ABM1_HG_BIN_33_64_SHIFT_FLAG; \
324 type ABM1_HG_BIN_41_48_SHIFT_INDEX; \
325 type ABM1_HG_BIN_49_56_SHIFT_INDEX; \
326 type ABM1_HG_BIN_57_64_SHIFT_INDEX; \
327 type ABM1_HG_RESULT_DATA; \
328 type ABM1_HG_RESULT_INDEX; \
329 type ABM1_ACE_SLOPE_DATA; \
330 type ABM1_ACE_OFFSET_DATA; \
331 type ABM1_ACE_OFFSET_SLOPE_INDEX; \
332 type ABM1_ACE_THRES_INDEX; \
333 type ABM1_ACE_IGNORE_MASTER_LOCK_EN; \
334 type ABM1_ACE_READBACK_DB_REG_VALUE_EN; \
335 type ABM1_ACE_DBUF_REG_UPDATE_PENDING; \
336 type ABM1_ACE_LOCK; \
337 type ABM1_ACE_THRES_DATA_1; \
338 type ABM1_ACE_THRES_DATA_2
339
340struct dce_abm_shift {
341 ABM_REG_FIELD_LIST(uint8_t);
342};
343
344struct dce_abm_mask {
345 ABM_REG_FIELD_LIST(uint32_t);
346};
347
348struct dce_abm_registers {
349 uint32_t DC_ABM1_HG_SAMPLE_RATE;
350 uint32_t DC_ABM1_LS_SAMPLE_RATE;
351 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
352 uint32_t DC_ABM1_HG_MISC_CTRL;
353 uint32_t DC_ABM1_IPCSC_COEFF_SEL;
354 uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
355 uint32_t BL1_PWM_TARGET_ABM_LEVEL;
356 uint32_t BL1_PWM_USER_LEVEL;
357 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
358 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
359 uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
360 uint32_t DC_ABM1_ACE_OFFSET_SLOPE_DATA;
361 uint32_t DC_ABM1_ACE_PWL_CNTL;
362 uint32_t DC_ABM1_HG_BIN_33_40_SHIFT_INDEX;
363 uint32_t DC_ABM1_HG_BIN_33_64_SHIFT_FLAG;
364 uint32_t DC_ABM1_HG_BIN_41_48_SHIFT_INDEX;
365 uint32_t DC_ABM1_HG_BIN_49_56_SHIFT_INDEX;
366 uint32_t DC_ABM1_HG_BIN_57_64_SHIFT_INDEX;
367 uint32_t DC_ABM1_HG_RESULT_DATA;
368 uint32_t DC_ABM1_HG_RESULT_INDEX;
369 uint32_t DC_ABM1_ACE_THRES_DATA;
370 uint32_t DC_ABM1_ACE_THRES_12;
371 uint32_t MASTER_COMM_CNTL_REG;
372 uint32_t MASTER_COMM_CMD_REG;
373 uint32_t MASTER_COMM_DATA_REG1;
374 uint32_t BIOS_SCRATCH_2;
375};
376
377struct dce_abm {
378 struct abm base;
379 const struct dce_abm_registers *regs;
380 const struct dce_abm_shift *abm_shift;
381 const struct dce_abm_mask *abm_mask;
382};
383
384struct abm *dce_abm_create(
385 struct dc_context *ctx,
386 const struct dce_abm_registers *regs,
387 const struct dce_abm_shift *abm_shift,
388 const struct dce_abm_mask *abm_mask);
389
390void dce_abm_destroy(struct abm **abm);
391
392#endif /* _DCE_ABM_H_ */
393

source code of linux/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h