1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef DC_TYPES_H_
26#define DC_TYPES_H_
27
28/* AND EdidUtility only needs a portion
29 * of this file, including the rest only
30 * causes additional issues.
31 */
32#include "os_types.h"
33#include "fixed31_32.h"
34#include "irq_types.h"
35#include "dc_ddc_types.h"
36#include "dc_dp_types.h"
37#include "dc_hdmi_types.h"
38#include "dc_hw_types.h"
39#include "dal_types.h"
40#include "grph_object_defs.h"
41#include "grph_object_ctrl_defs.h"
42
43#include "dm_cp_psp.h"
44
45/* forward declarations */
46struct dc_plane_state;
47struct dc_stream_state;
48struct dc_link;
49struct dc_sink;
50struct dal;
51struct dc_dmub_srv;
52
53/********************************
54 * Environment definitions
55 ********************************/
56enum dce_environment {
57 DCE_ENV_PRODUCTION_DRV = 0,
58 /* Emulation on FPGA, in "Maximus" System.
59 * This environment enforces that *only* DC registers accessed.
60 * (access to non-DC registers will hang FPGA) */
61 DCE_ENV_FPGA_MAXIMUS,
62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
63 * requirements of Diagnostics team. */
64 DCE_ENV_DIAG,
65 /*
66 * Guest VM system, DC HW may exist but is not virtualized and
67 * should not be used. SW support for VDI only.
68 */
69 DCE_ENV_VIRTUAL_HW
70};
71
72struct dc_perf_trace {
73 unsigned long read_count;
74 unsigned long write_count;
75 unsigned long last_entry_read;
76 unsigned long last_entry_write;
77};
78
79#define NUM_PIXEL_FORMATS 10
80
81enum tiling_mode {
82 TILING_MODE_INVALID,
83 TILING_MODE_LINEAR,
84 TILING_MODE_TILED,
85 TILING_MODE_COUNT
86};
87
88enum view_3d_format {
89 VIEW_3D_FORMAT_NONE = 0,
90 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
91 VIEW_3D_FORMAT_SIDE_BY_SIDE,
92 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
93 VIEW_3D_FORMAT_COUNT,
94 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
95};
96
97enum plane_stereo_format {
98 PLANE_STEREO_FORMAT_NONE = 0,
99 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
100 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
101 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
102 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
103 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
104 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
105};
106
107/* TODO: Find way to calculate number of bits
108 * Please increase if pixel_format enum increases
109 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
110 */
111
112enum dc_edid_connector_type {
113 DC_EDID_CONNECTOR_UNKNOWN = 0,
114 DC_EDID_CONNECTOR_ANALOG = 1,
115 DC_EDID_CONNECTOR_DIGITAL = 10,
116 DC_EDID_CONNECTOR_DVI = 11,
117 DC_EDID_CONNECTOR_HDMIA = 12,
118 DC_EDID_CONNECTOR_MDDI = 14,
119 DC_EDID_CONNECTOR_DISPLAYPORT = 15
120};
121
122enum dc_edid_status {
123 EDID_OK,
124 EDID_BAD_INPUT,
125 EDID_NO_RESPONSE,
126 EDID_BAD_CHECKSUM,
127 EDID_THE_SAME,
128 EDID_FALL_BACK,
129 EDID_PARTIAL_VALID,
130};
131
132enum act_return_status {
133 ACT_SUCCESS,
134 ACT_LINK_LOST,
135 ACT_FAILED
136};
137
138/* audio capability from EDID*/
139struct dc_cea_audio_mode {
140 uint8_t format_code; /* ucData[0] [6:3]*/
141 uint8_t channel_count; /* ucData[0] [2:0]*/
142 uint8_t sample_rate; /* ucData[1]*/
143 union {
144 uint8_t sample_size; /* for LPCM*/
145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
146 uint8_t max_bit_rate;
147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
148 };
149};
150
151struct dc_edid {
152 uint32_t length;
153 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
154};
155
156/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
157 * is used. In this case we assume speaker location are: front left, front
158 * right and front center. */
159#define DEFAULT_SPEAKER_LOCATION 5
160
161#define DC_MAX_AUDIO_DESC_COUNT 16
162
163#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
164
165struct dc_panel_patch {
166 unsigned int dppowerup_delay;
167 unsigned int extra_t12_ms;
168 unsigned int extra_delay_backlight_off;
169 unsigned int extra_t7_ms;
170 unsigned int skip_scdc_overwrite;
171 unsigned int delay_ignore_msa;
172 unsigned int disable_fec;
173 unsigned int extra_t3_ms;
174 unsigned int max_dsc_target_bpp_limit;
175 unsigned int embedded_tiled_slave;
176 unsigned int disable_fams;
177 unsigned int skip_avmute;
178 unsigned int skip_audio_sab_check;
179 unsigned int mst_start_top_delay;
180 unsigned int remove_sink_ext_caps;
181 unsigned int disable_colorimetry;
182 uint8_t blankstream_before_otg_off;
183 bool oled_optimize_display_on;
184 unsigned int force_mst_blocked_discovery;
185 unsigned int wait_after_dpcd_poweroff_ms;
186};
187
188/**
189 * struct dc_edid_caps - Capabilities read from EDID.
190 * @analog: Whether the monitor is analog. Used by DVI-I handling.
191 */
192struct dc_edid_caps {
193 /* sink identification */
194 uint16_t manufacturer_id;
195 uint16_t product_id;
196 uint32_t serial_number;
197 uint8_t manufacture_week;
198 uint8_t manufacture_year;
199 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
200
201 /* audio caps */
202 uint8_t speaker_flags;
203 uint32_t audio_mode_count;
204 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
205 uint32_t audio_latency;
206 uint32_t video_latency;
207
208 uint8_t qs_bit;
209 uint8_t qy_bit;
210
211 uint32_t max_tmds_clk_mhz;
212
213 /*HDMI 2.0 caps*/
214 bool lte_340mcsc_scramble;
215
216 bool edid_hdmi;
217 bool hdr_supported;
218 bool rr_capable;
219 bool scdc_present;
220 bool analog;
221
222 struct dc_panel_patch panel_patch;
223};
224
225struct dc_mode_flags {
226 /* note: part of refresh rate flag*/
227 uint32_t INTERLACE :1;
228 /* native display timing*/
229 uint32_t NATIVE :1;
230 /* preferred is the recommended mode, one per display */
231 uint32_t PREFERRED :1;
232 /* true if this mode should use reduced blanking timings
233 *_not_ related to the Reduced Blanking adjustment*/
234 uint32_t REDUCED_BLANKING :1;
235 /* note: part of refreshrate flag*/
236 uint32_t VIDEO_OPTIMIZED_RATE :1;
237 /* should be reported to upper layers as mode_flags*/
238 uint32_t PACKED_PIXEL_FORMAT :1;
239 /*< preferred view*/
240 uint32_t PREFERRED_VIEW :1;
241 /* this timing should be used only in tiled mode*/
242 uint32_t TILED_MODE :1;
243 uint32_t DSE_MODE :1;
244 /* Refresh rate divider when Miracast sink is using a
245 different rate than the output display device
246 Must be zero for wired displays and non-zero for
247 Miracast displays*/
248 uint32_t MIRACAST_REFRESH_DIVIDER;
249};
250
251
252enum dc_timing_source {
253 TIMING_SOURCE_UNDEFINED,
254
255 /* explicitly specifed by user, most important*/
256 TIMING_SOURCE_USER_FORCED,
257 TIMING_SOURCE_USER_OVERRIDE,
258 TIMING_SOURCE_CUSTOM,
259 TIMING_SOURCE_EXPLICIT,
260
261 /* explicitly specified by the display device, more important*/
262 TIMING_SOURCE_EDID_CEA_SVD_3D,
263 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
264 TIMING_SOURCE_EDID_CEA_SVD_420,
265 TIMING_SOURCE_EDID_DETAILED,
266 TIMING_SOURCE_EDID_ESTABLISHED,
267 TIMING_SOURCE_EDID_STANDARD,
268 TIMING_SOURCE_EDID_CEA_SVD,
269 TIMING_SOURCE_EDID_CVT_3BYTE,
270 TIMING_SOURCE_EDID_4BYTE,
271 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
272 TIMING_SOURCE_EDID_CEA_RID,
273 TIMING_SOURCE_EDID_DISPLAYID_TYPE5,
274 TIMING_SOURCE_VBIOS,
275 TIMING_SOURCE_CV,
276 TIMING_SOURCE_TV,
277 TIMING_SOURCE_HDMI_VIC,
278
279 /* implicitly specified by display device, still safe but less important*/
280 TIMING_SOURCE_DEFAULT,
281
282 /* only used for custom base modes */
283 TIMING_SOURCE_CUSTOM_BASE,
284
285 /* these timing might not work, least important*/
286 TIMING_SOURCE_RANGELIMIT,
287 TIMING_SOURCE_OS_FORCED,
288 TIMING_SOURCE_IMPLICIT,
289
290 /* only used by default mode list*/
291 TIMING_SOURCE_BASICMODE,
292
293 TIMING_SOURCE_COUNT
294};
295
296
297struct stereo_3d_features {
298 bool supported ;
299 bool allTimings ;
300 bool cloneMode ;
301 bool scaling ;
302 bool singleFrameSWPacked;
303};
304
305enum dc_timing_support_method {
306 TIMING_SUPPORT_METHOD_UNDEFINED,
307 TIMING_SUPPORT_METHOD_EXPLICIT,
308 TIMING_SUPPORT_METHOD_IMPLICIT,
309 TIMING_SUPPORT_METHOD_NATIVE
310};
311
312struct dc_mode_info {
313 uint32_t pixel_width;
314 uint32_t pixel_height;
315 uint32_t field_rate;
316 /* Vertical refresh rate for progressive modes.
317 * Field rate for interlaced modes.*/
318
319 enum dc_timing_standard timing_standard;
320 enum dc_timing_source timing_source;
321 struct dc_mode_flags flags;
322};
323
324enum dc_power_state {
325 DC_POWER_STATE_ON = 1,
326 DC_POWER_STATE_STANDBY,
327 DC_POWER_STATE_SUSPEND,
328 DC_POWER_STATE_OFF
329};
330
331/* DC PowerStates */
332enum dc_video_power_state {
333 DC_VIDEO_POWER_UNSPECIFIED = 0,
334 DC_VIDEO_POWER_ON = 1,
335 DC_VIDEO_POWER_STANDBY,
336 DC_VIDEO_POWER_SUSPEND,
337 DC_VIDEO_POWER_OFF,
338 DC_VIDEO_POWER_HIBERNATE,
339 DC_VIDEO_POWER_SHUTDOWN,
340 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
341 DC_VIDEO_POWER_AFTER_RESET,
342 DC_VIDEO_POWER_MAXIMUM
343};
344
345enum dc_acpi_cm_power_state {
346 DC_ACPI_CM_POWER_STATE_D0 = 1,
347 DC_ACPI_CM_POWER_STATE_D1 = 2,
348 DC_ACPI_CM_POWER_STATE_D2 = 4,
349 DC_ACPI_CM_POWER_STATE_D3 = 8
350};
351
352enum dc_connection_type {
353 dc_connection_none,
354 dc_connection_single,
355 dc_connection_mst_branch,
356 dc_connection_sst_branch,
357 dc_connection_dac_load
358};
359
360struct dc_csc_adjustments {
361 struct fixed31_32 contrast;
362 struct fixed31_32 saturation;
363 struct fixed31_32 brightness;
364 struct fixed31_32 hue;
365};
366
367/* Scaling format */
368enum scaling_transformation {
369 SCALING_TRANSFORMATION_UNINITIALIZED,
370 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
371 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
372 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
373 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
374 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
375 SCALING_TRANSFORMATION_INVALID = 0x80000000,
376
377 /* Flag the first and last */
378 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
379 SCALING_TRANSFORMATION_END =
380 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
381};
382
383enum display_content_type {
384 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
385 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
386 DISPLAY_CONTENT_TYPE_PHOTO = 2,
387 DISPLAY_CONTENT_TYPE_CINEMA = 4,
388 DISPLAY_CONTENT_TYPE_GAME = 8
389};
390
391enum cm_gamut_adjust_type {
392 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
393 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
394 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
395};
396
397struct cm_grph_csc_adjustment {
398 struct fixed31_32 temperature_matrix[12];
399 enum cm_gamut_adjust_type gamut_adjust_type;
400 enum cm_gamut_coef_format gamut_coef_format;
401};
402
403/* writeback */
404struct dwb_stereo_params {
405 bool stereo_enabled; /* false: normal mode, true: 3D stereo */
406 enum dwb_stereo_type stereo_type; /* indicates stereo format */
407 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
408 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
409};
410
411struct dc_dwb_cnv_params {
412 unsigned int src_width; /* input active width */
413 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
414 unsigned int crop_width; /* cropped window width at cnv output */
415 bool crop_en; /* window cropping enable in cnv */
416 unsigned int crop_height; /* cropped window height at cnv output */
417 unsigned int crop_x; /* cropped window start x value at cnv output */
418 unsigned int crop_y; /* cropped window start y value at cnv output */
419 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
420 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
421 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
422 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
423 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
424};
425
426struct dc_dwb_params {
427 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
428 unsigned int hdr_mult; /* must be in FP1.6.12 */
429 struct cm_grph_csc_adjustment csc_params;
430 struct dwb_stereo_params stereo_params;
431 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
432 unsigned int dest_width; /* Destination width */
433 unsigned int dest_height; /* Destination height */
434 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
435 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
436 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
437 struct scaling_taps scaler_taps; /* Scaling taps */
438 enum dwb_subsample_position subsample_position;
439 const struct dc_transfer_func *out_transfer_func;
440};
441
442/* audio*/
443
444union audio_sample_rates {
445 struct sample_rates {
446 uint8_t RATE_32:1;
447 uint8_t RATE_44_1:1;
448 uint8_t RATE_48:1;
449 uint8_t RATE_88_2:1;
450 uint8_t RATE_96:1;
451 uint8_t RATE_176_4:1;
452 uint8_t RATE_192:1;
453 } rate;
454
455 uint8_t all;
456};
457
458struct audio_speaker_flags {
459 uint32_t FL_FR:1;
460 uint32_t LFE:1;
461 uint32_t FC:1;
462 uint32_t RL_RR:1;
463 uint32_t RC:1;
464 uint32_t FLC_FRC:1;
465 uint32_t RLC_RRC:1;
466 uint32_t SUPPORT_AI:1;
467};
468
469struct audio_speaker_info {
470 uint32_t ALLSPEAKERS:7;
471 uint32_t SUPPORT_AI:1;
472};
473
474
475struct audio_info_flags {
476
477 union {
478
479 struct audio_speaker_flags speaker_flags;
480 struct audio_speaker_info info;
481
482 uint8_t all;
483 };
484};
485
486enum audio_format_code {
487 AUDIO_FORMAT_CODE_FIRST = 1,
488 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
489
490 AUDIO_FORMAT_CODE_AC3,
491 /*Layers 1 & 2 */
492 AUDIO_FORMAT_CODE_MPEG1,
493 /*MPEG1 Layer 3 */
494 AUDIO_FORMAT_CODE_MP3,
495 /*multichannel */
496 AUDIO_FORMAT_CODE_MPEG2,
497 AUDIO_FORMAT_CODE_AAC,
498 AUDIO_FORMAT_CODE_DTS,
499 AUDIO_FORMAT_CODE_ATRAC,
500 AUDIO_FORMAT_CODE_1BITAUDIO,
501 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
502 AUDIO_FORMAT_CODE_DTS_HD,
503 AUDIO_FORMAT_CODE_MAT_MLP,
504 AUDIO_FORMAT_CODE_DST,
505 AUDIO_FORMAT_CODE_WMAPRO,
506 AUDIO_FORMAT_CODE_LAST,
507 AUDIO_FORMAT_CODE_COUNT =
508 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
509};
510
511struct audio_mode {
512 /* ucData[0] [6:3] */
513 enum audio_format_code format_code;
514 /* ucData[0] [2:0] */
515 uint8_t channel_count;
516 /* ucData[1] */
517 union audio_sample_rates sample_rates;
518 union {
519 /* for LPCM */
520 uint8_t sample_size;
521 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
522 uint8_t max_bit_rate;
523 /* for Audio Formats 9-15 */
524 uint8_t vendor_specific;
525 };
526};
527
528struct audio_info {
529 struct audio_info_flags flags;
530 uint32_t video_latency;
531 uint32_t audio_latency;
532 uint32_t display_index;
533 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
534 uint32_t manufacture_id;
535 uint32_t product_id;
536 /* PortID used for ContainerID when defined */
537 uint32_t port_id[2];
538 uint32_t mode_count;
539 /* this field must be last in this struct */
540 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
541};
542struct audio_check {
543 unsigned int audio_packet_type;
544 unsigned int max_audiosample_rate;
545 unsigned int acat;
546};
547enum dc_infoframe_type {
548 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
549 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
550 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
551 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
552 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
553};
554
555struct dc_info_packet {
556 bool valid;
557 uint8_t hb0;
558 uint8_t hb1;
559 uint8_t hb2;
560 uint8_t hb3;
561 uint8_t sb[32];
562};
563
564struct dc_info_packet_128 {
565 bool valid;
566 uint8_t hb0;
567 uint8_t hb1;
568 uint8_t hb2;
569 uint8_t hb3;
570 uint8_t sb[128];
571};
572
573struct dc_edid_read_policy {
574 uint32_t max_retry_count;
575 uint32_t delay_time_ms;
576 uint32_t ignore_checksum;
577};
578
579#define DC_PLANE_UPDATE_TIMES_MAX 10
580
581struct dc_plane_flip_time {
582 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
583 unsigned int index;
584 unsigned int prev_update_time_in_us;
585};
586
587enum dc_alpm_mode {
588 DC_ALPM_AUXWAKE = 0,
589 DC_ALPM_AUXLESS = 1,
590 DC_ALPM_UNSUPPORTED = 0xF,
591};
592
593enum dc_psr_state {
594 PSR_STATE0 = 0x0,
595 PSR_STATE1,
596 PSR_STATE1a,
597 PSR_STATE2,
598 PSR_STATE2a,
599 PSR_STATE2b,
600 PSR_STATE3,
601 PSR_STATE3Init,
602 PSR_STATE4,
603 PSR_STATE4a,
604 PSR_STATE4b,
605 PSR_STATE4c,
606 PSR_STATE4d,
607 PSR_STATE4_FULL_FRAME,
608 PSR_STATE4a_FULL_FRAME,
609 PSR_STATE4b_FULL_FRAME,
610 PSR_STATE4c_FULL_FRAME,
611 PSR_STATE4_FULL_FRAME_POWERUP,
612 PSR_STATE4_FULL_FRAME_HW_LOCK,
613 PSR_STATE5,
614 PSR_STATE5a,
615 PSR_STATE5b,
616 PSR_STATE5c,
617 PSR_STATE_HWLOCK_MGR,
618 PSR_STATE_POLLVUPDATE,
619 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME,
620 PSR_STATE_INVALID = 0xFF
621};
622
623struct psr_config {
624 unsigned char psr_version;
625 unsigned int psr_rfb_setup_time;
626 bool psr_exit_link_training_required;
627 bool psr_frame_capture_indication_req;
628 unsigned int psr_sdp_transmit_line_num_deadline;
629 bool allow_smu_optimizations;
630 bool allow_multi_disp_optimizations;
631 /* Panel self refresh 2 selective update granularity required */
632 bool su_granularity_required;
633 /* psr2 selective update y granularity capability */
634 uint8_t su_y_granularity;
635 unsigned int line_time_in_us;
636 uint8_t rate_control_caps;
637 uint16_t dsc_slice_height;
638 bool os_request_force_ffu;
639};
640
641union dmcu_psr_level {
642 struct {
643 unsigned int SKIP_CRC:1;
644 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
645 unsigned int SKIP_PHY_POWER_DOWN:1;
646 unsigned int SKIP_AUX_ACK_CHECK:1;
647 unsigned int SKIP_CRTC_DISABLE:1;
648 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
649 unsigned int SKIP_SMU_NOTIFICATION:1;
650 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
651 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
652 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
653 unsigned int DISABLE_ALPM:1;
654 unsigned int ALPM_DEFAULT_PD_MODE:1;
655 unsigned int RESERVED:20;
656 } bits;
657 unsigned int u32all;
658};
659
660enum physical_phy_id {
661 PHYLD_0,
662 PHYLD_1,
663 PHYLD_2,
664 PHYLD_3,
665 PHYLD_4,
666 PHYLD_5,
667 PHYLD_6,
668 PHYLD_7,
669 PHYLD_8,
670 PHYLD_9,
671 PHYLD_COUNT,
672 PHYLD_UNKNOWN = (-1L)
673};
674
675enum phy_type {
676 PHY_TYPE_UNKNOWN = 1,
677 PHY_TYPE_PCIE_PHY = 2,
678 PHY_TYPE_UNIPHY = 3,
679};
680
681struct psr_context {
682 /* ddc line */
683 enum channel_id channel;
684 /* Transmitter id */
685 enum transmitter transmitterId;
686 /* Engine Id is used for Dig Be source select */
687 enum engine_id engineId;
688 /* Controller Id used for Dig Fe source select */
689 enum controller_id controllerId;
690 /* Pcie or Uniphy */
691 enum phy_type phyType;
692 /* Physical PHY Id used by SMU interpretation */
693 enum physical_phy_id smuPhyId;
694 /* Vertical total pixels from crtc timing.
695 * This is used for static screen detection.
696 * ie. If we want to detect half a frame,
697 * we use this to determine the hyst lines.
698 */
699 unsigned int crtcTimingVerticalTotal;
700 /* PSR supported from panel capabilities and
701 * current display configuration
702 */
703 bool psrSupportedDisplayConfig;
704 /* Whether fast link training is supported by the panel */
705 bool psrExitLinkTrainingRequired;
706 /* If RFB setup time is greater than the total VBLANK time,
707 * it is not possible for the sink to capture the video frame
708 * in the same frame the SDP is sent. In this case,
709 * the frame capture indication bit should be set and an extra
710 * static frame should be transmitted to the sink.
711 */
712 bool psrFrameCaptureIndicationReq;
713 /* Set the last possible line SDP may be transmitted without violating
714 * the RFB setup time or entering the active video frame.
715 */
716 unsigned int sdpTransmitLineNumDeadline;
717 /* The VSync rate in Hz used to calculate the
718 * step size for smooth brightness feature
719 */
720 unsigned int vsync_rate_hz;
721 unsigned int skipPsrWaitForPllLock;
722 unsigned int numberOfControllers;
723 /* Unused, for future use. To indicate that first changed frame from
724 * state3 shouldn't result in psr_inactive, but rather to perform
725 * an automatic single frame rfb_update.
726 */
727 bool rfb_update_auto_en;
728 /* Number of frame before entering static screen */
729 unsigned int timehyst_frames;
730 /* Partial frames before entering static screen */
731 unsigned int hyst_lines;
732 /* # of repeated AUX transaction attempts to make before
733 * indicating failure to the driver
734 */
735 unsigned int aux_repeats;
736 /* Controls hw blocks to power down during PSR active state */
737 union dmcu_psr_level psr_level;
738 /* Controls additional delay after remote frame capture before
739 * continuing powerd own
740 */
741 unsigned int frame_delay;
742 bool allow_smu_optimizations;
743 bool allow_multi_disp_optimizations;
744 /* Panel self refresh 2 selective update granularity required */
745 bool su_granularity_required;
746 /* psr2 selective update y granularity capability */
747 uint8_t su_y_granularity;
748 unsigned int line_time_in_us;
749 uint8_t rate_control_caps;
750 uint16_t dsc_slice_height;
751 bool os_request_force_ffu;
752};
753
754struct colorspace_transform {
755 struct fixed31_32 matrix[12];
756 bool enable_remap;
757};
758
759enum i2c_mot_mode {
760 I2C_MOT_UNDEF,
761 I2C_MOT_TRUE,
762 I2C_MOT_FALSE
763};
764
765struct AsicStateEx {
766 unsigned int memoryClock;
767 unsigned int displayClock;
768 unsigned int engineClock;
769 unsigned int maxSupportedDppClock;
770 unsigned int dppClock;
771 unsigned int socClock;
772 unsigned int dcfClockDeepSleep;
773 unsigned int fClock;
774 unsigned int phyClock;
775};
776
777
778enum dc_clock_type {
779 DC_CLOCK_TYPE_DISPCLK = 0,
780 DC_CLOCK_TYPE_DPPCLK = 1,
781};
782
783struct dc_clock_config {
784 uint32_t max_clock_khz;
785 uint32_t min_clock_khz;
786 uint32_t bw_requirequired_clock_khz;
787 uint32_t current_clock_khz;/*current clock in use*/
788};
789
790struct hw_asic_id {
791 uint32_t chip_id;
792 uint32_t chip_family;
793 uint32_t pci_revision_id;
794 uint32_t hw_internal_rev;
795 uint32_t vram_type;
796 uint32_t vram_width;
797 uint32_t feature_flags;
798 uint32_t fake_paths_num;
799 void *atombios_base_address;
800};
801
802struct dc_context {
803 struct dc *dc;
804
805 void *driver_context; /* e.g. amdgpu_device */
806 struct dal_logger *logger;
807 struct dc_perf_trace *perf_trace;
808 void *cgs_device;
809
810 enum dce_environment dce_environment;
811 struct hw_asic_id asic_id;
812
813 /* todo: below should probably move to dc. to facilitate removal
814 * of AS we will store these here
815 */
816 enum dce_version dce_version;
817 struct dc_bios *dc_bios;
818 bool created_bios;
819 struct gpio_service *gpio_service;
820 uint32_t dc_sink_id_count;
821 uint32_t dc_stream_id_count;
822 uint32_t dc_edp_id_count;
823 uint64_t fbc_gpu_addr;
824 struct dc_dmub_srv *dmub_srv;
825 struct cp_psp cp_psp;
826 uint32_t *dcn_reg_offsets;
827 uint32_t *nbio_reg_offsets;
828 uint32_t *clk_reg_offsets;
829};
830
831/* DSC DPCD capabilities */
832union dsc_slice_caps1 {
833 struct {
834 uint8_t NUM_SLICES_1 : 1;
835 uint8_t NUM_SLICES_2 : 1;
836 uint8_t RESERVED : 1;
837 uint8_t NUM_SLICES_4 : 1;
838 uint8_t NUM_SLICES_6 : 1;
839 uint8_t NUM_SLICES_8 : 1;
840 uint8_t NUM_SLICES_10 : 1;
841 uint8_t NUM_SLICES_12 : 1;
842 } bits;
843 uint8_t raw;
844};
845
846union dsc_slice_caps2 {
847 struct {
848 uint8_t NUM_SLICES_16 : 1;
849 uint8_t NUM_SLICES_20 : 1;
850 uint8_t NUM_SLICES_24 : 1;
851 uint8_t RESERVED : 5;
852 } bits;
853 uint8_t raw;
854};
855
856union dsc_color_formats {
857 struct {
858 uint8_t RGB : 1;
859 uint8_t YCBCR_444 : 1;
860 uint8_t YCBCR_SIMPLE_422 : 1;
861 uint8_t YCBCR_NATIVE_422 : 1;
862 uint8_t YCBCR_NATIVE_420 : 1;
863 uint8_t RESERVED : 3;
864 } bits;
865 uint8_t raw;
866};
867
868union dsc_color_depth {
869 struct {
870 uint8_t RESERVED1 : 1;
871 uint8_t COLOR_DEPTH_8_BPC : 1;
872 uint8_t COLOR_DEPTH_10_BPC : 1;
873 uint8_t COLOR_DEPTH_12_BPC : 1;
874 uint8_t RESERVED2 : 3;
875 } bits;
876 uint8_t raw;
877};
878
879struct dsc_dec_dpcd_caps {
880 bool is_dsc_supported;
881 uint8_t dsc_version;
882 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
883 union dsc_slice_caps1 slice_caps1;
884 union dsc_slice_caps2 slice_caps2;
885 int32_t lb_bit_depth;
886 bool is_block_pred_supported;
887 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
888 union dsc_color_formats color_formats;
889 union dsc_color_depth color_depth;
890 int32_t throughput_mode_0_mps; /* In MPs */
891 int32_t throughput_mode_1_mps; /* In MPs */
892 int32_t max_slice_width;
893 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
894
895 /* Extended DSC caps */
896 uint32_t branch_overall_throughput_0_mps; /* In MPs */
897 uint32_t branch_overall_throughput_1_mps; /* In MPs */
898 uint32_t branch_max_line_width;
899 bool is_dp; /* Decoded format */
900};
901
902struct hblank_expansion_dpcd_caps {
903 bool expansion_supported;
904 bool reduction_supported;
905 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/
906 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/
907 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */
908};
909
910struct dc_golden_table {
911 uint16_t dc_golden_table_ver;
912 uint32_t aux_dphy_rx_control0_val;
913 uint32_t aux_dphy_tx_control_val;
914 uint32_t aux_dphy_rx_control1_val;
915 uint32_t dc_gpio_aux_ctrl_0_val;
916 uint32_t dc_gpio_aux_ctrl_1_val;
917 uint32_t dc_gpio_aux_ctrl_2_val;
918 uint32_t dc_gpio_aux_ctrl_3_val;
919 uint32_t dc_gpio_aux_ctrl_4_val;
920 uint32_t dc_gpio_aux_ctrl_5_val;
921};
922
923enum dc_gpu_mem_alloc_type {
924 DC_MEM_ALLOC_TYPE_GART,
925 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
926 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
927 DC_MEM_ALLOC_TYPE_AGP
928};
929
930enum dc_link_encoding_format {
931 DC_LINK_ENCODING_UNSPECIFIED = 0,
932 DC_LINK_ENCODING_DP_8b_10b,
933 DC_LINK_ENCODING_DP_128b_132b,
934 DC_LINK_ENCODING_HDMI_TMDS,
935 DC_LINK_ENCODING_HDMI_FRL
936};
937
938enum dc_psr_version {
939 DC_PSR_VERSION_1 = 0,
940 DC_PSR_VERSION_SU_1 = 1,
941 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
942};
943
944enum dc_replay_version {
945 DC_FREESYNC_REPLAY = 0,
946 DC_VESA_PANEL_REPLAY = 1,
947 DC_REPLAY_VERSION_UNSUPPORTED = 0XFF,
948};
949
950/* Possible values of display_endpoint_id.endpoint */
951enum display_endpoint_type {
952 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
953 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
954 DISPLAY_ENDPOINT_UNKNOWN = -1
955};
956
957/* Extends graphics_object_id with an additional member 'ep_type' for
958 * distinguishing between physical endpoints (with entries in BIOS connector table) and
959 * logical endpoints.
960 */
961struct display_endpoint_id {
962 struct graphics_object_id link_id;
963 enum display_endpoint_type ep_type;
964};
965
966enum backlight_control_type {
967 BACKLIGHT_CONTROL_PWM = 0,
968 BACKLIGHT_CONTROL_VESA_AUX = 1,
969 BACKLIGHT_CONTROL_AMD_AUX = 2,
970};
971
972#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
973#define MAX_CRC_WINDOW_NUM 2
974
975struct otg_phy_mux {
976 uint8_t phy_output_num;
977 uint8_t otg_output_num;
978};
979
980struct crc_window {
981 struct rect rect;
982 bool enable;
983};
984#endif
985
986enum dc_detect_reason {
987 DETECT_REASON_BOOT,
988 DETECT_REASON_RESUMEFROMS3S4,
989 DETECT_REASON_HPD,
990 DETECT_REASON_HPDRX,
991 DETECT_REASON_FALLBACK,
992 DETECT_REASON_RETRAIN,
993 DETECT_REASON_TDR,
994};
995
996struct dc_link_status {
997 bool link_active;
998 struct dpcd_caps *dpcd_caps;
999};
1000
1001union hdcp_rx_caps {
1002 struct {
1003 uint8_t version;
1004 uint8_t reserved;
1005 struct {
1006 uint8_t repeater : 1;
1007 uint8_t hdcp_capable : 1;
1008 uint8_t reserved : 6;
1009 } byte0;
1010 } fields;
1011 uint8_t raw[3];
1012};
1013
1014union hdcp_bcaps {
1015 struct {
1016 uint8_t HDCP_CAPABLE:1;
1017 uint8_t REPEATER:1;
1018 uint8_t RESERVED:6;
1019 } bits;
1020 uint8_t raw;
1021};
1022
1023struct hdcp_caps {
1024 union hdcp_rx_caps rx_caps;
1025 union hdcp_bcaps bcaps;
1026};
1027
1028/* DP MST stream allocation (payload bandwidth number) */
1029struct link_mst_stream_allocation {
1030 /* DIG front */
1031 const struct stream_encoder *stream_enc;
1032 /* HPO DP Stream Encoder */
1033 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
1034 /* associate DRM payload table with DC stream encoder */
1035 uint8_t vcp_id;
1036 /* number of slots required for the DP stream in transport packet */
1037 uint8_t slot_count;
1038};
1039
1040#define MAX_CONTROLLER_NUM 6
1041
1042/* DP MST stream allocation table */
1043struct link_mst_stream_allocation_table {
1044 /* number of DP video streams */
1045 int stream_count;
1046 /* array of stream allocations */
1047 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
1048};
1049
1050/* PSR feature flags */
1051struct psr_settings {
1052 bool psr_feature_enabled; // PSR is supported by sink
1053 bool psr_allow_active; // PSR is currently active
1054 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD
1055 bool psr_vtotal_control_support; // Vtotal control is supported by sink
1056 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU
1057
1058 /* These parameters are calculated in Driver,
1059 * based on display timing and Sink capabilities.
1060 * If VBLANK region is too small and Sink takes a long time
1061 * to set up RFB, it may take an extra frame to enter PSR state.
1062 */
1063 bool psr_frame_capture_indication_req;
1064 unsigned int psr_sdp_transmit_line_num_deadline;
1065 uint8_t force_ffu_mode;
1066 unsigned int psr_power_opt;
1067
1068 /**
1069 * Some panels cannot handle idle pattern during PSR entry.
1070 * To power down phy before disable stream to avoid sending
1071 * idle pattern.
1072 */
1073 uint8_t power_down_phy_before_disable_stream;
1074};
1075
1076enum replay_coasting_vtotal_type {
1077 PR_COASTING_TYPE_NOM = 0,
1078 PR_COASTING_TYPE_STATIC,
1079 PR_COASTING_TYPE_FULL_SCREEN_VIDEO,
1080 PR_COASTING_TYPE_TEST_HARNESS,
1081 PR_COASTING_TYPE_NUM,
1082};
1083
1084enum replay_link_off_frame_count_level {
1085 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0,
1086 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2,
1087 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6,
1088};
1089
1090/*
1091 * This is general Interface for Replay to
1092 * set an 32 bit variable to dmub
1093 * The Message_type indicates which variable
1094 * passed to DMUB.
1095 */
1096enum replay_FW_Message_type {
1097 Replay_Msg_Not_Support = -1,
1098 Replay_Set_Timing_Sync_Supported,
1099 Replay_Set_Residency_Frameupdate_Timer,
1100 Replay_Set_Pseudo_VTotal,
1101 Replay_Disabled_Adaptive_Sync_SDP,
1102 Replay_Set_Version,
1103 Replay_Set_General_Cmd,
1104};
1105
1106union replay_error_status {
1107 struct {
1108 unsigned int STATE_TRANSITION_ERROR :1;
1109 unsigned int LINK_CRC_ERROR :1;
1110 unsigned int DESYNC_ERROR :1;
1111 unsigned int RESERVED_3 :1;
1112 unsigned int LOW_RR_INCORRECT_VTOTAL :1;
1113 unsigned int NO_DOUBLED_RR :1;
1114 unsigned int RESERVED_6_7 :2;
1115 } bits;
1116 unsigned char raw;
1117};
1118
1119union replay_low_refresh_rate_enable_options {
1120 struct {
1121 //BIT[0-3]: Replay Low Hz Support control
1122 unsigned int ENABLE_LOW_RR_SUPPORT :1;
1123 unsigned int SKIP_ASIC_CHECK :1;
1124 unsigned int RESERVED_2_3 :2;
1125 //BIT[4-15]: Replay Low Hz Enable Scenarios
1126 unsigned int ENABLE_STATIC_SCREEN :1;
1127 unsigned int ENABLE_FULL_SCREEN_VIDEO :1;
1128 unsigned int ENABLE_GENERAL_UI :1;
1129 unsigned int RESERVED_7_15 :9;
1130 //BIT[16-31]: Replay Low Hz Enable Check
1131 unsigned int ENABLE_STATIC_FLICKER_CHECK :1;
1132 unsigned int RESERVED_17_31 :15;
1133 } bits;
1134 unsigned int raw;
1135};
1136
1137struct replay_config {
1138 /* Replay version */
1139 enum dc_replay_version replay_version;
1140 /* Replay feature is supported */
1141 bool replay_supported;
1142 /* Replay caps support DPCD & EDID caps*/
1143 bool replay_cap_support;
1144 /* Power opt flags that are supported */
1145 unsigned int replay_power_opt_supported;
1146 /* SMU optimization is supported */
1147 bool replay_smu_opt_supported;
1148 /* Replay enablement option */
1149 unsigned int replay_enable_option;
1150 /* Replay debug flags */
1151 uint32_t debug_flags;
1152 /* Replay sync is supported */
1153 bool replay_timing_sync_supported;
1154 /* Replay Disable desync error check. */
1155 bool force_disable_desync_error_check;
1156 /* Replay Received Desync Error HPD. */
1157 bool received_desync_error_hpd;
1158 /* Replay feature is supported long vblank */
1159 bool replay_support_fast_resync_in_ultra_sleep_mode;
1160 /* Replay error status */
1161 union replay_error_status replay_error_status;
1162 /* Replay Low Hz enable Options */
1163 union replay_low_refresh_rate_enable_options low_rr_enable_options;
1164 /* Replay coasting vtotal is within low refresh rate range. */
1165 bool low_rr_activated;
1166 /* Replay low refresh rate supported*/
1167 bool low_rr_supported;
1168 /* Replay Video Conferencing Optimization Enabled */
1169 bool replay_video_conferencing_optimization_enabled;
1170 /* Replay alpm mode */
1171 enum dc_alpm_mode alpm_mode;
1172 /* Replay full screen only */
1173 bool os_request_force_ffu;
1174};
1175
1176/* Replay feature flags*/
1177struct replay_settings {
1178 /* Replay configuration */
1179 struct replay_config config;
1180 /* Replay feature is ready for activating */
1181 bool replay_feature_enabled;
1182 /* Replay is currently active */
1183 bool replay_allow_active;
1184 /* Replay is currently active */
1185 bool replay_allow_long_vblank;
1186 /* Power opt flags that are activated currently */
1187 unsigned int replay_power_opt_active;
1188 /* SMU optimization is enabled */
1189 bool replay_smu_opt_enable;
1190 /* Current Coasting vtotal */
1191 uint32_t coasting_vtotal;
1192 /* Coasting vtotal table */
1193 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
1194 /* Defer Update Coasting vtotal table */
1195 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM];
1196 /* Skip frame number table */
1197 uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM];
1198 /* Defer skip frame number table */
1199 uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM];
1200 /* Maximum link off frame count */
1201 uint32_t link_off_frame_count;
1202 /* Replay pseudo vtotal for low refresh rate*/
1203 uint16_t low_rr_full_screen_video_pseudo_vtotal;
1204 /* Replay last pseudo vtotal set to DMUB */
1205 uint16_t last_pseudo_vtotal;
1206 /* Replay desync error */
1207 uint32_t replay_desync_error_fail_count;
1208 /* The frame skip number dal send to DMUB */
1209 uint16_t frame_skip_number;
1210};
1211
1212/* To split out "global" and "per-panel" config settings.
1213 * Add a struct dc_panel_config under dc_link
1214 */
1215struct dc_panel_config {
1216 /* extra panel power sequence parameters */
1217 struct pps {
1218 unsigned int extra_t3_ms;
1219 unsigned int extra_t7_ms;
1220 unsigned int extra_delay_backlight_off;
1221 unsigned int extra_post_t7_ms;
1222 unsigned int extra_pre_t11_ms;
1223 unsigned int extra_t12_ms;
1224 unsigned int extra_post_OUI_ms;
1225 } pps;
1226 /* nit brightness */
1227 struct nits_brightness {
1228 unsigned int peak; /* nits */
1229 unsigned int max_avg; /* nits */
1230 unsigned int min; /* 1/10000 nits */
1231 unsigned int max_nonboost_brightness_millinits;
1232 unsigned int min_brightness_millinits;
1233 } nits_brightness;
1234 /* PSR */
1235 struct psr {
1236 bool disable_psr;
1237 bool disallow_psrsu;
1238 bool disallow_replay;
1239 bool rc_disable;
1240 bool rc_allow_static_screen;
1241 bool rc_allow_fullscreen_VPB;
1242 bool read_psrcap_again;
1243 unsigned int replay_enable_option;
1244 } psr;
1245 /* ABM */
1246 struct varib {
1247 unsigned int varibright_feature_enable;
1248 unsigned int def_varibright_level;
1249 unsigned int abm_config_setting;
1250 } varib;
1251 /* edp DSC */
1252 struct dsc {
1253 bool disable_dsc_edp;
1254 unsigned int force_dsc_edp_policy;
1255 } dsc;
1256 /* eDP ILR */
1257 struct ilr {
1258 bool optimize_edp_link_rate; /* eDP ILR */
1259 } ilr;
1260};
1261
1262#define MAX_SINKS_PER_LINK 4
1263
1264/*
1265 * USB4 DPIA BW ALLOCATION STRUCTS
1266 */
1267struct dc_dpia_bw_alloc {
1268 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks
1269 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already
1270 int link_max_bw; // The Max BW that link can require/support
1271 int allocated_bw; // The Actual Allocated BW for this DPIA
1272 int estimated_bw; // The estimated available BW for this DPIA
1273 int bw_granularity; // BW Granularity
1274 int dp_overhead; // DP overhead in dp tunneling
1275 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
1276 uint8_t nrd_max_lane_count; // Non-reduced max lane count
1277 uint8_t nrd_max_link_rate; // Non-reduced max link rate
1278};
1279
1280enum dc_hpd_enable_select {
1281 HPD_EN_FOR_ALL_EDP = 0,
1282 HPD_EN_FOR_PRIMARY_EDP_ONLY,
1283 HPD_EN_FOR_SECONDARY_EDP_ONLY,
1284};
1285
1286enum dc_cm2_shaper_3dlut_setting {
1287 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL,
1288 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER,
1289 /* Bypassing Shaper will always bypass 3DLUT */
1290 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT
1291};
1292
1293enum dc_cm2_gpu_mem_layout {
1294 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB,
1295 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR,
1296 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR
1297};
1298
1299enum dc_cm2_gpu_mem_pixel_component_order {
1300 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,
1301};
1302
1303enum dc_cm2_gpu_mem_format {
1304 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB,
1305 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB,
1306 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10
1307};
1308
1309struct dc_cm2_gpu_mem_format_parameters {
1310 enum dc_cm2_gpu_mem_format format;
1311 union {
1312 struct {
1313 /* bias & scale for float only */
1314 uint16_t bias;
1315 uint16_t scale;
1316 } float_params;
1317 };
1318};
1319
1320enum dc_cm2_gpu_mem_size {
1321 DC_CM2_GPU_MEM_SIZE_171717,
1322 DC_CM2_GPU_MEM_SIZE_TRANSFORMED,
1323};
1324
1325struct dc_cm2_gpu_mem_parameters {
1326 struct dc_plane_address addr;
1327 enum dc_cm2_gpu_mem_layout layout;
1328 struct dc_cm2_gpu_mem_format_parameters format_params;
1329 enum dc_cm2_gpu_mem_pixel_component_order component_order;
1330 enum dc_cm2_gpu_mem_size size;
1331 uint16_t bit_depth;
1332};
1333
1334enum dc_cm2_transfer_func_source {
1335 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM,
1336 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM
1337};
1338
1339struct dc_cm2_component_settings {
1340 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting;
1341 bool lut1d_enable;
1342};
1343
1344/*
1345 * All pointers in this struct must remain valid for as long as the 3DLUTs are used
1346 */
1347struct dc_cm2_func_luts {
1348 const struct dc_transfer_func *shaper;
1349 struct {
1350 enum dc_cm2_transfer_func_source lut3d_src;
1351 union {
1352 const struct dc_3dlut *lut3d_func;
1353 struct dc_cm2_gpu_mem_parameters gpu_mem_params;
1354 };
1355 bool rmcm_3dlut_shaper_select;
1356 bool mpc_3dlut_enable;
1357 bool rmcm_3dlut_enable;
1358 bool mpc_mcm_post_blend;
1359 uint8_t rmcm_tmz;
1360 } lut3d_data;
1361 const struct dc_transfer_func *lut1d_func;
1362};
1363
1364struct dc_cm2_parameters {
1365 struct dc_cm2_component_settings component_settings;
1366 struct dc_cm2_func_luts cm2_luts;
1367};
1368
1369enum mall_stream_type {
1370 SUBVP_NONE, // subvp not in use
1371 SUBVP_MAIN, // subvp in use, this stream is main stream
1372 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
1373};
1374
1375enum dc_power_source_type {
1376 DC_POWER_SOURCE_AC, // wall power
1377 DC_POWER_SOURCE_DC, // battery power
1378};
1379
1380struct dc_state_create_params {
1381 enum dc_power_source_type power_source;
1382};
1383
1384struct dc_commit_streams_params {
1385 struct dc_stream_state **streams;
1386 uint8_t stream_count;
1387 enum dc_power_source_type power_source;
1388};
1389
1390struct set_backlight_level_params {
1391 /* backlight in pwm */
1392 uint32_t backlight_pwm_u16_16;
1393 /* brightness ramping */
1394 uint32_t frame_ramp;
1395 /* backlight control type
1396 * 0: PWM backlight control
1397 * 1: VESA AUX backlight control
1398 * 2: AMD AUX backlight control
1399 */
1400 enum backlight_control_type control_type;
1401 /* backlight in millinits */
1402 uint32_t backlight_millinits;
1403 /* transition time in ms */
1404 uint32_t transition_time_in_ms;
1405 /* minimum luminance in nits */
1406 uint32_t min_luminance;
1407 /* maximum luminance in nits */
1408 uint32_t max_luminance;
1409 /* minimum backlight in pwm */
1410 uint32_t min_backlight_pwm;
1411 /* maximum backlight in pwm */
1412 uint32_t max_backlight_pwm;
1413 /* AUX HW instance */
1414 uint8_t aux_inst;
1415};
1416
1417enum dc_validate_mode {
1418 /* validate the mode and program HW */
1419 DC_VALIDATE_MODE_AND_PROGRAMMING = 0,
1420 /* only validate the mode */
1421 DC_VALIDATE_MODE_ONLY = 1,
1422 /* validate the mode and get the max state (voltage level) */
1423 DC_VALIDATE_MODE_AND_STATE_INDEX = 2,
1424};
1425
1426struct dc_validation_dpia_set {
1427 const struct dc_link *link;
1428 const struct dc_tunnel_settings *tunnel_settings;
1429 uint32_t required_bw;
1430};
1431
1432#endif /* DC_TYPES_H_ */
1433

source code of linux/drivers/gpu/drm/amd/display/dc/dc_types.h