1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_HDMI_TYPES_H
27#define DC_HDMI_TYPES_H
28
29#include "os_types.h"
30
31/* Address range from 0x00 to 0x1F.*/
32#define DP_ADAPTOR_TYPE2_SIZE 0x20
33#define DP_ADAPTOR_TYPE2_REG_ID 0x10
34#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
35/* Identifies adaptor as Dual-mode adaptor */
36#define DP_ADAPTOR_TYPE2_ID 0xA0
37/* MHz*/
38#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
39/* MHz*/
40#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
41/* kHZ*/
42#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
43/* kHZ*/
44#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 340000
45
46struct dp_hdmi_dongle_signature_data {
47 int8_t id[15];/* "DP-HDMI ADAPTOR"*/
48 uint8_t eot;/* end of transmition '\x4' */
49};
50
51/* DP-HDMI dongle slave address for retrieving dongle signature*/
52#define DP_HDMI_DONGLE_ADDRESS 0x40
53#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
54
55
56/* SCDC Address defines (HDMI 2.0)*/
57#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
58#define HDMI_SCDC_ADDRESS 0x54
59#define HDMI_SCDC_SINK_VERSION 0x01
60#define HDMI_SCDC_SOURCE_VERSION 0x02
61#define HDMI_SCDC_UPDATE_0 0x10
62#define HDMI_SCDC_TMDS_CONFIG 0x20
63#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
64#define HDMI_SCDC_CONFIG_0 0x30
65#define HDMI_SCDC_CONFIG_1 0x31
66#define HDMI_SCDC_SOURCE_TEST_REQ 0x35
67#define HDMI_SCDC_STATUS_FLAGS 0x40
68#define HDMI_SCDC_ERR_DETECT 0x50
69#define HDMI_SCDC_TEST_CONFIG 0xC0
70
71#define HDMI_SCDC_MANUFACTURER_OUI 0xD0
72#define HDMI_SCDC_DEVICE_ID 0xDB
73
74union hdmi_scdc_update_read_data {
75 uint8_t byte[2];
76 struct {
77 uint8_t STATUS_UPDATE:1;
78 uint8_t CED_UPDATE:1;
79 uint8_t RR_TEST:1;
80 uint8_t RESERVED:5;
81 uint8_t RESERVED2:8;
82 } fields;
83};
84
85union hdmi_scdc_status_flags_data {
86 uint8_t byte;
87 struct {
88 uint8_t CLOCK_DETECTED:1;
89 uint8_t CH0_LOCKED:1;
90 uint8_t CH1_LOCKED:1;
91 uint8_t CH2_LOCKED:1;
92 uint8_t RESERVED:4;
93 } fields;
94};
95
96union hdmi_scdc_ced_data {
97 uint8_t byte[11];
98 struct {
99 uint8_t CH0_8LOW:8;
100 uint8_t CH0_7HIGH:7;
101 uint8_t CH0_VALID:1;
102 uint8_t CH1_8LOW:8;
103 uint8_t CH1_7HIGH:7;
104 uint8_t CH1_VALID:1;
105 uint8_t CH2_8LOW:8;
106 uint8_t CH2_7HIGH:7;
107 uint8_t CH2_VALID:1;
108 uint8_t CHECKSUM:8;
109 uint8_t RESERVED:8;
110 uint8_t RESERVED2:8;
111 uint8_t RESERVED3:8;
112 uint8_t RESERVED4:4;
113 } fields;
114};
115
116union hdmi_scdc_manufacturer_OUI_data {
117 uint8_t byte[3];
118 struct {
119 uint8_t Manufacturer_OUI_1:8;
120 uint8_t Manufacturer_OUI_2:8;
121 uint8_t Manufacturer_OUI_3:8;
122 } fields;
123};
124
125union hdmi_scdc_device_id_data {
126 uint8_t byte;
127 struct {
128 uint8_t Hardware_Minor_Rev:4;
129 uint8_t Hardware_Major_Rev:4;
130 } fields;
131};
132
133#endif /* DC_HDMI_TYPES_H */
134

source code of linux/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h