1/*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_STREAM_H_
27#define DC_STREAM_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31
32/*******************************************************************************
33 * Stream Interfaces
34 ******************************************************************************/
35struct timing_sync_info {
36 int group_id;
37 int group_size;
38 bool master;
39};
40
41struct mall_stream_config {
42 /* MALL stream config to indicate if the stream is phantom or not.
43 * We will use a phantom stream to indicate that the pipe is phantom.
44 */
45 enum mall_stream_type type;
46 struct dc_stream_state *paired_stream; // master / slave stream
47 bool subvp_limit_cursor_size; /* stream has/is using subvp limiting hw cursor support */
48 bool cursor_size_limit_subvp; /* stream is using hw cursor config preventing subvp */
49};
50
51struct dc_stream_status {
52 int primary_otg_inst;
53 int stream_enc_inst;
54
55 /**
56 * @plane_count: Total of planes attached to a single stream
57 */
58 int plane_count;
59 int audio_inst;
60 struct timing_sync_info timing_sync_info;
61 struct dc_plane_state *plane_states[MAX_SURFACES];
62 bool is_abm_supported;
63 struct mall_stream_config mall_stream_config;
64 bool fpo_in_use;
65};
66
67enum hubp_dmdata_mode {
68 DMDATA_SW_MODE,
69 DMDATA_HW_MODE
70};
71
72struct dc_dmdata_attributes {
73 /* Specifies whether dynamic meta data will be updated by software
74 * or has to be fetched by hardware (DMA mode)
75 */
76 enum hubp_dmdata_mode dmdata_mode;
77 /* Specifies if current dynamic meta data is to be used only for the current frame */
78 bool dmdata_repeat;
79 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */
80 uint32_t dmdata_size;
81 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
82 bool dmdata_updated;
83 /* If hardware mode is used, the base address where DMDATA surface is located */
84 PHYSICAL_ADDRESS_LOC address;
85 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
86 bool dmdata_qos_mode;
87 /* If qos_mode = 1, this is the QOS value to be used: */
88 uint32_t dmdata_qos_level;
89 /* Specifies the value in unit of REFCLK cycles to be added to the
90 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
91 */
92 uint32_t dmdata_dl_delta;
93 /* An unbounded array of uint32s, represents software dmdata to be loaded */
94 uint32_t *dmdata_sw_data;
95};
96
97struct dc_writeback_info {
98 bool wb_enabled;
99 int dwb_pipe_inst;
100 struct dc_dwb_params dwb_params;
101 struct mcif_buf_params mcif_buf_params;
102 struct mcif_warmup_params mcif_warmup_params;
103 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
104 struct dc_plane_state *writeback_source_plane;
105 /* source MPCC instance. for use by internally by dc */
106 int mpcc_inst;
107};
108
109struct dc_writeback_update {
110 unsigned int num_wb_info;
111 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
112};
113
114enum vertical_interrupt_ref_point {
115 START_V_UPDATE = 0,
116 START_V_SYNC,
117 INVALID_POINT
118
119 //For now, only v_update interrupt is used.
120 //START_V_BLANK,
121 //START_V_ACTIVE
122};
123
124struct periodic_interrupt_config {
125 enum vertical_interrupt_ref_point ref_point;
126 int lines_offset;
127};
128
129struct dc_mst_stream_bw_update {
130 bool is_increase; // is bandwidth reduced or increased
131 uint32_t mst_stream_bw; // new mst bandwidth in kbps
132};
133
134union stream_update_flags {
135 struct {
136 uint32_t scaling:1;
137 uint32_t out_tf:1;
138 uint32_t out_csc:1;
139 uint32_t abm_level:1;
140 uint32_t dpms_off:1;
141 uint32_t gamut_remap:1;
142 uint32_t wb_update:1;
143 uint32_t dsc_changed : 1;
144 uint32_t mst_bw : 1;
145 uint32_t crtc_timing_adjust : 1;
146 uint32_t fams_changed : 1;
147 uint32_t scaler_sharpener : 1;
148 uint32_t sharpening_required : 1;
149 } bits;
150
151 uint32_t raw;
152};
153
154struct test_pattern {
155 enum dp_test_pattern type;
156 enum dp_test_pattern_color_space color_space;
157 struct link_training_settings const *p_link_settings;
158 unsigned char const *p_custom_pattern;
159 unsigned int cust_pattern_size;
160};
161
162#define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR)
163
164struct dc_stream_debug_options {
165 char force_odm_combine_segments;
166 /*
167 * When force_odm_combine_segments is non zero, allow dc to
168 * temporarily transition to ODM bypass when minimal transition state
169 * is required to prevent visual glitches showing on the screen
170 */
171 char allow_transition_for_forced_odm;
172};
173
174#define LUMINANCE_DATA_TABLE_SIZE 10
175
176struct luminance_data {
177 bool is_valid;
178 int refresh_rate_hz[LUMINANCE_DATA_TABLE_SIZE];
179 int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE];
180 int flicker_criteria_milli_nits_GAMING;
181 int flicker_criteria_milli_nits_STATIC;
182 int nominal_refresh_rate;
183 int dm_max_decrease_from_nominal;
184};
185
186struct dc_stream_state {
187 // sink is deprecated, new code should not reference
188 // this pointer
189 struct dc_sink *sink;
190
191 struct dc_link *link;
192 /* For dynamic link encoder assignment, update the link encoder assigned to
193 * a stream via the volatile dc_state rather than the static dc_link.
194 */
195 struct link_encoder *link_enc;
196 struct dc_stream_debug_options debug;
197 struct dc_panel_patch sink_patches;
198 struct dc_crtc_timing timing;
199 struct dc_crtc_timing_adjust adjust;
200 struct dc_info_packet vrr_infopacket;
201 struct dc_info_packet vsc_infopacket;
202 struct dc_info_packet vsp_infopacket;
203 struct dc_info_packet hfvsif_infopacket;
204 struct dc_info_packet vtem_infopacket;
205 struct dc_info_packet adaptive_sync_infopacket;
206 struct dc_info_packet avi_infopacket;
207 uint8_t dsc_packed_pps[128];
208 struct rect src; /* composition area */
209 struct rect dst; /* stream addressable area */
210
211 struct audio_info audio_info;
212
213 struct dc_info_packet hdr_static_metadata;
214 PHYSICAL_ADDRESS_LOC dmdata_address;
215 bool use_dynamic_meta;
216
217 struct dc_transfer_func out_transfer_func;
218 struct colorspace_transform gamut_remap_matrix;
219 struct dc_csc_transform csc_color_matrix;
220
221 enum dc_color_space output_color_space;
222 enum display_content_type content_type;
223 enum dc_dither_option dither_option;
224
225 enum view_3d_format view_format;
226
227 bool use_vsc_sdp_for_colorimetry;
228 bool ignore_msa_timing_param;
229
230 /**
231 * @allow_freesync:
232 *
233 * It say if Freesync is enabled or not.
234 */
235 bool allow_freesync;
236
237 /**
238 * @vrr_active_variable:
239 *
240 * It describes if VRR is in use.
241 */
242 bool vrr_active_variable;
243 bool freesync_on_desktop;
244 bool vrr_active_fixed;
245
246 bool converter_disable_audio;
247 uint8_t qs_bit;
248 uint8_t qy_bit;
249
250 /* TODO: custom INFO packets */
251 /* TODO: ABM info (DMCU) */
252 /* TODO: CEA VIC */
253
254 /* DMCU info */
255 unsigned int abm_level;
256
257 struct periodic_interrupt_config periodic_interrupt;
258
259 /* from core_stream struct */
260 struct dc_context *ctx;
261
262 /* used by DCP and FMT */
263 struct bit_depth_reduction_params bit_depth_params;
264 struct clamping_and_pixel_encoding_params clamping;
265
266 int phy_pix_clk;
267 enum signal_type signal;
268 bool dpms_off;
269
270 void *dm_stream_context;
271
272 struct dc_cursor_attributes cursor_attributes;
273 struct dc_cursor_position cursor_position;
274 bool hw_cursor_req;
275
276 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
277
278 /* from stream struct */
279 struct kref refcount;
280
281 struct crtc_trigger_info triggered_crtc_reset;
282
283 /* writeback */
284 unsigned int num_wb_info;
285 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
286 const struct dc_transfer_func *func_shaper;
287 const struct dc_3dlut *lut3d_func;
288 /* Computed state bits */
289 bool mode_changed : 1;
290
291 /* Output from DC when stream state is committed or altered
292 * DC may only access these values during:
293 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
294 * values may not change outside of those calls
295 */
296 struct {
297 // For interrupt management, some hardware instance
298 // offsets need to be exposed to DM
299 uint8_t otg_offset;
300 } out;
301
302 bool apply_edp_fast_boot_optimization;
303 bool apply_seamless_boot_optimization;
304 uint32_t apply_boot_odm_mode;
305
306 uint32_t stream_id;
307
308 struct test_pattern test_pattern;
309 union stream_update_flags update_flags;
310
311 bool has_non_synchronizable_pclk;
312 bool vblank_synchronized;
313 bool is_phantom;
314
315 struct luminance_data lumin_data;
316 bool scaler_sharpener_update;
317 bool sharpening_required;
318};
319
320#define ABM_LEVEL_IMMEDIATE_DISABLE 255
321
322struct dc_stream_update {
323 struct dc_stream_state *stream;
324
325 struct rect src;
326 struct rect dst;
327 struct dc_transfer_func *out_transfer_func;
328 struct dc_info_packet *hdr_static_metadata;
329 unsigned int *abm_level;
330
331 struct periodic_interrupt_config *periodic_interrupt;
332
333 struct dc_info_packet *vrr_infopacket;
334 struct dc_info_packet *vsc_infopacket;
335 struct dc_info_packet *vsp_infopacket;
336 struct dc_info_packet *hfvsif_infopacket;
337 struct dc_info_packet *vtem_infopacket;
338 struct dc_info_packet *adaptive_sync_infopacket;
339 struct dc_info_packet *avi_infopacket;
340
341 bool *dpms_off;
342 bool integer_scaling_update;
343 bool *allow_freesync;
344 bool *vrr_active_variable;
345 bool *vrr_active_fixed;
346
347 struct colorspace_transform *gamut_remap;
348 enum dc_color_space *output_color_space;
349 enum dc_dither_option *dither_option;
350
351 struct dc_csc_transform *output_csc_transform;
352
353 struct dc_writeback_update *wb_update;
354 struct dc_dsc_config *dsc_config;
355 struct dc_mst_stream_bw_update *mst_bw_update;
356 struct dc_transfer_func *func_shaper;
357 struct dc_3dlut *lut3d_func;
358
359 struct test_pattern *pending_test_pattern;
360 struct dc_crtc_timing_adjust *crtc_timing_adjust;
361
362 struct dc_cursor_attributes *cursor_attributes;
363 struct dc_cursor_position *cursor_position;
364 bool *hw_cursor_req;
365 bool *scaler_sharpener_update;
366 bool *sharpening_required;
367};
368
369bool dc_is_stream_unchanged(
370 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
371bool dc_is_stream_scaling_unchanged(
372 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
373
374/*
375 * Setup stream attributes if no stream updates are provided
376 * there will be no impact on the stream parameters
377 *
378 * Set up surface attributes and associate to a stream
379 * The surfaces parameter is an absolute set of all surface active for the stream.
380 * If no surfaces are provided, the stream will be blanked; no memory read.
381 * Any flip related attribute changes must be done through this interface.
382 *
383 * After this call:
384 * Surfaces attributes are programmed and configured to be composed into stream.
385 * This does not trigger a flip. No surface address is programmed.
386 *
387 */
388bool dc_update_planes_and_stream(struct dc *dc,
389 struct dc_surface_update *surface_updates, int surface_count,
390 struct dc_stream_state *dc_stream,
391 struct dc_stream_update *stream_update);
392
393/*
394 * Set up surface attributes and associate to a stream
395 * The surfaces parameter is an absolute set of all surface active for the stream.
396 * If no surfaces are provided, the stream will be blanked; no memory read.
397 * Any flip related attribute changes must be done through this interface.
398 *
399 * After this call:
400 * Surfaces attributes are programmed and configured to be composed into stream.
401 * This does not trigger a flip. No surface address is programmed.
402 */
403void dc_commit_updates_for_stream(struct dc *dc,
404 struct dc_surface_update *srf_updates,
405 int surface_count,
406 struct dc_stream_state *stream,
407 struct dc_stream_update *stream_update,
408 struct dc_state *state);
409/*
410 * Log the current stream state.
411 */
412void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
413
414uint8_t dc_get_current_stream_count(struct dc *dc);
415struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
416
417/*
418 * Return the current frame counter.
419 */
420uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
421
422/*
423 * Send dp sdp message.
424 */
425bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
426 const uint8_t *custom_sdp_message,
427 unsigned int sdp_message_size);
428
429/* TODO: Return parsed values rather than direct register read
430 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
431 * being refactored properly to be dce-specific
432 */
433bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
434 uint32_t *v_blank_start,
435 uint32_t *v_blank_end,
436 uint32_t *h_position,
437 uint32_t *v_position);
438
439bool dc_stream_add_writeback(struct dc *dc,
440 struct dc_stream_state *stream,
441 struct dc_writeback_info *wb_info);
442
443bool dc_stream_fc_disable_writeback(struct dc *dc,
444 struct dc_stream_state *stream,
445 uint32_t dwb_pipe_inst);
446
447bool dc_stream_remove_writeback(struct dc *dc,
448 struct dc_stream_state *stream,
449 uint32_t dwb_pipe_inst);
450
451enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
452 struct dc_state *state,
453 struct dc_stream_state *stream);
454
455bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
456
457bool dc_stream_set_dynamic_metadata(struct dc *dc,
458 struct dc_stream_state *stream,
459 struct dc_dmdata_attributes *dmdata_attr);
460
461enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
462
463/*
464 * Enable stereo when commit_streams is not required,
465 * for example, frame alternate.
466 */
467void dc_enable_stereo(
468 struct dc *dc,
469 struct dc_state *context,
470 struct dc_stream_state *streams[],
471 uint8_t stream_count);
472
473/* Triggers multi-stream synchronization. */
474void dc_trigger_sync(struct dc *dc, struct dc_state *context);
475
476struct surface_update_descriptor dc_check_update_surfaces_for_stream(
477 const struct dc_check_config *check_config,
478 struct dc_surface_update *updates,
479 int surface_count,
480 struct dc_stream_update *stream_update);
481
482/**
483 * Create a new default stream for the requested sink
484 */
485struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
486
487struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
488
489void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
490
491void dc_stream_retain(struct dc_stream_state *dc_stream);
492void dc_stream_release(struct dc_stream_state *dc_stream);
493
494struct dc_stream_status *dc_stream_get_status(struct dc_stream_state *dc_stream);
495const struct dc_stream_status *dc_stream_get_status_const(const struct dc_stream_state *dc_stream);
496
497/*******************************************************************************
498 * Cursor interfaces - To manages the cursor within a stream
499 ******************************************************************************/
500/* TODO: Deprecated once we switch to dc_set_cursor_position */
501
502void program_cursor_attributes(
503 struct dc *dc,
504 struct dc_stream_state *stream);
505
506void program_cursor_position(
507 struct dc *dc,
508 struct dc_stream_state *stream);
509
510bool dc_stream_check_cursor_attributes(
511 const struct dc_stream_state *stream,
512 struct dc_state *state,
513 const struct dc_cursor_attributes *attributes);
514
515bool dc_stream_set_cursor_attributes(
516 struct dc_stream_state *stream,
517 const struct dc_cursor_attributes *attributes);
518
519bool dc_stream_program_cursor_attributes(
520 struct dc_stream_state *stream,
521 const struct dc_cursor_attributes *attributes);
522
523bool dc_stream_set_cursor_position(
524 struct dc_stream_state *stream,
525 const struct dc_cursor_position *position);
526
527bool dc_stream_program_cursor_position(
528 struct dc_stream_state *stream,
529 const struct dc_cursor_position *position);
530
531
532bool dc_stream_adjust_vmin_vmax(struct dc *dc,
533 struct dc_stream_state *stream,
534 struct dc_crtc_timing_adjust *adjust);
535
536bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
537 struct dc_stream_state *stream,
538 uint32_t *refresh_rate);
539
540#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
541bool dc_stream_forward_crc_window(struct dc_stream_state *stream,
542 struct rect *rect,
543 uint8_t phy_id,
544 bool is_stop);
545
546bool dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream,
547 struct crc_window *window,
548 uint8_t phy_id,
549 bool stop);
550#endif
551
552bool dc_stream_configure_crc(struct dc *dc,
553 struct dc_stream_state *stream,
554 struct crc_params *crc_window,
555 bool enable,
556 bool continuous,
557 uint8_t idx,
558 bool reset);
559
560bool dc_stream_get_crc(struct dc *dc,
561 struct dc_stream_state *stream,
562 uint8_t idx,
563 uint32_t *r_cr,
564 uint32_t *g_y,
565 uint32_t *b_cb);
566
567void dc_stream_set_static_screen_params(struct dc *dc,
568 struct dc_stream_state **stream,
569 int num_streams,
570 const struct dc_static_screen_params *params);
571
572void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
573 enum dc_dynamic_expansion option);
574
575void dc_stream_set_dither_option(struct dc_stream_state *stream,
576 enum dc_dither_option option);
577
578bool dc_stream_set_gamut_remap(struct dc *dc,
579 const struct dc_stream_state *stream);
580
581bool dc_stream_program_csc_matrix(struct dc *dc,
582 struct dc_stream_state *stream);
583
584struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream(
585 const struct dc *dc,
586 const struct dc_stream_state *stream,
587 bool allocate_one);
588
589void dc_stream_release_3dlut_for_stream(
590 const struct dc *dc,
591 const struct dc_stream_state *stream);
592
593void dc_stream_init_rmcm_3dlut(struct dc *dc);
594
595struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
596
597void dc_dmub_update_dirty_rect(struct dc *dc,
598 int surface_count,
599 struct dc_stream_state *stream,
600 struct dc_surface_update *srf_updates,
601 struct dc_state *context);
602
603bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream);
604bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream);
605
606#endif /* DC_STREAM_H_ */
607

source code of linux/drivers/gpu/drm/amd/display/dc/dc_stream.h