1	/*
2	* Copyright 2012-2023 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	* Authors: AMD
23	*
24	*/
25
26	#ifndef DC_INTERFACE_H_
27	#define DC_INTERFACE_H_
28
29	#include "dc_types.h"
30	#include "dc_state.h"
31	#include "dc_plane.h"
32	#include "grph_object_defs.h"
33	#include "logger_types.h"
34	#include "hdcp_msg_types.h"
35	#include "gpio_types.h"
36	#include "link_service_types.h"
37	#include "grph_object_ctrl_defs.h"
38	#include <inc/hw/opp.h>
39
40	#include "hwss/hw_sequencer.h"
41	#include "inc/compressor.h"
42	#include "inc/hw/dmcu.h"
43	#include "dml/display_mode_lib.h"
44
45	#include "dml2_0/dml2_wrapper.h"
46
47	#include "dmub/inc/dmub_cmd.h"
48
49	#include "sspl/dc_spl_types.h"
50
51	struct abm_save_restore;
52
53	/* forward declaration */
54	struct aux_payload;
55	struct set_config_cmd_payload;
56	struct dmub_notification;
57	struct dcn_hubbub_reg_state;
58	struct dcn_hubp_reg_state;
59	struct dcn_dpp_reg_state;
60	struct dcn_mpc_reg_state;
61	struct dcn_opp_reg_state;
62	struct dcn_dsc_reg_state;
63	struct dcn_optc_reg_state;
64	struct dcn_dccg_reg_state;
65
66	#define DC_VER "3.2.359"
67
68	/**
69	* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
70	*/
71	#define MAX_SURFACES 4
72	/**
73	* MAX_PLANES - representative of the upper bound of planes that are supported by the HW
74	*/
75	#define MAX_PLANES 6
76	#define MAX_STREAMS 6
77	#define MIN_VIEWPORT_SIZE 12
78	#define MAX_NUM_EDP 2
79	#define MAX_SUPPORTED_FORMATS 7
80
81	#define MAX_HOST_ROUTERS_NUM 3
82	#define MAX_DPIA_PER_HOST_ROUTER 3
83	#define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER)
84
85	/* Display Core Interfaces */
86	struct dc_versions {
87	const char *dc_ver;
88	struct dmcu_version dmcu_version;
89	};
90
91	enum dp_protocol_version {
92	DP_VERSION_1_4 = 0,
93	DP_VERSION_2_1,
94	DP_VERSION_UNKNOWN,
95	};
96
97	enum dc_plane_type {
98	DC_PLANE_TYPE_INVALID,
99	DC_PLANE_TYPE_DCE_RGB,
100	DC_PLANE_TYPE_DCE_UNDERLAY,
101	DC_PLANE_TYPE_DCN_UNIVERSAL,
102	};
103
104	// Sizes defined as multiples of 64KB
105	enum det_size {
106	DET_SIZE_DEFAULT = 0,
107	DET_SIZE_192KB = 3,
108	DET_SIZE_256KB = 4,
109	DET_SIZE_320KB = 5,
110	DET_SIZE_384KB = 6
111	};
112
113
114	struct dc_plane_cap {
115	enum dc_plane_type type;
116	uint32_t per_pixel_alpha : 1;
117	struct {
118	uint32_t argb8888 : 1;
119	uint32_t nv12 : 1;
120	uint32_t fp16 : 1;
121	uint32_t p010 : 1;
122	uint32_t ayuv : 1;
123	} pixel_format_support;
124	// max upscaling factor x1000
125	// upscaling factors are always >= 1
126	// for example, 1080p -> 8K is 4.0, or 4000 raw value
127	struct {
128	uint32_t argb8888;
129	uint32_t nv12;
130	uint32_t fp16;
131	} max_upscale_factor;
132	// max downscale factor x1000
133	// downscale factors are always <= 1
134	// for example, 8K -> 1080p is 0.25, or 250 raw value
135	struct {
136	uint32_t argb8888;
137	uint32_t nv12;
138	uint32_t fp16;
139	} max_downscale_factor;
140	// minimal width/height
141	uint32_t min_width;
142	uint32_t min_height;
143	};
144
145	/**
146	* DOC: color-management-caps
147	*
148	* **Color management caps (DPP and MPC)**
149	*
150	* Modules/color calculates various color operations which are translated to
151	* abstracted HW. DCE 5-12 had almost no important changes, but starting with
152	* DCN1, every new generation comes with fairly major differences in color
153	* pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
154	* decide mapping to HW block based on logical capabilities.
155	*/
156
157	/**
158	* struct rom_curve_caps - predefined transfer function caps for degamma and regamma
159	* @srgb: RGB color space transfer func
160	* @bt2020: BT.2020 transfer func
161	* @gamma2_2: standard gamma
162	* @pq: perceptual quantizer transfer function
163	* @hlg: hybrid log–gamma transfer function
164	*/
165	struct rom_curve_caps {
166	uint16_t srgb : 1;
167	uint16_t bt2020 : 1;
168	uint16_t gamma2_2 : 1;
169	uint16_t pq : 1;
170	uint16_t hlg : 1;
171	};
172
173	/**
174	* struct dpp_color_caps - color pipeline capabilities for display pipe and
175	* plane blocks
176	*
177	* @dcn_arch: all DCE generations treated the same
178	* @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
179	* just plain 256-entry lookup
180	* @icsc: input color space conversion
181	* @dgam_ram: programmable degamma LUT
182	* @post_csc: post color space conversion, before gamut remap
183	* @gamma_corr: degamma correction
184	* @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
185	* with MPC by setting mpc:shared_3d_lut flag
186	* @ogam_ram: programmable out/blend gamma LUT
187	* @ocsc: output color space conversion
188	* @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
189	* @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
190	* @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
191	*
192	* Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
193	*/
194	struct dpp_color_caps {
195	uint16_t dcn_arch : 1;
196	uint16_t input_lut_shared : 1;
197	uint16_t icsc : 1;
198	uint16_t dgam_ram : 1;
199	uint16_t post_csc : 1;
200	uint16_t gamma_corr : 1;
201	uint16_t hw_3d_lut : 1;
202	uint16_t ogam_ram : 1;
203	uint16_t ocsc : 1;
204	uint16_t dgam_rom_for_yuv : 1;
205	struct rom_curve_caps dgam_rom_caps;
206	struct rom_curve_caps ogam_rom_caps;
207	};
208
209	/* Below structure is to describe the HW support for mem layout, extend support
210	range to match what OS could handle in the roadmap */
211	struct lut3d_caps {
212	uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */
213	struct {
214	uint32_t swizzle_3d_rgb : 1;
215	uint32_t swizzle_3d_bgr : 1;
216	uint32_t linear_1d : 1;
217	} mem_layout_support;
218	struct {
219	uint32_t unorm_12msb : 1;
220	uint32_t unorm_12lsb : 1;
221	uint32_t float_fp1_5_10 : 1;
222	} mem_format_support;
223	struct {
224	uint32_t order_rgba : 1;
225	uint32_t order_bgra : 1;
226	} mem_pixel_order_support;
227	/*< size options are 9, 17, 33, 45, 65 */
228	struct {
229	uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */
230	uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */
231	uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */
232	uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */
233	uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */
234	} lut_dim_caps;
235	};
236
237	/**
238	* struct mpc_color_caps - color pipeline capabilities for multiple pipe and
239	* plane combined blocks
240	*
241	* @gamut_remap: color transformation matrix
242	* @ogam_ram: programmable out gamma LUT
243	* @ocsc: output color space conversion matrix
244	* @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
245	* @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT
246	* @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
247	* instance
248	* @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
249	* @mcm_3d_lut_caps: HW support cap for MCM LUT memory
250	* @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory
251	* @preblend: whether color manager supports preblend with MPC
252	*/
253	struct mpc_color_caps {
254	uint16_t gamut_remap : 1;
255	uint16_t ogam_ram : 1;
256	uint16_t ocsc : 1;
257	uint16_t num_3dluts : 3;
258	uint16_t num_rmcm_3dluts : 3;
259	uint16_t shared_3d_lut:1;
260	struct rom_curve_caps ogam_rom_caps;
261	struct lut3d_caps mcm_3d_lut_caps;
262	struct lut3d_caps rmcm_3d_lut_caps;
263	bool preblend;
264	};
265
266	/**
267	* struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
268	* @dpp: color pipes caps for DPP
269	* @mpc: color pipes caps for MPC
270	*/
271	struct dc_color_caps {
272	struct dpp_color_caps dpp;
273	struct mpc_color_caps mpc;
274	};
275
276	struct dc_dmub_caps {
277	bool psr;
278	bool mclk_sw;
279	bool subvp_psr;
280	bool gecc_enable;
281	uint8_t fams_ver;
282	bool aux_backlight_support;
283	};
284
285	struct dc_scl_caps {
286	bool sharpener_support;
287	};
288
289	struct dc_check_config {
290	/**
291	* max video plane width that can be safely assumed to be always
292	* supported by single DPP pipe.
293	*/
294	unsigned int max_optimizable_video_width;
295	bool enable_legacy_fast_update;
296	};
297
298	struct dc_caps {
299	uint32_t max_streams;
300	uint32_t max_links;
301	uint32_t max_audios;
302	uint32_t max_slave_planes;
303	uint32_t max_slave_yuv_planes;
304	uint32_t max_slave_rgb_planes;
305	uint32_t max_planes;
306	uint32_t max_downscale_ratio;
307	uint32_t i2c_speed_in_khz;
308	uint32_t i2c_speed_in_khz_hdcp;
309	uint32_t dmdata_alloc_size;
310	unsigned int max_cursor_size;
311	unsigned int max_buffered_cursor_size;
312	unsigned int max_video_width;
313	unsigned int min_horizontal_blanking_period;
314	int linear_pitch_alignment;
315	bool dcc_const_color;
316	bool dynamic_audio;
317	bool is_apu;
318	bool dual_link_dvi;
319	bool post_blend_color_processing;
320	bool force_dp_tps4_for_cp2520;
321	bool disable_dp_clk_share;
322	bool psp_setup_panel_mode;
323	bool extended_aux_timeout_support;
324	bool dmcub_support;
325	bool zstate_support;
326	bool ips_support;
327	bool ips_v2_support;
328	uint32_t num_of_internal_disp;
329	enum dp_protocol_version max_dp_protocol_version;
330	unsigned int mall_size_per_mem_channel;
331	unsigned int mall_size_total;
332	unsigned int cursor_cache_size;
333	struct dc_plane_cap planes[MAX_PLANES];
334	struct dc_color_caps color;
335	struct dc_dmub_caps dmub_caps;
336	bool dp_hpo;
337	bool dp_hdmi21_pcon_support;
338	bool edp_dsc_support;
339	bool vbios_lttpr_aware;
340	bool vbios_lttpr_enable;
341	bool fused_io_supported;
342	uint32_t max_otg_num;
343	uint32_t max_cab_allocation_bytes;
344	uint32_t cache_line_size;
345	uint32_t cache_num_ways;
346	uint16_t subvp_fw_processing_delay_us;
347	uint8_t subvp_drr_max_vblank_margin_us;
348	uint16_t subvp_prefetch_end_to_mall_start_us;
349	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
350	uint16_t subvp_pstate_allow_width_us;
351	uint16_t subvp_vertical_int_margin_us;
352	bool seamless_odm;
353	uint32_t max_v_total;
354	bool vtotal_limited_by_fp2;
355	uint32_t max_disp_clock_khz_at_vmin;
356	uint8_t subvp_drr_vblank_start_margin_us;
357	bool cursor_not_scaled;
358	bool dcmode_power_limits_present;
359	bool sequential_ono;
360	/* Conservative limit for DCC cases which require ODM4:1 to support*/
361	uint32_t dcc_plane_width_limit;
362	struct dc_scl_caps scl_caps;
363	uint8_t num_of_host_routers;
364	uint8_t num_of_dpias_per_host_router;
365	/* limit of the ODM only, could be limited by other factors (like pipe count)*/
366	uint8_t max_odm_combine_factor;
367	};
368
369	struct dc_bug_wa {
370	bool no_connect_phy_config;
371	bool dedcn20_305_wa;
372	bool skip_clock_update;
373	bool lt_early_cr_pattern;
374	struct {
375	uint8_t uclk : 1;
376	uint8_t fclk : 1;
377	uint8_t dcfclk : 1;
378	uint8_t dcfclk_ds: 1;
379	} clock_update_disable_mask;
380	bool skip_psr_ips_crtc_disable;
381	};
382	struct dc_dcc_surface_param {
383	struct dc_size surface_size;
384	enum surface_pixel_format format;
385	unsigned int plane0_pitch;
386	struct dc_size plane1_size;
387	unsigned int plane1_pitch;
388	union {
389	enum swizzle_mode_values swizzle_mode;
390	enum swizzle_mode_addr3_values swizzle_mode_addr3;
391	};
392	enum dc_scan_direction scan;
393	};
394
395	struct dc_dcc_setting {
396	unsigned int max_compressed_blk_size;
397	unsigned int max_uncompressed_blk_size;
398	bool independent_64b_blks;
399	//These bitfields to be used starting with DCN 3.0
400	struct {
401	uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
402	uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
403	uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
404	uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
405	uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case)
406	uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x
407	uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case)
408	} dcc_controls;
409	};
410
411	struct dc_surface_dcc_cap {
412	union {
413	struct {
414	struct dc_dcc_setting rgb;
415	} grph;
416
417	struct {
418	struct dc_dcc_setting luma;
419	struct dc_dcc_setting chroma;
420	} video;
421	};
422
423	bool capable;
424	bool const_color_support;
425	};
426
427	struct dc_static_screen_params {
428	struct {
429	bool force_trigger;
430	bool cursor_update;
431	bool surface_update;
432	bool overlay_update;
433	} triggers;
434	unsigned int num_frames;
435	};
436
437
438	/* Surface update type is used by dc_update_surfaces_and_stream
439	* The update type is determined at the very beginning of the function based
440	* on parameters passed in and decides how much programming (or updating) is
441	* going to be done during the call.
442	*
443	* UPDATE_TYPE_FAST is used for really fast updates that do not require much
444	* logical calculations or hardware register programming. This update MUST be
445	* ISR safe on windows. Currently fast update will only be used to flip surface
446	* address.
447	*
448	* UPDATE_TYPE_MED is used for slower updates which require significant hw
449	* re-programming however do not affect bandwidth consumption or clock
450	* requirements. At present, this is the level at which front end updates
451	* that do not require us to run bw_calcs happen. These are in/out transfer func
452	* updates, viewport offset changes, recout size changes and pixel depth changes.
453	* This update can be done at ISR, but we want to minimize how often this happens.
454	*
455	* UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
456	* bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
457	* end related. Any time viewport dimensions, recout dimensions, scaling ratios or
458	* gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
459	* a full update. This cannot be done at ISR level and should be a rare event.
460	* Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
461	* underscan we don't expect to see this call at all.
462	*/
463
464	enum surface_update_type {
465	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
466	UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
467	UPDATE_TYPE_FULL, /* may need to shuffle resources */
468	};
469
470	enum dc_lock_descriptor {
471	LOCK_DESCRIPTOR_NONE = 0x0,
472	LOCK_DESCRIPTOR_STREAM = 0x1,
473	LOCK_DESCRIPTOR_LINK = 0x2,
474	LOCK_DESCRIPTOR_GLOBAL = 0x4,
475	};
476
477	struct surface_update_descriptor {
478	enum surface_update_type update_type;
479	enum dc_lock_descriptor lock_descriptor;
480	};
481
482	/* Forward declaration*/
483	struct dc;
484	struct dc_plane_state;
485	struct dc_state;
486
487	struct dc_cap_funcs {
488	bool (*get_dcc_compression_cap)(const struct dc *dc,
489	const struct dc_dcc_surface_param *input,
490	struct dc_surface_dcc_cap *output);
491	bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
492	};
493
494	struct link_training_settings;
495
496	union allow_lttpr_non_transparent_mode {
497	struct {
498	bool DP1_4A : 1;
499	bool DP2_0 : 1;
500	} bits;
501	unsigned char raw;
502	};
503
504	/* Structure to hold configuration flags set by dm at dc creation. */
505	struct dc_config {
506	bool gpu_vm_support;
507	bool disable_disp_pll_sharing;
508	bool fbc_support;
509	bool disable_fractional_pwm;
510	bool allow_seamless_boot_optimization;
511	bool seamless_boot_edp_requested;
512	bool edp_not_connected;
513	bool edp_no_power_sequencing;
514	bool force_enum_edp;
515	bool forced_clocks;
516	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
517	bool multi_mon_pp_mclk_switch;
518	bool disable_dmcu;
519	bool enable_4to1MPC;
520	bool enable_windowed_mpo_odm;
521	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
522	uint32_t allow_edp_hotplug_detection;
523	bool skip_riommu_prefetch_wa;
524	bool clamp_min_dcfclk;
525	uint64_t vblank_alignment_dto_params;
526	uint8_t vblank_alignment_max_frame_time_diff;
527	bool is_asymmetric_memory;
528	bool is_single_rank_dimm;
529	bool is_vmin_only_asic;
530	bool use_spl;
531	bool prefer_easf;
532	bool use_pipe_ctx_sync_logic;
533	int smart_mux_version;
534	bool ignore_dpref_ss;
535	bool enable_mipi_converter_optimization;
536	bool use_default_clock_table;
537	bool force_bios_enable_lttpr;
538	uint8_t force_bios_fixed_vs;
539	int sdpif_request_limit_words_per_umc;
540	bool dc_mode_clk_limit_support;
541	bool EnableMinDispClkODM;
542	bool enable_auto_dpm_test_logs;
543	unsigned int disable_ips;
544	unsigned int disable_ips_rcg;
545	unsigned int disable_ips_in_vpb;
546	bool disable_ips_in_dpms_off;
547	bool usb4_bw_alloc_support;
548	bool allow_0_dtb_clk;
549	bool use_assr_psp_message;
550	bool support_edp0_on_dp1;
551	unsigned int enable_fpo_flicker_detection;
552	bool disable_hbr_audio_dp2;
553	bool consolidated_dpia_dp_lt;
554	bool set_pipe_unlock_order;
555	bool enable_dpia_pre_training;
556	bool unify_link_enc_assignment;
557	bool enable_cursor_offload;
558	struct spl_sharpness_range dcn_sharpness_range;
559	struct spl_sharpness_range dcn_override_sharpness_range;
560	};
561
562	enum visual_confirm {
563	VISUAL_CONFIRM_DISABLE = 0,
564	VISUAL_CONFIRM_SURFACE = 1,
565	VISUAL_CONFIRM_HDR = 2,
566	VISUAL_CONFIRM_MPCTREE = 4,
567	VISUAL_CONFIRM_PSR = 5,
568	VISUAL_CONFIRM_SWAPCHAIN = 6,
569	VISUAL_CONFIRM_FAMS = 7,
570	VISUAL_CONFIRM_SWIZZLE = 9,
571	VISUAL_CONFIRM_SMARTMUX_DGPU = 10,
572	VISUAL_CONFIRM_REPLAY = 12,
573	VISUAL_CONFIRM_SUBVP = 14,
574	VISUAL_CONFIRM_MCLK_SWITCH = 16,
575	VISUAL_CONFIRM_FAMS2 = 19,
576	VISUAL_CONFIRM_HW_CURSOR = 20,
577	VISUAL_CONFIRM_VABC = 21,
578	VISUAL_CONFIRM_DCC = 22,
579	VISUAL_CONFIRM_EXPLICIT = 0x80000000,
580	};
581
582	enum dc_psr_power_opts {
583	psr_power_opt_invalid = 0x0,
584	psr_power_opt_smu_opt_static_screen = 0x1,
585	psr_power_opt_z10_static_screen = 0x10,
586	psr_power_opt_ds_disable_allow = 0x100,
587	};
588
589	enum dml_hostvm_override_opts {
590	DML_HOSTVM_NO_OVERRIDE = 0x0,
591	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
592	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
593	};
594
595	enum dc_replay_power_opts {
596	replay_power_opt_invalid = 0x0,
597	replay_power_opt_smu_opt_static_screen = 0x1,
598	replay_power_opt_z10_static_screen = 0x10,
599	};
600
601	enum dcc_option {
602	DCC_ENABLE = 0,
603	DCC_DISABLE = 1,
604	DCC_HALF_REQ_DISALBE = 2,
605	};
606
607	enum in_game_fams_config {
608	INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
609	INGAME_FAMS_DISABLE, // disable in-game fams
610	INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
611	INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies
612	};
613
614	/**
615	* enum pipe_split_policy - Pipe split strategy supported by DCN
616	*
617	* This enum is used to define the pipe split policy supported by DCN. By
618	* default, DC favors MPC_SPLIT_DYNAMIC.
619	*/
620	enum pipe_split_policy {
621	/**
622	* @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
623	* pipe in order to bring the best trade-off between performance and
624	* power consumption. This is the recommended option.
625	*/
626	MPC_SPLIT_DYNAMIC = 0,
627
628	/**
629	* @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
630	* try any sort of split optimization.
631	*/
632	MPC_SPLIT_AVOID = 1,
633
634	/**
635	* @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
636	* optimize the pipe utilization when using a single display; if the
637	* user connects to a second display, DC will avoid pipe split.
638	*/
639	MPC_SPLIT_AVOID_MULT_DISP = 2,
640	};
641
642	enum wm_report_mode {
643	WM_REPORT_DEFAULT = 0,
644	WM_REPORT_OVERRIDE = 1,
645	};
646	enum dtm_pstate{
647	dtm_level_p0 = 0,/*highest voltage*/
648	dtm_level_p1,
649	dtm_level_p2,
650	dtm_level_p3,
651	dtm_level_p4,/*when active_display_count = 0*/
652	};
653
654	enum dcn_pwr_state {
655	DCN_PWR_STATE_UNKNOWN = -1,
656	DCN_PWR_STATE_MISSION_MODE = 0,
657	DCN_PWR_STATE_LOW_POWER = 3,
658	};
659
660	enum dcn_zstate_support_state {
661	DCN_ZSTATE_SUPPORT_UNKNOWN,
662	DCN_ZSTATE_SUPPORT_ALLOW,
663	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
664	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
665	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
666	DCN_ZSTATE_SUPPORT_DISALLOW,
667	};
668
669	/*
670	* struct dc_clocks - DC pipe clocks
671	*
672	* For any clocks that may differ per pipe only the max is stored in this
673	* structure
674	*/
675	struct dc_clocks {
676	int dispclk_khz;
677	int actual_dispclk_khz;
678	int dppclk_khz;
679	int actual_dppclk_khz;
680	int disp_dpp_voltage_level_khz;
681	int dcfclk_khz;
682	int socclk_khz;
683	int dcfclk_deep_sleep_khz;
684	int fclk_khz;
685	int phyclk_khz;
686	int dramclk_khz;
687	bool p_state_change_support;
688	enum dcn_zstate_support_state zstate_support;
689	bool dtbclk_en;
690	int ref_dtbclk_khz;
691	bool fclk_p_state_change_support;
692	enum dcn_pwr_state pwr_state;
693	/*
694	* Elements below are not compared for the purposes of
695	* optimization required
696	*/
697	bool prev_p_state_change_support;
698	bool fclk_prev_p_state_change_support;
699	int num_ways;
700	int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];
701
702	/*
703	* @fw_based_mclk_switching
704	*
705	* DC has a mechanism that leverage the variable refresh rate to switch
706	* memory clock in cases that we have a large latency to achieve the
707	* memory clock change and a short vblank window. DC has some
708	* requirements to enable this feature, and this field describes if the
709	* system support or not such a feature.
710	*/
711	bool fw_based_mclk_switching;
712	bool fw_based_mclk_switching_shut_down;
713	int prev_num_ways;
714	enum dtm_pstate dtm_level;
715	int max_supported_dppclk_khz;
716	int max_supported_dispclk_khz;
717	int bw_dppclk_khz; /*a copy of dppclk_khz*/
718	int bw_dispclk_khz;
719	int idle_dramclk_khz;
720	int idle_fclk_khz;
721	int subvp_prefetch_dramclk_khz;
722	int subvp_prefetch_fclk_khz;
723
724	/* Stutter efficiency is technically not clock values
725	* but stored here so the values are part of the update_clocks call similar to num_ways
726	* Efficiencies are stored as percentage (0-100)
727	*/
728	struct {
729	uint8_t base_efficiency; //LP1
730	uint8_t low_power_efficiency; //LP2
731	} stutter_efficiency;
732	};
733
734	struct dc_bw_validation_profile {
735	bool enable;
736
737	unsigned long long total_ticks;
738	unsigned long long voltage_level_ticks;
739	unsigned long long watermark_ticks;
740	unsigned long long rq_dlg_ticks;
741
742	unsigned long long total_count;
743	unsigned long long skip_fast_count;
744	unsigned long long skip_pass_count;
745	unsigned long long skip_fail_count;
746	};
747
748	#define BW_VAL_TRACE_SETUP() \
749	unsigned long long end_tick = 0; \
750	unsigned long long voltage_level_tick = 0; \
751	unsigned long long watermark_tick = 0; \
752	unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
753	dm_get_timestamp(dc->ctx) : 0
754
755	#define BW_VAL_TRACE_COUNT() \
756	if (dc->debug.bw_val_profile.enable) \
757	dc->debug.bw_val_profile.total_count++
758
759	#define BW_VAL_TRACE_SKIP(status) \
760	if (dc->debug.bw_val_profile.enable) { \
761	if (!voltage_level_tick) \
762	voltage_level_tick = dm_get_timestamp(dc->ctx); \
763	dc->debug.bw_val_profile.skip_ ## status ## _count++; \
764	}
765
766	#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
767	if (dc->debug.bw_val_profile.enable) \
768	voltage_level_tick = dm_get_timestamp(dc->ctx)
769
770	#define BW_VAL_TRACE_END_WATERMARKS() \
771	if (dc->debug.bw_val_profile.enable) \
772	watermark_tick = dm_get_timestamp(dc->ctx)
773
774	#define BW_VAL_TRACE_FINISH() \
775	if (dc->debug.bw_val_profile.enable) { \
776	end_tick = dm_get_timestamp(dc->ctx); \
777	dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
778	dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
779	if (watermark_tick) { \
780	dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
781	dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
782	} \
783	}
784
785	union mem_low_power_enable_options {
786	struct {
787	bool vga: 1;
788	bool i2c: 1;
789	bool dmcu: 1;
790	bool dscl: 1;
791	bool cm: 1;
792	bool mpc: 1;
793	bool optc: 1;
794	bool vpg: 1;
795	bool afmt: 1;
796	} bits;
797	uint32_t u32All;
798	};
799
800	union root_clock_optimization_options {
801	struct {
802	bool dpp: 1;
803	bool dsc: 1;
804	bool hdmistream: 1;
805	bool hdmichar: 1;
806	bool dpstream: 1;
807	bool symclk32_se: 1;
808	bool symclk32_le: 1;
809	bool symclk_fe: 1;
810	bool physymclk: 1;
811	bool dpiasymclk: 1;
812	uint32_t reserved: 22;
813	} bits;
814	uint32_t u32All;
815	};
816
817	union fine_grain_clock_gating_enable_options {
818	struct {
819	bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
820	bool dchub : 1; /* Display controller hub */
821	bool dchubbub : 1;
822	bool dpp : 1; /* Display pipes and planes */
823	bool opp : 1; /* Output pixel processing */
824	bool optc : 1; /* Output pipe timing combiner */
825	bool dio : 1; /* Display output */
826	bool dwb : 1; /* Display writeback */
827	bool mmhubbub : 1; /* Multimedia hub */
828	bool dmu : 1; /* Display core management unit */
829	bool az : 1; /* Azalia */
830	bool dchvm : 1;
831	bool dsc : 1; /* Display stream compression */
832
833	uint32_t reserved : 19;
834	} bits;
835	uint32_t u32All;
836	};
837
838	enum pg_hw_pipe_resources {
839	PG_HUBP = 0,
840	PG_DPP,
841	PG_DSC,
842	PG_MPCC,
843	PG_OPP,
844	PG_OPTC,
845	PG_DPSTREAM,
846	PG_HDMISTREAM,
847	PG_PHYSYMCLK,
848	PG_HW_PIPE_RESOURCES_NUM_ELEMENT
849	};
850
851	enum pg_hw_resources {
852	PG_DCCG = 0,
853	PG_DCIO,
854	PG_DIO,
855	PG_DCHUBBUB,
856	PG_DCHVM,
857	PG_DWB,
858	PG_HPO,
859	PG_DCOH,
860	PG_HW_RESOURCES_NUM_ELEMENT
861	};
862
863	struct pg_block_update {
864	bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
865	bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
866	};
867
868	union dpia_debug_options {
869	struct {
870	uint32_t disable_dpia:1; /* bit 0 */
871	uint32_t force_non_lttpr:1; /* bit 1 */
872	uint32_t extend_aux_rd_interval:1; /* bit 2 */
873	uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
874	uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
875	uint32_t disable_usb4_pm_support:1; /* bit 5 */
876	uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */
877	uint32_t reserved:25;
878	} bits;
879	uint32_t raw;
880	};
881
882	/* AUX wake work around options
883	* 0: enable/disable work around
884	* 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
885	* 15-2: reserved
886	* 31-16: timeout in ms
887	*/
888	union aux_wake_wa_options {
889	struct {
890	uint32_t enable_wa : 1;
891	uint32_t use_default_timeout : 1;
892	uint32_t rsvd: 14;
893	uint32_t timeout_ms : 16;
894	} bits;
895	uint32_t raw;
896	};
897
898	struct dc_debug_data {
899	uint32_t ltFailCount;
900	uint32_t i2cErrorCount;
901	uint32_t auxErrorCount;
902	struct pipe_topology_history topology_history;
903	};
904
905	struct dc_phy_addr_space_config {
906	struct {
907	uint64_t start_addr;
908	uint64_t end_addr;
909	uint64_t fb_top;
910	uint64_t fb_offset;
911	uint64_t fb_base;
912	uint64_t agp_top;
913	uint64_t agp_bot;
914	uint64_t agp_base;
915	} system_aperture;
916
917	struct {
918	uint64_t page_table_start_addr;
919	uint64_t page_table_end_addr;
920	uint64_t page_table_base_addr;
921	bool base_addr_is_mc_addr;
922	} gart_config;
923
924	bool valid;
925	bool is_hvm_enabled;
926	uint64_t page_table_default_page_addr;
927	};
928
929	struct dc_virtual_addr_space_config {
930	uint64_t page_table_base_addr;
931	uint64_t page_table_start_addr;
932	uint64_t page_table_end_addr;
933	uint32_t page_table_block_size_in_bytes;
934	uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
935	};
936
937	struct dc_bounding_box_overrides {
938	int sr_exit_time_ns;
939	int sr_enter_plus_exit_time_ns;
940	int sr_exit_z8_time_ns;
941	int sr_enter_plus_exit_z8_time_ns;
942	int urgent_latency_ns;
943	int percent_of_ideal_drambw;
944	int dram_clock_change_latency_ns;
945	int dummy_clock_change_latency_ns;
946	int fclk_clock_change_latency_ns;
947	/* This forces a hard min on the DCFCLK we use
948	* for DML. Unlike the debug option for forcing
949	* DCFCLK, this override affects watermark calculations
950	*/
951	int min_dcfclk_mhz;
952	};
953
954	struct dc_state;
955	struct resource_pool;
956	struct dce_hwseq;
957	struct link_service;
958
959	/*
960	* struct dc_debug_options - DC debug struct
961	*
962	* This struct provides a simple mechanism for developers to change some
963	* configurations, enable/disable features, and activate extra debug options.
964	* This can be very handy to narrow down whether some specific feature is
965	* causing an issue or not.
966	*/
967	struct dc_debug_options {
968	bool native422_support;
969	bool disable_dsc;
970	enum visual_confirm visual_confirm;
971	int visual_confirm_rect_height;
972
973	bool sanity_checks;
974	bool max_disp_clk;
975	bool surface_trace;
976	bool clock_trace;
977	bool validation_trace;
978	bool bandwidth_calcs_trace;
979	int max_downscale_src_width;
980
981	/* stutter efficiency related */
982	bool disable_stutter;
983	bool use_max_lb;
984	enum dcc_option disable_dcc;
985
986	/*
987	* @pipe_split_policy: Define which pipe split policy is used by the
988	* display core.
989	*/
990	enum pipe_split_policy pipe_split_policy;
991	bool force_single_disp_pipe_split;
992	bool voltage_align_fclk;
993	bool disable_min_fclk;
994
995	bool hdcp_lc_force_fw_enable;
996	bool hdcp_lc_enable_sw_fallback;
997
998	bool disable_dfs_bypass;
999	bool disable_dpp_power_gate;
1000	bool disable_hubp_power_gate;
1001	bool disable_dsc_power_gate;
1002	bool disable_optc_power_gate;
1003	bool disable_hpo_power_gate;
1004	bool disable_io_clk_power_gate;
1005	bool disable_mem_power_gate;
1006	bool disable_dio_power_gate;
1007	int dsc_min_slice_height_override;
1008	int dsc_bpp_increment_div;
1009	bool disable_pplib_wm_range;
1010	enum wm_report_mode pplib_wm_report_mode;
1011	unsigned int min_disp_clk_khz;
1012	unsigned int min_dpp_clk_khz;
1013	unsigned int min_dram_clk_khz;
1014	int sr_exit_time_dpm0_ns;
1015	int sr_enter_plus_exit_time_dpm0_ns;
1016	int sr_exit_time_ns;
1017	int sr_enter_plus_exit_time_ns;
1018	int sr_exit_z8_time_ns;
1019	int sr_enter_plus_exit_z8_time_ns;
1020	int urgent_latency_ns;
1021	uint32_t underflow_assert_delay_us;
1022	int percent_of_ideal_drambw;
1023	int dram_clock_change_latency_ns;
1024	bool optimized_watermark;
1025	int always_scale;
1026	bool disable_pplib_clock_request;
1027	bool disable_clock_gate;
1028	bool disable_mem_low_power;
1029	bool pstate_enabled;
1030	bool disable_dmcu;
1031	bool force_abm_enable;
1032	bool disable_stereo_support;
1033	bool vsr_support;
1034	bool performance_trace;
1035	bool az_endpoint_mute_only;
1036	bool always_use_regamma;
1037	bool recovery_enabled;
1038	bool avoid_vbios_exec_table;
1039	bool scl_reset_length10;
1040	bool hdmi20_disable;
1041	bool skip_detection_link_training;
1042	uint32_t edid_read_retry_times;
1043	unsigned int force_odm_combine; //bit vector based on otg inst
1044	unsigned int seamless_boot_odm_combine;
1045	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
1046	int minimum_z8_residency_time;
1047	int minimum_z10_residency_time;
1048	bool disable_z9_mpc;
1049	unsigned int force_fclk_khz;
1050	bool enable_tri_buf;
1051	bool ips_disallow_entry;
1052	bool dmub_offload_enabled;
1053	bool dmcub_emulation;
1054	bool disable_idle_power_optimizations;
1055	unsigned int mall_size_override;
1056	unsigned int mall_additional_timer_percent;
1057	bool mall_error_as_fatal;
1058	bool dmub_command_table; /* for testing only */
1059	struct dc_bw_validation_profile bw_val_profile;
1060	bool disable_fec;
1061	bool disable_48mhz_pwrdwn;
1062	/* This forces a hard min on the DCFCLK requested to SMU/PP
1063	* watermarks are not affected.
1064	*/
1065	unsigned int force_min_dcfclk_mhz;
1066	int dwb_fi_phase;
1067	bool disable_timing_sync;
1068	bool cm_in_bypass;
1069	int force_clock_mode;/*every mode change.*/
1070
1071	bool disable_dram_clock_change_vactive_support;
1072	bool validate_dml_output;
1073	bool enable_dmcub_surface_flip;
1074	bool usbc_combo_phy_reset_wa;
1075	bool enable_dram_clock_change_one_display_vactive;
1076	/* TODO - remove once tested */
1077	bool legacy_dp2_lt;
1078	bool set_mst_en_for_sst;
1079	bool disable_uhbr;
1080	bool force_dp2_lt_fallback_method;
1081	bool ignore_cable_id;
1082	union mem_low_power_enable_options enable_mem_low_power;
1083	union root_clock_optimization_options root_clock_optimization;
1084	union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
1085	bool hpo_optimization;
1086	bool force_vblank_alignment;
1087
1088	/* Enable dmub aux for legacy ddc */
1089	bool enable_dmub_aux_for_legacy_ddc;
1090	bool disable_fams;
1091	enum in_game_fams_config disable_fams_gaming;
1092	/* FEC/PSR1 sequence enable delay in 100us */
1093	uint8_t fec_enable_delay_in100us;
1094	bool enable_driver_sequence_debug;
1095	enum det_size crb_alloc_policy;
1096	int crb_alloc_policy_min_disp_count;
1097	bool disable_z10;
1098	bool enable_z9_disable_interface;
1099	bool psr_skip_crtc_disable;
1100	uint32_t ips_skip_crtc_disable_mask;
1101	union dpia_debug_options dpia_debug;
1102	bool disable_fixed_vs_aux_timeout_wa;
1103	uint32_t fixed_vs_aux_delay_config_wa;
1104	bool force_disable_subvp;
1105	bool force_subvp_mclk_switch;
1106	bool allow_sw_cursor_fallback;
1107	unsigned int force_subvp_num_ways;
1108	unsigned int force_mall_ss_num_ways;
1109	bool alloc_extra_way_for_cursor;
1110	uint32_t subvp_extra_lines;
1111	bool disable_force_pstate_allow_on_hw_release;
1112	bool force_usr_allow;
1113	/* uses value at boot and disables switch */
1114	bool disable_dtb_ref_clk_switch;
1115	bool extended_blank_optimization;
1116	union aux_wake_wa_options aux_wake_wa;
1117	uint32_t mst_start_top_delay;
1118	uint8_t psr_power_use_phy_fsm;
1119	enum dml_hostvm_override_opts dml_hostvm_override;
1120	bool dml_disallow_alternate_prefetch_modes;
1121	bool use_legacy_soc_bb_mechanism;
1122	bool exit_idle_opt_for_cursor_updates;
1123	bool using_dml2;
1124	bool enable_single_display_2to1_odm_policy;
1125	bool enable_double_buffered_dsc_pg_support;
1126	bool enable_dp_dig_pixel_rate_div_policy;
1127	bool using_dml21;
1128	enum lttpr_mode lttpr_mode_override;
1129	unsigned int dsc_delay_factor_wa_x1000;
1130	unsigned int min_prefetch_in_strobe_ns;
1131	bool disable_unbounded_requesting;
1132	bool dig_fifo_off_in_blank;
1133	bool override_dispclk_programming;
1134	bool otg_crc_db;
1135	bool disallow_dispclk_dppclk_ds;
1136	bool disable_fpo_optimizations;
1137	bool support_eDP1_5;
1138	uint32_t fpo_vactive_margin_us;
1139	bool disable_fpo_vactive;
1140	bool disable_boot_optimizations;
1141	bool override_odm_optimization;
1142	bool minimize_dispclk_using_odm;
1143	bool disable_subvp_high_refresh;
1144	bool disable_dp_plus_plus_wa;
1145	uint32_t fpo_vactive_min_active_margin_us;
1146	uint32_t fpo_vactive_max_blank_us;
1147	bool enable_hpo_pg_support;
1148	bool disable_dc_mode_overwrite;
1149	bool replay_skip_crtc_disabled;
1150	bool ignore_pg;/*do nothing, let pmfw control it*/
1151	bool psp_disabled_wa;
1152	unsigned int ips2_eval_delay_us;
1153	unsigned int ips2_entry_delay_us;
1154	bool optimize_ips_handshake;
1155	bool disable_dmub_reallow_idle;
1156	bool disable_timeout;
1157	bool disable_extblankadj;
1158	bool enable_idle_reg_checks;
1159	unsigned int static_screen_wait_frames;
1160	uint32_t pwm_freq;
1161	bool force_chroma_subsampling_1tap;
1162	unsigned int dcc_meta_propagation_delay_us;
1163	bool disable_422_left_edge_pixel;
1164	bool dml21_force_pstate_method;
1165	uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1166	uint32_t dml21_disable_pstate_method_mask;
1167	union fw_assisted_mclk_switch_version fams_version;
1168	union dmub_fams2_global_feature_config fams2_config;
1169	unsigned int force_cositing;
1170	unsigned int disable_spl;
1171	unsigned int force_easf;
1172	unsigned int force_sharpness;
1173	unsigned int force_sharpness_level;
1174	unsigned int force_lls;
1175	bool notify_dpia_hr_bw;
1176	bool enable_ips_visual_confirm;
1177	unsigned int sharpen_policy;
1178	unsigned int scale_to_sharpness_policy;
1179	unsigned int enable_oled_edp_power_up_opt;
1180	bool enable_hblank_borrow;
1181	bool force_subvp_df_throttle;
1182	uint32_t acpi_transition_bitmasks[MAX_PIPES];
1183	bool enable_pg_cntl_debug_logs;
1184	unsigned int auxless_alpm_lfps_setup_ns;
1185	unsigned int auxless_alpm_lfps_period_ns;
1186	unsigned int auxless_alpm_lfps_silence_ns;
1187	unsigned int auxless_alpm_lfps_t1t2_us;
1188	short auxless_alpm_lfps_t1t2_offset_us;
1189	bool disable_stutter_for_wm_program;
1190	bool enable_block_sequence_programming;
1191	};
1192
1193
1194	/* Generic structure that can be used to query properties of DC. More fields
1195	* can be added as required.
1196	*/
1197	struct dc_current_properties {
1198	unsigned int cursor_size_limit;
1199	};
1200
1201	enum frame_buffer_mode {
1202	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1203	FRAME_BUFFER_MODE_ZFB_ONLY,
1204	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1205	} ;
1206
1207	struct dchub_init_data {
1208	int64_t zfb_phys_addr_base;
1209	int64_t zfb_mc_base_addr;
1210	uint64_t zfb_size_in_byte;
1211	enum frame_buffer_mode fb_mode;
1212	bool dchub_initialzied;
1213	bool dchub_info_valid;
1214	};
1215
1216	struct dml2_soc_bb;
1217
1218	struct dc_init_data {
1219	struct hw_asic_id asic_id;
1220	void *driver; /* ctx */
1221	struct cgs_device *cgs_device;
1222	struct dc_bounding_box_overrides bb_overrides;
1223
1224	int num_virtual_links;
1225	/*
1226	* If 'vbios_override' not NULL, it will be called instead
1227	* of the real VBIOS. Intended use is Diagnostics on FPGA.
1228	*/
1229	struct dc_bios *vbios_override;
1230	enum dce_environment dce_environment;
1231
1232	struct dmub_offload_funcs *dmub_if;
1233	struct dc_reg_helper_state *dmub_offload;
1234
1235	struct dc_config flags;
1236	uint64_t log_mask;
1237
1238	struct dpcd_vendor_signature vendor_signature;
1239	bool force_smu_not_present;
1240	/*
1241	* IP offset for run time initializaion of register addresses
1242	*
1243	* DCN3.5+ will fail dc_create() if these fields are null for them. They are
1244	* applicable starting with DCN32/321 and are not used for ASICs upstreamed
1245	* before them.
1246	*/
1247	uint32_t *dcn_reg_offsets;
1248	uint32_t *nbio_reg_offsets;
1249	uint32_t *clk_reg_offsets;
1250	void *bb_from_dmub;
1251	};
1252
1253	struct dc_callback_init {
1254	struct cp_psp cp_psp;
1255	};
1256
1257	struct dc *dc_create(const struct dc_init_data *init_params);
1258	void dc_hardware_init(struct dc *dc);
1259
1260	int dc_get_vmid_use_vector(struct dc *dc);
1261	void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1262	/* Returns the number of vmids supported */
1263	int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1264	void dc_init_callbacks(struct dc *dc,
1265	const struct dc_callback_init *init_params);
1266	void dc_deinit_callbacks(struct dc *dc);
1267	void dc_destroy(struct dc **dc);
1268
1269	/* Surface Interfaces */
1270
1271	enum {
1272	TRANSFER_FUNC_POINTS = 1025
1273	};
1274
1275	struct dc_hdr_static_metadata {
1276	/* display chromaticities and white point in units of 0.00001 */
1277	unsigned int chromaticity_green_x;
1278	unsigned int chromaticity_green_y;
1279	unsigned int chromaticity_blue_x;
1280	unsigned int chromaticity_blue_y;
1281	unsigned int chromaticity_red_x;
1282	unsigned int chromaticity_red_y;
1283	unsigned int chromaticity_white_point_x;
1284	unsigned int chromaticity_white_point_y;
1285
1286	uint32_t min_luminance;
1287	uint32_t max_luminance;
1288	uint32_t maximum_content_light_level;
1289	uint32_t maximum_frame_average_light_level;
1290	};
1291
1292	enum dc_transfer_func_type {
1293	TF_TYPE_PREDEFINED,
1294	TF_TYPE_DISTRIBUTED_POINTS,
1295	TF_TYPE_BYPASS,
1296	TF_TYPE_HWPWL
1297	};
1298
1299	struct dc_transfer_func_distributed_points {
1300	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1301	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1302	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1303
1304	uint16_t end_exponent;
1305	uint16_t x_point_at_y1_red;
1306	uint16_t x_point_at_y1_green;
1307	uint16_t x_point_at_y1_blue;
1308	};
1309
1310	enum dc_transfer_func_predefined {
1311	TRANSFER_FUNCTION_SRGB,
1312	TRANSFER_FUNCTION_BT709,
1313	TRANSFER_FUNCTION_PQ,
1314	TRANSFER_FUNCTION_LINEAR,
1315	TRANSFER_FUNCTION_UNITY,
1316	TRANSFER_FUNCTION_HLG,
1317	TRANSFER_FUNCTION_HLG12,
1318	TRANSFER_FUNCTION_GAMMA22,
1319	TRANSFER_FUNCTION_GAMMA24,
1320	TRANSFER_FUNCTION_GAMMA26
1321	};
1322
1323
1324	struct dc_transfer_func {
1325	struct kref refcount;
1326	enum dc_transfer_func_type type;
1327	enum dc_transfer_func_predefined tf;
1328	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1329	uint32_t sdr_ref_white_level;
1330	union {
1331	struct pwl_params pwl;
1332	struct dc_transfer_func_distributed_points tf_pts;
1333	};
1334	};
1335
1336
1337	union dc_3dlut_state {
1338	struct {
1339	uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1340	uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1341	uint32_t rmu_mux_num:3; /*index of mux to use*/
1342	uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1343	uint32_t mpc_rmu1_mux:4;
1344	uint32_t mpc_rmu2_mux:4;
1345	uint32_t reserved:15;
1346	} bits;
1347	uint32_t raw;
1348	};
1349
1350
1351	#define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0
1352	#define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0
1353	#define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0
1354
1355	struct lut_rgb {
1356	uint16_t b;
1357	uint16_t g;
1358	uint16_t r;
1359	uint16_t padding;
1360	};
1361
1362	//this structure maps directly to how the lut will read it from memory
1363	struct lut_mem_mapping {
1364	union {
1365	//NATIVE MODE 1, 2
1366	//RGB layout [b][g][r] //red is 128 byte aligned
1367	//BGR layout [r][g][b] //blue is 128 byte aligned
1368	struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN];
1369	struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN];
1370
1371	//TRANSFORMED
1372	uint16_t linear_rgb[(33*33*33*4/128+1)*128];
1373	};
1374	uint16_t size;
1375	};
1376
1377	struct dc_rmcm_3dlut {
1378	bool isInUse;
1379	const struct dc_stream_state *stream;
1380	uint8_t protection_bits;
1381	};
1382
1383	struct dc_3dlut {
1384	struct kref refcount;
1385	struct tetrahedral_params lut_3d;
1386	struct fixed31_32 hdr_multiplier;
1387	union dc_3dlut_state state;
1388	};
1389	/*
1390	* This structure is filled in by dc_surface_get_status and contains
1391	* the last requested address and the currently active address so the called
1392	* can determine if there are any outstanding flips
1393	*/
1394	struct dc_plane_status {
1395	struct dc_plane_address requested_address;
1396	struct dc_plane_address current_address;
1397	bool is_flip_pending;
1398	bool is_right_eye;
1399	};
1400
1401	union surface_update_flags {
1402
1403	struct {
1404	uint32_t addr_update:1;
1405	/* Medium updates */
1406	uint32_t dcc_change:1;
1407	uint32_t color_space_change:1;
1408	uint32_t horizontal_mirror_change:1;
1409	uint32_t per_pixel_alpha_change:1;
1410	uint32_t global_alpha_change:1;
1411	uint32_t hdr_mult:1;
1412	uint32_t rotation_change:1;
1413	uint32_t swizzle_change:1;
1414	uint32_t scaling_change:1;
1415	uint32_t position_change:1;
1416	uint32_t in_transfer_func_change:1;
1417	uint32_t input_csc_change:1;
1418	uint32_t coeff_reduction_change:1;
1419	uint32_t pixel_format_change:1;
1420	uint32_t plane_size_change:1;
1421	uint32_t gamut_remap_change:1;
1422
1423	/* Full updates */
1424	uint32_t new_plane:1;
1425	uint32_t bpp_change:1;
1426	uint32_t gamma_change:1;
1427	uint32_t bandwidth_change:1;
1428	uint32_t clock_change:1;
1429	uint32_t stereo_format_change:1;
1430	uint32_t lut_3d:1;
1431	uint32_t tmz_changed:1;
1432	uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
1433	uint32_t full_update:1;
1434	uint32_t sdr_white_level_nits:1;
1435	} bits;
1436
1437	uint32_t raw;
1438	};
1439
1440	#define DC_REMOVE_PLANE_POINTERS 1
1441
1442	struct dc_plane_state {
1443	struct dc_plane_address address;
1444	struct dc_plane_flip_time time;
1445	bool triplebuffer_flips;
1446	struct scaling_taps scaling_quality;
1447	struct rect src_rect;
1448	struct rect dst_rect;
1449	struct rect clip_rect;
1450
1451	struct plane_size plane_size;
1452	struct dc_tiling_info tiling_info;
1453
1454	struct dc_plane_dcc_param dcc;
1455
1456	struct dc_gamma gamma_correction;
1457	struct dc_transfer_func in_transfer_func;
1458	struct dc_bias_and_scale bias_and_scale;
1459	struct dc_csc_transform input_csc_color_matrix;
1460	struct fixed31_32 coeff_reduction_factor;
1461	struct fixed31_32 hdr_mult;
1462	struct colorspace_transform gamut_remap_matrix;
1463
1464	// TODO: No longer used, remove
1465	struct dc_hdr_static_metadata hdr_static_ctx;
1466
1467	enum dc_color_space color_space;
1468
1469	struct dc_3dlut lut3d_func;
1470	struct dc_transfer_func in_shaper_func;
1471	struct dc_transfer_func blend_tf;
1472
1473	struct dc_transfer_func *gamcor_tf;
1474	enum surface_pixel_format format;
1475	enum dc_rotation_angle rotation;
1476	enum plane_stereo_format stereo_format;
1477
1478	bool is_tiling_rotated;
1479	bool per_pixel_alpha;
1480	bool pre_multiplied_alpha;
1481	bool global_alpha;
1482	int global_alpha_value;
1483	bool visible;
1484	bool flip_immediate;
1485	bool horizontal_mirror;
1486	int layer_index;
1487
1488	union surface_update_flags update_flags;
1489	bool flip_int_enabled;
1490	bool skip_manual_trigger;
1491
1492	/* private to DC core */
1493	struct dc_plane_status status;
1494	struct dc_context *ctx;
1495
1496	/* HACK: Workaround for forcing full reprogramming under some conditions */
1497	bool force_full_update;
1498
1499	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1500
1501	/* private to dc_surface.c */
1502	enum dc_irq_source irq_source;
1503	struct kref refcount;
1504	struct tg_color visual_confirm_color;
1505
1506	bool is_statically_allocated;
1507	enum chroma_cositing cositing;
1508	enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;
1509	bool mcm_lut1d_enable;
1510	struct dc_cm2_func_luts mcm_luts;
1511	bool lut_bank_a;
1512	enum mpcc_movable_cm_location mcm_location;
1513	struct dc_csc_transform cursor_csc_color_matrix;
1514	bool adaptive_sharpness_en;
1515	int adaptive_sharpness_policy;
1516	int sharpness_level;
1517	enum linear_light_scaling linear_light_scaling;
1518	unsigned int sdr_white_level_nits;
1519	struct spl_sharpness_range sharpness_range;
1520	enum sharpness_range_source sharpness_source;
1521	};
1522
1523	struct dc_plane_info {
1524	struct plane_size plane_size;
1525	struct dc_tiling_info tiling_info;
1526	struct dc_plane_dcc_param dcc;
1527	enum surface_pixel_format format;
1528	enum dc_rotation_angle rotation;
1529	enum plane_stereo_format stereo_format;
1530	enum dc_color_space color_space;
1531	bool horizontal_mirror;
1532	bool visible;
1533	bool per_pixel_alpha;
1534	bool pre_multiplied_alpha;
1535	bool global_alpha;
1536	int global_alpha_value;
1537	bool input_csc_enabled;
1538	int layer_index;
1539	enum chroma_cositing cositing;
1540	};
1541
1542	#include "dc_stream.h"
1543
1544	struct dc_scratch_space {
1545	/* used to temporarily backup plane states of a stream during
1546	* dc update. The reason is that plane states are overwritten
1547	* with surface updates in dc update. Once they are overwritten
1548	* current state is no longer valid. We want to temporarily
1549	* store current value in plane states so we can still recover
1550	* a valid current state during dc update.
1551	*/
1552	struct dc_plane_state plane_states[MAX_SURFACES];
1553
1554	struct dc_stream_state stream_state;
1555	};
1556
1557	/*
1558	* A link contains one or more sinks and their connected status.
1559	* The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1560	*/
1561	struct dc_link {
1562	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1563	unsigned int sink_count;
1564	struct dc_sink *local_sink;
1565	unsigned int link_index;
1566	enum dc_connection_type type;
1567	enum signal_type connector_signal;
1568	enum dc_irq_source irq_source_hpd;
1569	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1570	enum dc_irq_source irq_source_read_request;/* Read Request */
1571
1572	bool is_hpd_filter_disabled;
1573	bool dp_ss_off;
1574
1575	/**
1576	* @link_state_valid:
1577	*
1578	* If there is no link and local sink, this variable should be set to
1579	* false. Otherwise, it should be set to true; usually, the function
1580	* core_link_enable_stream sets this field to true.
1581	*/
1582	bool link_state_valid;
1583	bool aux_access_disabled;
1584	bool sync_lt_in_progress;
1585	bool skip_stream_reenable;
1586	bool is_internal_display;
1587	/** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1588	bool is_dig_mapping_flexible;
1589	bool hpd_status; /* HPD status of link without physical HPD pin. */
1590	bool is_hpd_pending; /* Indicates a new received hpd */
1591
1592	/* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1593	* for every link training. This is incompatible with DP LL compliance automation,
1594	* which expects the same link settings to be used every retry on a link loss.
1595	* This flag is used to skip the fallback when link loss occurs during automation.
1596	*/
1597	bool skip_fallback_on_link_loss;
1598
1599	bool edp_sink_present;
1600
1601	struct dp_trace dp_trace;
1602
1603	/* caps is the same as reported_link_cap. link_traing use
1604	* reported_link_cap. Will clean up. TODO
1605	*/
1606	struct dc_link_settings reported_link_cap;
1607	struct dc_link_settings verified_link_cap;
1608	struct dc_link_settings cur_link_settings;
1609	struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1610	struct dc_link_settings preferred_link_setting;
1611	/* preferred_training_settings are override values that
1612	* come from DM. DM is responsible for the memory
1613	* management of the override pointers.
1614	*/
1615	struct dc_link_training_overrides preferred_training_settings;
1616	struct dp_audio_test_data audio_test_data;
1617
1618	uint8_t ddc_hw_inst;
1619
1620	uint8_t hpd_src;
1621
1622	uint8_t link_enc_hw_inst;
1623	/* DIG link encoder ID. Used as index in link encoder resource pool.
1624	* For links with fixed mapping to DIG, this is not changed after dc_link
1625	* object creation.
1626	*/
1627	enum engine_id eng_id;
1628	enum engine_id dpia_preferred_eng_id;
1629
1630	bool test_pattern_enabled;
1631	/* Pending/Current test pattern are only used to perform and track
1632	* FIXED_VS retimer test pattern/lane adjustment override state.
1633	* Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1634	* to perform specific lane adjust overrides before setting certain
1635	* PHY test patterns. In cases when lane adjust and set test pattern
1636	* calls are not performed atomically (i.e. performing link training),
1637	* pending_test_pattern will be invalid or contain a non-PHY test pattern
1638	* and current_test_pattern will contain required context for any future
1639	* set pattern/set lane adjust to transition between override state(s).
1640	* */
1641	enum dp_test_pattern current_test_pattern;
1642	enum dp_test_pattern pending_test_pattern;
1643
1644	union compliance_test_state compliance_test_state;
1645
1646	void *priv;
1647
1648	struct ddc_service *ddc;
1649
1650	enum dp_panel_mode panel_mode;
1651	bool aux_mode;
1652
1653	/* Private to DC core */
1654
1655	const struct dc *dc;
1656
1657	struct dc_context *ctx;
1658
1659	struct panel_cntl *panel_cntl;
1660	struct link_encoder *link_enc;
1661	struct graphics_object_id link_id;
1662	/* Endpoint type distinguishes display endpoints which do not have entries
1663	* in the BIOS connector table from those that do. Helps when tracking link
1664	* encoder to display endpoint assignments.
1665	*/
1666	enum display_endpoint_type ep_type;
1667	union ddi_channel_mapping ddi_channel_mapping;
1668	struct connector_device_tag_info device_tag;
1669	struct dpcd_caps dpcd_caps;
1670	uint32_t dongle_max_pix_clk;
1671	unsigned short chip_caps;
1672	unsigned int dpcd_sink_count;
1673	struct hdcp_caps hdcp_caps;
1674	enum edp_revision edp_revision;
1675	union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1676
1677	struct psr_settings psr_settings;
1678	struct replay_settings replay_settings;
1679
1680	/* Drive settings read from integrated info table */
1681	struct dc_lane_settings bios_forced_drive_settings;
1682
1683	/* Vendor specific LTTPR workaround variables */
1684	uint8_t vendor_specific_lttpr_link_rate_wa;
1685	bool apply_vendor_specific_lttpr_link_rate_wa;
1686
1687	/* MST record stream using this link */
1688	struct link_flags {
1689	bool dp_keep_receiver_powered;
1690	bool dp_skip_DID2;
1691	bool dp_skip_reset_segment;
1692	bool dp_skip_fs_144hz;
1693	bool dp_mot_reset_segment;
1694	/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1695	bool dpia_mst_dsc_always_on;
1696	/* Forced DPIA into TBT3 compatibility mode. */
1697	bool dpia_forced_tbt3_mode;
1698	bool dongle_mode_timing_override;
1699	bool blank_stream_on_ocs_change;
1700	bool read_dpcd204h_on_irq_hpd;
1701	bool force_dp_ffe_preset;
1702	bool skip_phy_ssc_reduction;
1703	} wa_flags;
1704	union dc_dp_ffe_preset forced_dp_ffe_preset;
1705	struct link_mst_stream_allocation_table mst_stream_alloc_table;
1706
1707	struct dc_link_status link_status;
1708	struct dprx_states dprx_states;
1709
1710	struct gpio *hpd_gpio;
1711	enum dc_link_fec_state fec_state;
1712	bool is_dds;
1713	bool is_display_mux_present;
1714	bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1715
1716	struct dc_panel_config panel_config;
1717	struct phy_state phy_state;
1718	uint32_t phy_transition_bitmask;
1719	// BW ALLOCATON USB4 ONLY
1720	struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1721	bool skip_implict_edp_power_control;
1722	enum backlight_control_type backlight_control_type;
1723	};
1724
1725	struct dc {
1726	struct dc_debug_options debug;
1727	struct dc_versions versions;
1728	struct dc_caps caps;
1729	struct dc_check_config check_config;
1730	struct dc_cap_funcs cap_funcs;
1731	struct dc_config config;
1732	struct dc_bounding_box_overrides bb_overrides;
1733	struct dc_bug_wa work_arounds;
1734	struct dc_context *ctx;
1735	struct dc_phy_addr_space_config vm_pa_config;
1736
1737	uint8_t link_count;
1738	struct dc_link *links[MAX_LINKS];
1739	uint8_t lowest_dpia_link_index;
1740	struct link_service *link_srv;
1741
1742	struct dc_state *current_state;
1743	struct resource_pool *res_pool;
1744
1745	struct clk_mgr *clk_mgr;
1746
1747	/* Display Engine Clock levels */
1748	struct dm_pp_clock_levels sclk_lvls;
1749
1750	/* Inputs into BW and WM calculations. */
1751	struct bw_calcs_dceip *bw_dceip;
1752	struct bw_calcs_vbios *bw_vbios;
1753	struct dcn_soc_bounding_box *dcn_soc;
1754	struct dcn_ip_params *dcn_ip;
1755	struct display_mode_lib dml;
1756
1757	/* HW functions */
1758	struct hw_sequencer_funcs hwss;
1759	struct dce_hwseq *hwseq;
1760
1761	/* Require to optimize clocks and bandwidth for added/removed planes */
1762	bool optimized_required;
1763	bool idle_optimizations_allowed;
1764	bool enable_c20_dtm_b0;
1765
1766	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
1767
1768	/* For eDP to know the switching state of SmartMux */
1769	bool is_switch_in_progress_orig;
1770	bool is_switch_in_progress_dest;
1771
1772	/* FBC compressor */
1773	struct compressor *fbc_compressor;
1774
1775	struct dc_debug_data debug_data;
1776	struct dpcd_vendor_signature vendor_signature;
1777
1778	const char *build_id;
1779	struct vm_helper *vm_helper;
1780
1781	uint32_t *dcn_reg_offsets;
1782	uint32_t *nbio_reg_offsets;
1783	uint32_t *clk_reg_offsets;
1784
1785	/* Scratch memory */
1786	struct {
1787	struct {
1788	/*
1789	* For matching clock_limits table in driver with table
1790	* from PMFW.
1791	*/
1792	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1793	} update_bw_bounding_box;
1794	struct dc_scratch_space current_state;
1795	struct dc_scratch_space new_state;
1796	struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
1797	struct dc_link temp_link;
1798	bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
1799	} scratch;
1800
1801	struct dml2_configuration_options dml2_options;
1802	struct dml2_configuration_options dml2_dc_power_options;
1803	enum dc_acpi_cm_power_state power_state;
1804	struct soc_and_ip_translator *soc_and_ip_translator;
1805	};
1806
1807	struct dc_scaling_info {
1808	struct rect src_rect;
1809	struct rect dst_rect;
1810	struct rect clip_rect;
1811	struct scaling_taps scaling_quality;
1812	};
1813
1814	struct dc_fast_update {
1815	const struct dc_flip_addrs *flip_addr;
1816	const struct dc_gamma *gamma;
1817	const struct colorspace_transform *gamut_remap_matrix;
1818	const struct dc_csc_transform *input_csc_color_matrix;
1819	const struct fixed31_32 *coeff_reduction_factor;
1820	struct dc_transfer_func *out_transfer_func;
1821	struct dc_csc_transform *output_csc_transform;
1822	const struct dc_csc_transform *cursor_csc_color_matrix;
1823	};
1824
1825	struct dc_surface_update {
1826	struct dc_plane_state *surface;
1827
1828	/* isr safe update parameters. null means no updates */
1829	const struct dc_flip_addrs *flip_addr;
1830	const struct dc_plane_info *plane_info;
1831	const struct dc_scaling_info *scaling_info;
1832	struct fixed31_32 hdr_mult;
1833	/* following updates require alloc/sleep/spin that is not isr safe,
1834	* null means no updates
1835	*/
1836	const struct dc_gamma *gamma;
1837	const struct dc_transfer_func *in_transfer_func;
1838
1839	const struct dc_csc_transform *input_csc_color_matrix;
1840	const struct fixed31_32 *coeff_reduction_factor;
1841	const struct dc_transfer_func *func_shaper;
1842	const struct dc_3dlut *lut3d_func;
1843	const struct dc_transfer_func *blend_tf;
1844	const struct colorspace_transform *gamut_remap_matrix;
1845	/*
1846	* Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1847	*
1848	* change cm2_params.component_settings: Full update
1849	* change cm2_params.cm2_luts: Fast update
1850	*/
1851	const struct dc_cm2_parameters *cm2_params;
1852	const struct dc_csc_transform *cursor_csc_color_matrix;
1853	unsigned int sdr_white_level_nits;
1854	struct dc_bias_and_scale bias_and_scale;
1855	};
1856
1857	struct dc_underflow_debug_data {
1858	struct dcn_hubbub_reg_state *hubbub_reg_state;
1859	struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
1860	struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
1861	struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
1862	struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
1863	struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
1864	struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
1865	struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];
1866	};
1867
1868	struct power_features {
1869	bool ips;
1870	bool rcg;
1871	bool replay;
1872	bool dds;
1873	bool sprs;
1874	bool psr;
1875	bool fams;
1876	bool mpo;
1877	bool uclk_p_state;
1878	};
1879
1880	/*
1881	* Create a new surface with default parameters;
1882	*/
1883	void dc_gamma_retain(struct dc_gamma *dc_gamma);
1884	void dc_gamma_release(struct dc_gamma **dc_gamma);
1885	struct dc_gamma *dc_create_gamma(void);
1886
1887	void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1888	void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1889	struct dc_transfer_func *dc_create_transfer_func(void);
1890
1891	struct dc_3dlut *dc_create_3dlut_func(void);
1892	void dc_3dlut_func_release(struct dc_3dlut *lut);
1893	void dc_3dlut_func_retain(struct dc_3dlut *lut);
1894
1895	void dc_post_update_surfaces_to_stream(
1896	struct dc *dc);
1897
1898	/**
1899	* struct dc_validation_set - Struct to store surface/stream associations for validation
1900	*/
1901	struct dc_validation_set {
1902	/**
1903	* @stream: Stream state properties
1904	*/
1905	struct dc_stream_state *stream;
1906
1907	/**
1908	* @plane_states: Surface state
1909	*/
1910	struct dc_plane_state *plane_states[MAX_SURFACES];
1911
1912	/**
1913	* @plane_count: Total of active planes
1914	*/
1915	uint8_t plane_count;
1916	};
1917
1918	bool dc_validate_boot_timing(const struct dc *dc,
1919	const struct dc_sink *sink,
1920	struct dc_crtc_timing *crtc_timing);
1921
1922	enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1923
1924	enum dc_status dc_validate_with_context(struct dc *dc,
1925	const struct dc_validation_set set[],
1926	int set_count,
1927	struct dc_state *context,
1928	enum dc_validate_mode validate_mode);
1929
1930	bool dc_set_generic_gpio_for_stereo(bool enable,
1931	struct gpio_service *gpio_service);
1932
1933	enum dc_status dc_validate_global_state(
1934	struct dc *dc,
1935	struct dc_state *new_ctx,
1936	enum dc_validate_mode validate_mode);
1937
1938	bool dc_acquire_release_mpc_3dlut(
1939	struct dc *dc, bool acquire,
1940	struct dc_stream_state *stream,
1941	struct dc_3dlut **lut,
1942	struct dc_transfer_func **shaper);
1943
1944	bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1945	void get_audio_check(struct audio_info *aud_modes,
1946	struct audio_check *aud_chk);
1947
1948	bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
1949	void populate_fast_updates(struct dc_fast_update *fast_update,
1950	struct dc_surface_update *srf_updates,
1951	int surface_count,
1952	struct dc_stream_update *stream_update);
1953	/*
1954	* Set up streams and links associated to drive sinks
1955	* The streams parameter is an absolute set of all active streams.
1956	*
1957	* After this call:
1958	* Phy, Encoder, Timing Generator are programmed and enabled.
1959	* New streams are enabled with blank stream; no memory read.
1960	*/
1961	enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1962
1963
1964	struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1965	struct dc_stream_state *stream,
1966	int mpcc_inst);
1967
1968
1969	uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1970
1971	void dc_set_disable_128b_132b_stream_overhead(bool disable);
1972
1973	/* The function returns minimum bandwidth required to drive a given timing
1974	* return - minimum required timing bandwidth in kbps.
1975	*/
1976	uint32_t dc_bandwidth_in_kbps_from_timing(
1977	const struct dc_crtc_timing *timing,
1978	const enum dc_link_encoding_format link_encoding);
1979
1980	/* Link Interfaces */
1981	/* Return an enumerated dc_link.
1982	* dc_link order is constant and determined at
1983	* boot time. They cannot be created or destroyed.
1984	* Use dc_get_caps() to get number of links.
1985	*/
1986	struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1987
1988	/* Return instance id of the edp link. Inst 0 is primary edp link. */
1989	bool dc_get_edp_link_panel_inst(const struct dc *dc,
1990	const struct dc_link *link,
1991	unsigned int *inst_out);
1992
1993	/* Return an array of link pointers to edp links. */
1994	void dc_get_edp_links(const struct dc *dc,
1995	struct dc_link **edp_links,
1996	int *edp_num);
1997
1998	void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1999	bool powerOn);
2000
2001	/* The function initiates detection handshake over the given link. It first
2002	* determines if there are display connections over the link. If so it initiates
2003	* detection protocols supported by the connected receiver device. The function
2004	* contains protocol specific handshake sequences which are sometimes mandatory
2005	* to establish a proper connection between TX and RX. So it is always
2006	* recommended to call this function as the first link operation upon HPD event
2007	* or power up event. Upon completion, the function will update link structure
2008	* in place based on latest RX capabilities. The function may also cause dpms
2009	* to be reset to off for all currently enabled streams to the link. It is DM's
2010	* responsibility to serialize detection and DPMS updates.
2011	*
2012	* @reason - Indicate which event triggers this detection. dc may customize
2013	* detection flow depending on the triggering events.
2014	* return false - if detection is not fully completed. This could happen when
2015	* there is an unrecoverable error during detection or detection is partially
2016	* completed (detection has been delegated to dm mst manager ie.
2017	* link->connection_type == dc_connection_mst_branch when returning false).
2018	* return true - detection is completed, link has been fully updated with latest
2019	* detection result.
2020	*/
2021	bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
2022
2023	struct dc_sink_init_data;
2024
2025	/* When link connection type is dc_connection_mst_branch, remote sink can be
2026	* added to the link. The interface creates a remote sink and associates it with
2027	* current link. The sink will be retained by link until remove remote sink is
2028	* called.
2029	*
2030	* @dc_link - link the remote sink will be added to.
2031	* @edid - byte array of EDID raw data.
2032	* @len - size of the edid in byte
2033	* @init_data -
2034	*/
2035	struct dc_sink *dc_link_add_remote_sink(
2036	struct dc_link *dc_link,
2037	const uint8_t *edid,
2038	int len,
2039	struct dc_sink_init_data *init_data);
2040
2041	/* Remove remote sink from a link with dc_connection_mst_branch connection type.
2042	* @link - link the sink should be removed from
2043	* @sink - sink to be removed.
2044	*/
2045	void dc_link_remove_remote_sink(
2046	struct dc_link *link,
2047	struct dc_sink *sink);
2048
2049	/* Enable HPD interrupt handler for a given link */
2050	void dc_link_enable_hpd(const struct dc_link *link);
2051
2052	/* Disable HPD interrupt handler for a given link */
2053	void dc_link_disable_hpd(const struct dc_link *link);
2054
2055	/* determine if there is a sink connected to the link
2056	*
2057	* @type - dc_connection_single if connected, dc_connection_none otherwise.
2058	* return - false if an unexpected error occurs, true otherwise.
2059	*
2060	* NOTE: This function doesn't detect downstream sink connections i.e
2061	* dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
2062	* return dc_connection_single if the branch device is connected despite of
2063	* downstream sink's connection status.
2064	*/
2065	bool dc_link_detect_connection_type(struct dc_link *link,
2066	enum dc_connection_type *type);
2067
2068	/* query current hpd pin value
2069	* return - true HPD is asserted (HPD high), false otherwise (HPD low)
2070	*
2071	*/
2072	bool dc_link_get_hpd_state(struct dc_link *link);
2073
2074	/* Getter for cached link status from given link */
2075	const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
2076
2077	/* enable/disable hardware HPD filter.
2078	*
2079	* @link - The link the HPD pin is associated with.
2080	* @enable = true - enable hardware HPD filter. HPD event will only queued to irq
2081	* handler once after no HPD change has been detected within dc default HPD
2082	* filtering interval since last HPD event. i.e if display keeps toggling hpd
2083	* pulses within default HPD interval, no HPD event will be received until HPD
2084	* toggles have stopped. Then HPD event will be queued to irq handler once after
2085	* dc default HPD filtering interval since last HPD event.
2086	*
2087	* @enable = false - disable hardware HPD filter. HPD event will be queued
2088	* immediately to irq handler after no HPD change has been detected within
2089	* IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
2090	*/
2091	void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
2092
2093	/* submit i2c read/write payloads through ddc channel
2094	* @link_index - index to a link with ddc in i2c mode
2095	* @cmd - i2c command structure
2096	* return - true if success, false otherwise.
2097	*/
2098	bool dc_submit_i2c(
2099	struct dc *dc,
2100	uint32_t link_index,
2101	struct i2c_command *cmd);
2102
2103	/* submit i2c read/write payloads through oem channel
2104	* @link_index - index to a link with ddc in i2c mode
2105	* @cmd - i2c command structure
2106	* return - true if success, false otherwise.
2107	*/
2108	bool dc_submit_i2c_oem(
2109	struct dc *dc,
2110	struct i2c_command *cmd);
2111
2112	enum aux_return_code_type;
2113	/* Attempt to transfer the given aux payload. This function does not perform
2114	* retries or handle error states. The reply is returned in the payload->reply
2115	* and the result through operation_result. Returns the number of bytes
2116	* transferred,or -1 on a failure.
2117	*/
2118	int dc_link_aux_transfer_raw(struct ddc_service *ddc,
2119	struct aux_payload *payload,
2120	enum aux_return_code_type *operation_result);
2121
2122	struct ddc_service *
2123	dc_get_oem_i2c_device(struct dc *dc);
2124
2125	bool dc_is_oem_i2c_device_present(
2126	struct dc *dc,
2127	size_t slave_address
2128	);
2129
2130	/* return true if the connected receiver supports the hdcp version */
2131	bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
2132	bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
2133
2134	/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
2135	*
2136	* TODO - When defer_handling is true the function will have a different purpose.
2137	* It no longer does complete hpd rx irq handling. We should create a separate
2138	* interface specifically for this case.
2139	*
2140	* Return:
2141	* true - Downstream port status changed. DM should call DC to do the
2142	* detection.
2143	* false - no change in Downstream port status. No further action required
2144	* from DM.
2145	*/
2146	bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
2147	union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
2148	bool defer_handling, bool *has_left_work);
2149	/* handle DP specs define test automation sequence*/
2150	void dc_link_dp_handle_automated_test(struct dc_link *link);
2151
2152	/* handle DP Link loss sequence and try to recover RX link loss with best
2153	* effort
2154	*/
2155	void dc_link_dp_handle_link_loss(struct dc_link *link);
2156
2157	/* Determine if hpd rx irq should be handled or ignored
2158	* return true - hpd rx irq should be handled.
2159	* return false - it is safe to ignore hpd rx irq event
2160	*/
2161	bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
2162
2163	/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
2164	* @link - link the hpd irq data associated with
2165	* @hpd_irq_dpcd_data - input hpd irq data
2166	* return - true if hpd irq data indicates a link lost
2167	*/
2168	bool dc_link_check_link_loss_status(struct dc_link *link,
2169	union hpd_irq_data *hpd_irq_dpcd_data);
2170
2171	/* Read hpd rx irq data from a given link
2172	* @link - link where the hpd irq data should be read from
2173	* @irq_data - output hpd irq data
2174	* return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
2175	* read has failed.
2176	*/
2177	enum dc_status dc_link_dp_read_hpd_rx_irq_data(
2178	struct dc_link *link,
2179	union hpd_irq_data *irq_data);
2180
2181	/* The function clears recorded DP RX states in the link. DM should call this
2182	* function when it is resuming from S3 power state to previously connected links.
2183	*
2184	* TODO - in the future we should consider to expand link resume interface to
2185	* support clearing previous rx states. So we don't have to rely on dm to call
2186	* this interface explicitly.
2187	*/
2188	void dc_link_clear_dprx_states(struct dc_link *link);
2189
2190	/* Destruct the mst topology of the link and reset the allocated payload table
2191	*
2192	* NOTE: this should only be called if DM chooses not to call dc_link_detect but
2193	* still wants to reset MST topology on an unplug event */
2194	bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
2195
2196	/* The function calculates effective DP link bandwidth when a given link is
2197	* using the given link settings.
2198	*
2199	* return - total effective link bandwidth in kbps.
2200	*/
2201	uint32_t dc_link_bandwidth_kbps(
2202	const struct dc_link *link,
2203	const struct dc_link_settings *link_setting);
2204
2205	struct dp_audio_bandwidth_params {
2206	const struct dc_crtc_timing *crtc_timing;
2207	enum dp_link_encoding link_encoding;
2208	uint32_t channel_count;
2209	uint32_t sample_rate_hz;
2210	};
2211
2212	/* The function calculates the minimum size of hblank (in bytes) needed to
2213	* support the specified channel count and sample rate combination, given the
2214	* link encoding and timing to be used. This calculation is not supported
2215	* for 8b/10b SST.
2216	*
2217	* return - min hblank size in bytes, 0 if 8b/10b SST.
2218	*/
2219	uint32_t dc_link_required_hblank_size_bytes(
2220	const struct dc_link *link,
2221	struct dp_audio_bandwidth_params *audio_params);
2222
2223	/* The function takes a snapshot of current link resource allocation state
2224	* @dc: pointer to dc of the dm calling this
2225	* @map: a dc link resource snapshot defined internally to dc.
2226	*
2227	* DM needs to capture a snapshot of current link resource allocation mapping
2228	* and store it in its persistent storage.
2229	*
2230	* Some of the link resource is using first come first serve policy.
2231	* The allocation mapping depends on original hotplug order. This information
2232	* is lost after driver is loaded next time. The snapshot is used in order to
2233	* restore link resource to its previous state so user will get consistent
2234	* link capability allocation across reboot.
2235	*
2236	*/
2237	void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2238
2239	/* This function restores link resource allocation state from a snapshot
2240	* @dc: pointer to dc of the dm calling this
2241	* @map: a dc link resource snapshot defined internally to dc.
2242	*
2243	* DM needs to call this function after initial link detection on boot and
2244	* before first commit streams to restore link resource allocation state
2245	* from previous boot session.
2246	*
2247	* Some of the link resource is using first come first serve policy.
2248	* The allocation mapping depends on original hotplug order. This information
2249	* is lost after driver is loaded next time. The snapshot is used in order to
2250	* restore link resource to its previous state so user will get consistent
2251	* link capability allocation across reboot.
2252	*
2253	*/
2254	void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2255
2256	/* TODO: this is not meant to be exposed to DM. Should switch to stream update
2257	* interface i.e stream_update->dsc_config
2258	*/
2259	bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
2260
2261	/* translate a raw link rate data to bandwidth in kbps */
2262	uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2263
2264	/* determine the optimal bandwidth given link and required bw.
2265	* @link - current detected link
2266	* @req_bw - requested bandwidth in kbps
2267	* @link_settings - returned most optimal link settings that can fit the
2268	* requested bandwidth
2269	* return - false if link can't support requested bandwidth, true if link
2270	* settings is found.
2271	*/
2272	bool dc_link_decide_edp_link_settings(struct dc_link *link,
2273	struct dc_link_settings *link_settings,
2274	uint32_t req_bw);
2275
2276	/* return the max dp link settings can be driven by the link without considering
2277	* connected RX device and its capability
2278	*/
2279	bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
2280	struct dc_link_settings *max_link_enc_cap);
2281
2282	/* determine when the link is driving MST mode, what DP link channel coding
2283	* format will be used. The decision will remain unchanged until next HPD event.
2284	*
2285	* @link - a link with DP RX connection
2286	* return - if stream is committed to this link with MST signal type, type of
2287	* channel coding format dc will choose.
2288	*/
2289	enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
2290	const struct dc_link *link);
2291
2292	/* get max dp link settings the link can enable with all things considered. (i.e
2293	* TX/RX/Cable capabilities and dp override policies.
2294	*
2295	* @link - a link with DP RX connection
2296	* return - max dp link settings the link can enable.
2297	*
2298	*/
2299	const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
2300
2301	/* Get the highest encoding format that the link supports; highest meaning the
2302	* encoding format which supports the maximum bandwidth.
2303	*
2304	* @link - a link with DP RX connection
2305	* return - highest encoding format link supports.
2306	*/
2307	enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
2308
2309	/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
2310	* to a link with dp connector signal type.
2311	* @link - a link with dp connector signal type
2312	* return - true if connected, false otherwise
2313	*/
2314	bool dc_link_is_dp_sink_present(struct dc_link *link);
2315
2316	/* Force DP lane settings update to main-link video signal and notify the change
2317	* to DP RX via DPCD. This is a debug interface used for video signal integrity
2318	* tuning purpose. The interface assumes link has already been enabled with DP
2319	* signal.
2320	*
2321	* @lt_settings - a container structure with desired hw_lane_settings
2322	*/
2323	void dc_link_set_drive_settings(struct dc *dc,
2324	struct link_training_settings *lt_settings,
2325	struct dc_link *link);
2326
2327	/* Enable a test pattern in Link or PHY layer in an active link for compliance
2328	* test or debugging purpose. The test pattern will remain until next un-plug.
2329	*
2330	* @link - active link with DP signal output enabled.
2331	* @test_pattern - desired test pattern to output.
2332	* NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
2333	* @test_pattern_color_space - for video test pattern choose a desired color
2334	* space.
2335	* @p_link_settings - For PHY pattern choose a desired link settings
2336	* @p_custom_pattern - some test pattern will require a custom input to
2337	* customize some pattern details. Otherwise keep it to NULL.
2338	* @cust_pattern_size - size of the custom pattern input.
2339	*
2340	*/
2341	bool dc_link_dp_set_test_pattern(
2342	struct dc_link *link,
2343	enum dp_test_pattern test_pattern,
2344	enum dp_test_pattern_color_space test_pattern_color_space,
2345	const struct link_training_settings *p_link_settings,
2346	const unsigned char *p_custom_pattern,
2347	unsigned int cust_pattern_size);
2348
2349	/* Force DP link settings to always use a specific value until reboot to a
2350	* specific link. If link has already been enabled, the interface will also
2351	* switch to desired link settings immediately. This is a debug interface to
2352	* generic dp issue trouble shooting.
2353	*/
2354	void dc_link_set_preferred_link_settings(struct dc *dc,
2355	struct dc_link_settings *link_setting,
2356	struct dc_link *link);
2357
2358	/* Force DP link to customize a specific link training behavior by overriding to
2359	* standard DP specs defined protocol. This is a debug interface to trouble shoot
2360	* display specific link training issues or apply some display specific
2361	* workaround in link training.
2362	*
2363	* @link_settings - if not NULL, force preferred link settings to the link.
2364	* @lt_override - a set of override pointers. If any pointer is none NULL, dc
2365	* will apply this particular override in future link training. If NULL is
2366	* passed in, dc resets previous overrides.
2367	* NOTE: DM must keep the memory from override pointers until DM resets preferred
2368	* training settings.
2369	*/
2370	void dc_link_set_preferred_training_settings(struct dc *dc,
2371	struct dc_link_settings *link_setting,
2372	struct dc_link_training_overrides *lt_overrides,
2373	struct dc_link *link,
2374	bool skip_immediate_retrain);
2375
2376	/* return - true if FEC is supported with connected DP RX, false otherwise */
2377	bool dc_link_is_fec_supported(const struct dc_link *link);
2378
2379	/* query FEC enablement policy to determine if FEC will be enabled by dc during
2380	* link enablement.
2381	* return - true if FEC should be enabled, false otherwise.
2382	*/
2383	bool dc_link_should_enable_fec(const struct dc_link *link);
2384
2385	/* determine lttpr mode the current link should be enabled with a specific link
2386	* settings.
2387	*/
2388	enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2389	struct dc_link_settings *link_setting);
2390
2391	/* Force DP RX to update its power state.
2392	* NOTE: this interface doesn't update dp main-link. Calling this function will
2393	* cause DP TX main-link and DP RX power states out of sync. DM has to restore
2394	* RX power state back upon finish DM specific execution requiring DP RX in a
2395	* specific power state.
2396	* @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2397	* state.
2398	*/
2399	void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2400
2401	/* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2402	* current value read from extended receiver cap from 02200h - 0220Fh.
2403	* Some DP RX has problems of providing accurate DP receiver caps from extended
2404	* field, this interface is a workaround to revert link back to use base caps.
2405	*/
2406	void dc_link_overwrite_extended_receiver_cap(
2407	struct dc_link *link);
2408
2409	void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2410	bool wait_for_hpd);
2411
2412	/* Set backlight level of an embedded panel (eDP, LVDS).
2413	* backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2414	* and 16 bit fractional, where 1.0 is max backlight value.
2415	*/
2416	bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2417	struct set_backlight_level_params *backlight_level_params);
2418
2419	/* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2420	bool dc_link_set_backlight_level_nits(struct dc_link *link,
2421	bool isHDR,
2422	uint32_t backlight_millinits,
2423	uint32_t transition_time_in_ms);
2424
2425	bool dc_link_get_backlight_level_nits(struct dc_link *link,
2426	uint32_t *backlight_millinits,
2427	uint32_t *backlight_millinits_peak);
2428
2429	int dc_link_get_backlight_level(const struct dc_link *dc_link);
2430
2431	int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2432
2433	bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2434	bool wait, bool force_static, const unsigned int *power_opts);
2435
2436	bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2437
2438	bool dc_link_setup_psr(struct dc_link *dc_link,
2439	const struct dc_stream_state *stream, struct psr_config *psr_config,
2440	struct psr_context *psr_context);
2441
2442	/*
2443	* Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2444	*
2445	* @link: pointer to the dc_link struct instance
2446	* @enable: enable(active) or disable(inactive) replay
2447	* @wait: state transition need to wait the active set completed.
2448	* @force_static: force disable(inactive) the replay
2449	* @power_opts: set power optimazation parameters to DMUB.
2450	*
2451	* return: allow Replay active will return true, else will return false.
2452	*/
2453	bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2454	bool wait, bool force_static, const unsigned int *power_opts);
2455
2456	bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2457
2458	/* On eDP links this function call will stall until T12 has elapsed.
2459	* If the panel is not in power off state, this function will return
2460	* immediately.
2461	*/
2462	bool dc_link_wait_for_t12(struct dc_link *link);
2463
2464	/* Determine if dp trace has been initialized to reflect upto date result *
2465	* return - true if trace is initialized and has valid data. False dp trace
2466	* doesn't have valid result.
2467	*/
2468	bool dc_dp_trace_is_initialized(struct dc_link *link);
2469
2470	/* Query a dp trace flag to indicate if the current dp trace data has been
2471	* logged before
2472	*/
2473	bool dc_dp_trace_is_logged(struct dc_link *link,
2474	bool in_detection);
2475
2476	/* Set dp trace flag to indicate whether DM has already logged the current dp
2477	* trace data. DM can set is_logged to true upon logging and check
2478	* dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2479	*/
2480	void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2481	bool in_detection,
2482	bool is_logged);
2483
2484	/* Obtain driver time stamp for last dp link training end. The time stamp is
2485	* formatted based on dm_get_timestamp DM function.
2486	* @in_detection - true to get link training end time stamp of last link
2487	* training in detection sequence. false to get link training end time stamp
2488	* of last link training in commit (dpms) sequence
2489	*/
2490	unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2491	bool in_detection);
2492
2493	/* Get how many link training attempts dc has done with latest sequence.
2494	* @in_detection - true to get link training count of last link
2495	* training in detection sequence. false to get link training count of last link
2496	* training in commit (dpms) sequence
2497	*/
2498	const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2499	bool in_detection);
2500
2501	/* Get how many link loss has happened since last link training attempts */
2502	unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2503
2504	/*
2505	* USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2506	*/
2507	/*
2508	* Send a request from DP-Tx requesting to allocate BW remotely after
2509	* allocating it locally. This will get processed by CM and a CB function
2510	* will be called.
2511	*
2512	* @link: pointer to the dc_link struct instance
2513	* @req_bw: The requested bw in Kbyte to allocated
2514	*
2515	* return: none
2516	*/
2517	void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2518
2519	/*
2520	* Handle the USB4 BW Allocation related functionality here:
2521	* Plug => Try to allocate max bw from timing parameters supported by the sink
2522	* Unplug => de-allocate bw
2523	*
2524	* @link: pointer to the dc_link struct instance
2525	* @peak_bw: Peak bw used by the link/sink
2526	*
2527	*/
2528	void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2529	struct dc_link *link, int peak_bw);
2530
2531	/*
2532	* Calculates the DP tunneling bandwidth required for the stream timing
2533	* and aggregates the stream bandwidth for the respective DP tunneling link
2534	*
2535	* return: dc_status
2536	*/
2537	enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);
2538
2539	/*
2540	* Get if ALPM is supported by the link
2541	*/
2542	void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support,
2543	bool *auxwake_support);
2544
2545	/* Sink Interfaces - A sink corresponds to a display output device */
2546
2547	struct dc_container_id {
2548	// 128bit GUID in binary form
2549	unsigned char guid[16];
2550	// 8 byte port ID -> ELD.PortID
2551	unsigned int portId[2];
2552	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2553	unsigned short manufacturerName;
2554	// 2 byte product code -> ELD.ProductCode
2555	unsigned short productCode;
2556	};
2557
2558
2559	struct dc_sink_dsc_caps {
2560	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2561	// 'false' if they are sink's DSC caps
2562	bool is_virtual_dpcd_dsc;
2563	// 'true' if MST topology supports DSC passthrough for sink
2564	// 'false' if MST topology does not support DSC passthrough
2565	bool is_dsc_passthrough_supported;
2566	struct dsc_dec_dpcd_caps dsc_dec_caps;
2567	};
2568
2569	struct dc_sink_hblank_expansion_caps {
2570	// 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology),
2571	// 'false' if they are sink's HBlank expansion caps
2572	bool is_virtual_dpcd_hblank_expansion;
2573	struct hblank_expansion_dpcd_caps dpcd_caps;
2574	};
2575
2576	struct dc_sink_fec_caps {
2577	bool is_rx_fec_supported;
2578	bool is_topology_fec_supported;
2579	};
2580
2581	struct scdc_caps {
2582	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2583	union hdmi_scdc_device_id_data device_id;
2584	};
2585
2586	/*
2587	* The sink structure contains EDID and other display device properties
2588	*/
2589	struct dc_sink {
2590	enum signal_type sink_signal;
2591	struct dc_edid dc_edid; /* raw edid */
2592	struct dc_edid_caps edid_caps; /* parse display caps */
2593	struct dc_container_id *dc_container_id;
2594	uint32_t dongle_max_pix_clk;
2595	void *priv;
2596	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2597	bool converter_disable_audio;
2598
2599	struct scdc_caps scdc_caps;
2600	struct dc_sink_dsc_caps dsc_caps;
2601	struct dc_sink_fec_caps fec_caps;
2602	struct dc_sink_hblank_expansion_caps hblank_expansion_caps;
2603
2604	bool is_vsc_sdp_colorimetry_supported;
2605
2606	/* private to DC core */
2607	struct dc_link *link;
2608	struct dc_context *ctx;
2609
2610	uint32_t sink_id;
2611
2612	/* private to dc_sink.c */
2613	// refcount must be the last member in dc_sink, since we want the
2614	// sink structure to be logically cloneable up to (but not including)
2615	// refcount
2616	struct kref refcount;
2617	};
2618
2619	void dc_sink_retain(struct dc_sink *sink);
2620	void dc_sink_release(struct dc_sink *sink);
2621
2622	struct dc_sink_init_data {
2623	enum signal_type sink_signal;
2624	struct dc_link *link;
2625	uint32_t dongle_max_pix_clk;
2626	bool converter_disable_audio;
2627	};
2628
2629	struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2630
2631	/* Newer interfaces */
2632	struct dc_cursor {
2633	struct dc_plane_address address;
2634	struct dc_cursor_attributes attributes;
2635	};
2636
2637
2638	/* Interrupt interfaces */
2639	enum dc_irq_source dc_interrupt_to_irq_source(
2640	struct dc *dc,
2641	uint32_t src_id,
2642	uint32_t ext_id);
2643	bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2644	void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2645	enum dc_irq_source dc_get_hpd_irq_source_at_index(
2646	struct dc *dc, uint32_t link_index);
2647
2648	void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2649
2650	/* Power Interfaces */
2651
2652	void dc_set_power_state(
2653	struct dc *dc,
2654	enum dc_acpi_cm_power_state power_state);
2655	void dc_resume(struct dc *dc);
2656
2657	void dc_power_down_on_boot(struct dc *dc);
2658
2659	/*
2660	* HDCP Interfaces
2661	*/
2662	enum hdcp_message_status dc_process_hdcp_msg(
2663	enum signal_type signal,
2664	struct dc_link *link,
2665	struct hdcp_protection_message *message_info);
2666	bool dc_is_dmcu_initialized(struct dc *dc);
2667
2668	enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2669	void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2670
2671	bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2672	unsigned int pitch,
2673	unsigned int height,
2674	enum surface_pixel_format format,
2675	struct dc_cursor_attributes *cursor_attr);
2676
2677	#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)
2678	#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)
2679
2680	void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2681	void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2682	bool dc_dmub_is_ips_idle_state(struct dc *dc);
2683
2684	/* set min and max memory clock to lowest and highest DPM level, respectively */
2685	void dc_unlock_memory_clock_frequency(struct dc *dc);
2686
2687	/* set min memory clock to the min required for current mode, max to maxDPM */
2688	void dc_lock_memory_clock_frequency(struct dc *dc);
2689
2690	/* set soft max for memclk, to be used for AC/DC switching clock limitations */
2691	void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2692
2693	/* cleanup on driver unload */
2694	void dc_hardware_release(struct dc *dc);
2695
2696	/* disables fw based mclk switch */
2697	void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2698
2699	bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2700
2701	bool dc_set_replay_allow_active(struct dc *dc, bool active);
2702
2703	bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2704
2705	void dc_z10_restore(const struct dc *dc);
2706	void dc_z10_save_init(struct dc *dc);
2707
2708	bool dc_is_dmub_outbox_supported(struct dc *dc);
2709	bool dc_enable_dmub_notifications(struct dc *dc);
2710
2711	bool dc_abm_save_restore(
2712	struct dc *dc,
2713	struct dc_stream_state *stream,
2714	struct abm_save_restore *pData);
2715
2716	void dc_enable_dmub_outbox(struct dc *dc);
2717
2718	bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2719	uint32_t link_index,
2720	struct aux_payload *payload);
2721
2722	/*
2723	* smart power OLED Interfaces
2724	*/
2725	bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits,
2726	uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline);
2727	bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL);
2728
2729	/* Get dc link index from dpia port index */
2730	uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2731	uint8_t dpia_port_index);
2732
2733	bool dc_process_dmub_set_config_async(struct dc *dc,
2734	uint32_t link_index,
2735	struct set_config_cmd_payload *payload,
2736	struct dmub_notification *notify);
2737
2738	enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2739	uint32_t link_index,
2740	uint8_t mst_alloc_slots,
2741	uint8_t *mst_slots_in_use);
2742
2743	void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);
2744
2745	void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2746	uint32_t hpd_int_enable);
2747
2748	void dc_print_dmub_diagnostic_data(const struct dc *dc);
2749
2750	void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2751
2752	struct dc_power_profile {
2753	int power_level; /* Lower is better */
2754	};
2755
2756	struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2757
2758	unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);
2759
2760	bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index);
2761
2762	void dc_log_preos_dmcub_info(const struct dc *dc);
2763
2764	/* DSC Interfaces */
2765	#include "dc_dsc.h"
2766
2767	void dc_get_visual_confirm_for_stream(
2768	struct dc *dc,
2769	struct dc_stream_state *stream_state,
2770	struct tg_color *color);
2771
2772	/* Disable acc mode Interfaces */
2773	void dc_disable_accelerated_mode(struct dc *dc);
2774
2775	bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2776	struct dc_stream_state *new_stream);
2777
2778	bool dc_is_cursor_limit_pending(struct dc *dc);
2779	bool dc_can_clear_cursor_limit(const struct dc *dc);
2780
2781	/**
2782	* dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.
2783	*
2784	* @dc: Pointer to the display core context.
2785	* @primary_otg_inst: Instance index of the primary OTG that underflowed.
2786	* @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information.
2787	*
2788	* This function collects and logs underflow-related HW states when underflow happens,
2789	* including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
2790	* The results are stored in the provided out_data structure for further analysis or logging.
2791	*/
2792	void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);
2793
2794	void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data);
2795
2796	/**
2797	* Software state variables used to program register fields across the display pipeline
2798	*/
2799	struct dc_register_software_state {
2800	/* HUBP register programming variables for each pipe */
2801	struct {
2802	bool valid_plane_state;
2803	bool valid_stream;
2804	bool min_dc_gfx_version9;
2805	uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */
2806	uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */
2807	uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */
2808	uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */
2809	uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */
2810	uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */
2811	uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */
2812	uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */
2813	uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */
2814	uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */
2815	uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */
2816	uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */
2817	uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */
2818	uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */
2819	uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */
2820
2821	/* Additional DCC configuration */
2822	uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */
2823	uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */
2824
2825	/* Surface pitch configuration */
2826	uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */
2827	uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */
2828	uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */
2829	uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */
2830
2831	/* Surface addresses */
2832	uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */
2833	uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */
2834	uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */
2835	uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */
2836
2837	/* TMZ configuration */
2838	uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */
2839	uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */
2840
2841	/* Tiling configuration */
2842	uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */
2843	uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */
2844	uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */
2845	uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */
2846	uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */
2847	uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */
2848	uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */
2849
2850	/* DML Request Size Configuration - Luma */
2851	uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */
2852	uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */
2853	uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */
2854	uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */
2855	uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */
2856	uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */
2857	uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */
2858	uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */
2859
2860	/* DML Request Size Configuration - Chroma */
2861	uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */
2862	uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */
2863	uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */
2864	uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */
2865	uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */
2866	uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */
2867	uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */
2868	uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */
2869
2870	/* DML Expansion Modes */
2871	uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */
2872	uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */
2873	uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */
2874	uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */
2875
2876	/* DML DLG parameters - nominal */
2877	uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */
2878	uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */
2879	uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */
2880	uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */
2881
2882	/* DML prefetch settings */
2883	uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */
2884	uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */
2885	uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */
2886
2887	/* TTU parameters */
2888	uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */
2889	uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */
2890	uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */
2891	uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */
2892	} hubp[MAX_PIPES];
2893
2894	/* HUBBUB register programming variables */
2895	struct {
2896	/* Individual DET buffer control per pipe - software state that programs DET registers */
2897	uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */
2898	uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */
2899	uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */
2900	uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */
2901
2902	/* Compression buffer control - software state that programs COMPBUF registers */
2903	uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */
2904	uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */
2905	uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */
2906	} hubbub;
2907
2908	/* DPP register programming variables for each pipe (simplified for available fields) */
2909	struct {
2910	uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */
2911
2912	/* Recout (Rectangle of Interest) configuration */
2913	uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */
2914	uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */
2915	uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */
2916	uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */
2917
2918	/* MPC (Multiple Pipe/Plane Combiner) size configuration */
2919	uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */
2920	uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */
2921
2922	/* DSCL mode configuration */
2923	uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */
2924
2925	/* Scaler ratios (simplified to integer parts) */
2926	uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */
2927	uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */
2928
2929	/* Basic scaler taps */
2930	uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */
2931	uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */
2932	} dpp[MAX_PIPES];
2933
2934	/* DCCG register programming variables */
2935	struct {
2936	/* Core Display Clock Control */
2937	uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */
2938	uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */
2939
2940	/* DPP Clock Control - 4 fields per pipe */
2941	uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */
2942	uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */
2943	uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */
2944	uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */
2945	uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */
2946
2947	/* DSC Clock Control - 4 fields per DSC resource */
2948	uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */
2949	uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */
2950	uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */
2951	uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */
2952
2953	/* Pixel Clock Control - per pipe */
2954	uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */
2955	uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */
2956	uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */
2957	uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */
2958	uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */
2959	uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */
2960	uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */
2961
2962	/* DTBCLK DTO Control - 4 DTOs */
2963	uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */
2964	uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */
2965	uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */
2966
2967	/* DP Stream Clock Control - 4 pipes */
2968	uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */
2969	uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */
2970	uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */
2971	uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */
2972
2973	/* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */
2974	uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */
2975	uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */
2976	uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */
2977
2978	/* SYMCLK32 SE Control - 4 instances */
2979	uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */
2980	uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */
2981	uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */
2982
2983	/* SYMCLK32 LE Control - 2 instances */
2984	uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */
2985	uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */
2986	uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */
2987
2988	/* DPIA Clock Control */
2989	uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */
2990	uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */
2991	uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */
2992	uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */
2993	uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */
2994	uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */
2995
2996	/* Clock Gating Control */
2997	uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */
2998	uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */
2999	uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */
3000
3001	/* VSync Control */
3002	uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */
3003	uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */
3004	uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */
3005
3006	/* Time Base Control */
3007	uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */
3008	uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */
3009	} dccg;
3010
3011	/* DSC essential configuration for underflow analysis */
3012	struct {
3013	/* DSC active state - critical for bandwidth analysis */
3014	uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */
3015
3016	/* DSC configuration affecting bandwidth and timing */
3017	uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */
3018	uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */
3019	uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */
3020
3021	/* OPP integration - affects pipeline flow */
3022	uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */
3023	uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */
3024	} dsc[MAX_PIPES];
3025
3026	/* MPC register programming variables */
3027	struct {
3028	/* MPCC blending tree and mode control */
3029	uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */
3030	uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */
3031	uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */
3032	uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */
3033	uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */
3034	uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */
3035	uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */
3036	uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */
3037
3038	/* MPCC blending tree connections */
3039	uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */
3040	uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */
3041
3042	/* MPCC output gamma control */
3043	uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */
3044	uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */
3045	uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */
3046
3047	/* MPCC pipe assignment and status */
3048	uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */
3049	uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */
3050	uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */
3051
3052	/* MPC output processing */
3053	uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */
3054	uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */
3055	} mpc;
3056
3057	/* OPP register programming variables for each pipe */
3058	struct {
3059	/* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */
3060	uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */
3061
3062	/* Format Control (FMT) - 18 fields from FMT_CONTROL register */
3063	uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */
3064	uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */
3065	uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */
3066	uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */
3067	uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */
3068	uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */
3069	uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */
3070	uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */
3071	uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */
3072	uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */
3073	uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */
3074	uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */
3075	uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */
3076	uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */
3077	uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */
3078	uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */
3079	uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */
3080	uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */
3081
3082	/* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */
3083	uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */
3084
3085	/* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */
3086	uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */
3087	uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */
3088	uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */
3089
3090	/* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */
3091	uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */
3092	uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */
3093	uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */
3094	uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */
3095	uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */
3096	uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */
3097
3098	/* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */
3099	uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */
3100	uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */
3101	uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */
3102	} opp[MAX_PIPES];
3103
3104	/* OPTC register programming variables for each pipe */
3105	struct {
3106	uint32_t otg_master_inst;
3107
3108	/* OTG_CONTROL register - 5 fields for OTG control */
3109	uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */
3110	uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */
3111	uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */
3112	uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */
3113	uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */
3114
3115	/* OTG Horizontal Timing - 7 fields */
3116	uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */
3117	uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */
3118	uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */
3119	uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */
3120	uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */
3121	uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */
3122	uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */
3123
3124	/* OTG Vertical Timing - 7 fields */
3125	uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */
3126	uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */
3127	uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */
3128	uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */
3129	uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */
3130	uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */
3131	uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */
3132
3133	/* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */
3134	uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */
3135	uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */
3136	uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */
3137	uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */
3138	uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */
3139	uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */
3140	uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */
3141	uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */
3142	uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */
3143
3144	/* OPTC Data Source and ODM - 6 fields */
3145	uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */
3146	uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */
3147	uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */
3148	uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */
3149	uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */
3150	uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */
3151
3152	/* OPTC Data Format and DSC - 4 fields */
3153	uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */
3154	uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */
3155	uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */
3156	uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */
3157	uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */
3158
3159	/* OPTC Clock and Underflow Control - 4 fields */
3160	uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */
3161	uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */
3162	uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */
3163	uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */
3164	uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */
3165
3166	/* OTG Stereo and 3D Control - 6 fields */
3167	uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */
3168	uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */
3169	uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */
3170	uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */
3171	uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */
3172	uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */
3173	uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */
3174
3175	/* OTG GSL (Global Sync Lock) Control - 5 fields */
3176	uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */
3177	uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */
3178	uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */
3179	uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */
3180	uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */
3181
3182	/* OTG DRR Advanced Control - 4 fields */
3183	uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */
3184	uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */
3185	uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */
3186	uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */
3187
3188	/* OTG DSC Position Control - 2 fields */
3189	uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */
3190	uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */
3191
3192	/* OTG Double Buffer Control - 2 fields */
3193	uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */
3194	uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */
3195
3196	/* OTG Vertical Interrupts - 6 fields */
3197	uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */
3198	uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */
3199	uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */
3200	uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */
3201	uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */
3202	uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */
3203
3204	/* OTG Global Sync Parameters - 6 fields */
3205	uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */
3206	uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */
3207	uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */
3208	uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */
3209	uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */
3210	uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */
3211
3212	/* OTG Manual Trigger Control - 11 fields */
3213	uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */
3214	uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */
3215	uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */
3216	uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */
3217	uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */
3218	uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */
3219	uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */
3220	uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */
3221	uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */
3222	uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */
3223	uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */
3224	uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */
3225
3226	/* OTG Static Screen and Update Control - 6 fields */
3227	uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */
3228	uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */
3229	uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */
3230	uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */
3231	uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */
3232	uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */
3233
3234	/* VTG Control - 3 fields */
3235	uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */
3236	uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */
3237	uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */
3238
3239	/* OTG Status (Read-Only) - 12 fields */
3240	uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */
3241	uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */
3242	uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */
3243	uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */
3244	uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */
3245	uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */
3246	uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */
3247	uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */
3248	uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */
3249	uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */
3250	uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */
3251	} optc[MAX_PIPES];
3252
3253	/* Metadata */
3254	uint32_t active_pipe_count;
3255	uint32_t active_stream_count;
3256	bool state_valid;
3257	};
3258
3259	/**
3260	* dc_capture_register_software_state() - Capture software state for register programming
3261	* @dc: DC context containing current display configuration
3262	* @state: Pointer to dc_register_software_state structure to populate
3263	*
3264	* Extracts all software state variables that are used to program hardware register
3265	* fields across the display driver pipeline. This provides a complete snapshot
3266	* of the software configuration that drives hardware register programming.
3267	*
3268	* The function traverses the DC context and extracts values from:
3269	* - Stream configurations (timing, format, DSC settings)
3270	* - Plane states (surface format, rotation, scaling, cursor)
3271	* - Pipe contexts (resource allocation, blending, viewport)
3272	* - Clock manager (display clocks, DPP clocks, pixel clocks)
3273	* - Resource context (DET buffer allocation, ODM configuration)
3274	*
3275	* This is essential for underflow debugging as it captures the exact software
3276	* state that determines how registers are programmed, allowing analysis of
3277	* whether underflow is caused by incorrect register programming or timing issues.
3278	*
3279	* Return: true if state was successfully captured, false on error
3280	*/
3281	bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state);
3282
3283	#endif /* DC_INTERFACE_H_ */
3284